MT8960 MITEL | Alldatasheet

Document overview

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Technical content

Features

  • S T - B U S compatible
  • Transmit/Receive filters & PCM Codec in one I.C
  • Meets AT&T D3/D4 and CCITT G711 and G712
  • µ-Law: MT8960/62/64/67
  • A-Law: MT8961/63/65/67
  • Low power consumption: Op.: 30 mW typ. Stby.: 2.5 mW typ.
  • Digital Coding Options: MT8964/65/66/67 CCITT Code MT8960/61/62/63 Alternative Code
  • Digitally controlled gain adjust of both filters
  • Analog and digital loopback
  • Filters and codec independently user accessible for testing
  • Powerdown mode available
  • 2.048 MHz master clock input
  • Up to six uncommitted control outputs
  • ±5V ±5% power supply

Description

Manufactured in ISO2-CMOS, these integrated filter/ codecs are designed to meet the demanding performance needs of the digital telecommunications industry, e.g., PABX, Central Office, Digital telephones.

Ordering Information

MT8964/65AC 18 Pin Ceramic DIP MT8960/61/64/65AE 18 Pin Plastic DIP MT8962/63AE 20 Pin Plastic DIP MT8962/63/66/67AS 20 Pin SOIC 0°C to+70°C Figure 1 - Functional Block Diagram ANUL VX SD0 SD1 SD2 SD3 SD4 SD5 V R VRef GNDA GNDD V DD VEE DSTo CSTi CA F1i C2i DSTi Transmit Filter Output Register Receive Filter Analog to Digital PCM Encoder PCM Digital to Analog Decoder Output Register Input Register A Register 8-Bits B-Register 8-Bits Control Logic ISSUE 10 May 1995 Integrated PCM Filter Codec ISO2-CMOS

MT8960/61/62/63/64/65/66/67ISO2-CMOS 6-20 Figure 2 - Pin Connections Pin Description Pin Name Description CSTi Control ST-BUS In is a TTL-compatible digital input used to control the function of the filter/codec. Three modes of operation may be effected by applying to this input a logic high (VDD ), logic low (GNDD), or an 8-bit serial word, depending on the logic states of CA and F1i. Functions controlled are: powerdown, filter gain adjust, loopback, chip testing, SD outputs. DSTi Data ST-BUS In accepts the incoming 8-bit PCM word. Input is TTL-compatible. C2i Clock Input is a TTL-compatible 2.048 MHz clock. DSTo Data ST-BUS Out is a three-state digital output driving the PCM bus with the outgoing 8-bit PCM word. VDD Positive power Supply (+5V). F1i Synchronization Input is an active low digital input enabling (in conjunction with CA) the PCM input, PCM output and digital control input. It is internally sampled on every positive edge of the clock, C2i, and provides frame and channel synchronization. CA Control Address is a three-level digital input which enables PCM input and output and determines into which control register (A or B) the serial data, presented to CSTi, is stored. SD3 System Drive Output is an open drain output of an N-channel transistor which has its source tied to GNDA. Inactive state is open circuit. SD4-5 System Drive Outputs are open drain outputs of N-channel transistors which have their source tied to GNDD. Inactive state is open circuit. SD0-2 System Drive Outputs are “Totempole“ CMOS outputs switching between GNDD and VDD . Inactive state is logic low. VEE Negative power supply (-5V). VX Voice Transmit is the analog input to the transmit filter. ANUL Auto Null is used to integrate an internal auto-null signal. A 0.1µF capacitor must be connected between this pin and GNDA. VR Voice Receive is the analog output of the receive filter. GNDA Analog ground (0V). VRef Voltage Reference input to D to A converter. GNDD Digital ground (0V). 10 11

20 PIN PDIP/SOIC

18 PIN CERDIP/PDIP

MT8960/61/64/65 MT8962/63/66/67

MT8960/61/62/63/64/65/66/67ISO2-CMOS 6-22 Functional Description Figure 1 shows the functional block diagram of the MT8960-67. These devices provide the conversion interface between the voiceband analog signals of a telephone subscriber loop and the digital signals required in a digital PCM (pulse code modulation) switching system. Analog (voiceband) signals in the transmit path enter the chip at V X , are sampled at 8kHz, and the samples quantized and assigned 8-bit digital values defined by logarithmic PCM encoding laws. Analog signals in the receive path leave the chip at V R after reconstruction from digital 8-bit words. Separate switched capacitor filter sections are used for bandlimiting prior to digital encoding in the transmit path and after digital decoding in the receive path. All filter clocks are derived from the 2.048 MHz master clock input, C2i. Chip size is minimized by the use of common circuitry performing the A to D and D to A conversion. A successive approximation technique is used with capacitor arrays to define the 16 steps and 8 chords in the signal conversion process. Eight-bit PCM encoded digital data enters and leaves the chip serially on DSTi and DSTo pins, respectively. Transmit Path Analog signals at the input (Vx) are firstly bandlimited to 508 kHz by an RC lowpass filter section. This performs the necessary anti-aliasing for the following first-order sampled data lowpass pre-filter which is clocked at 512 kHz. This further bandlimits the signal to 124 kHz before a fifth-order elliptic lowpass filter, clocked at 128 kHz, provides the 3.4 kHz bandwidth required by the encoder section. A 50/60 Hz third-order highpass notch filter clocked at 8 kHz completes the transmit filter path. Accumulated DC offset is cancelled in this last section by a switched-capacitor auto-zero loop which integrates the sign bit of the encoded PCM word, fed back from the codec and injects this voltage level into the non-inverting input of the comparator. An integrating capacitor (of value between 0.1 and 1 µF) must be externally connected from this point (ANUL) to the Analog Ground (GNDA). The absolute gain of the transmit filter (nominally 0 dB at 1 kHz) can be adjusted from 0 dB to 7 dB in 1 dB steps by means of three binary controlled gain pads. The resulting bandpass characteristics with the limits shown in Figure 10 meet the CCITT and AT&T recommended specifications. Typical atttenuations are 30 dB for 0-60 Hz and 35 dB for 4.6 kHz and above. The filter output signal is an 8 kHz staircase waveform which is fed into the codec capacitor array, or alternatively, into an external capacitive load of 250 pF when the chip is in the test mode. The digital encoder generates an eight-bit digital word representation of the 8 kHz sampled analog signal. The first bit of serial data stream is bit 7 (MSB) and represents the sign of the analog signal. Bits 4-6 represent the chord which contains the analog sample value. Bits 0-3 represent the step value of the analog sample within the selected chord. The MT8960-63 provide a sign plus magnitude PCM output code format. The MT8964/66 PCM output code conforms to the AT &T D3 specification, i.e., true sign bit and inverted magnitude bits. The MT8965/67 PCM output code conforms to the CCITT specifications with alternate digit inversion (even bits inverted). See Figs. 3 and 4 for the digital output code corresponding to the analog voltage, V IN, at VX input. The eight-bit digital word is output at DSTo at a nominal rate of 2.048 MHz, via the output buffer as the first 8-bits of the 125 µs sampling frame. Receive Path An eight-bit PCM encoded digital word is received on DSTi input once during the 125 µs period and is loaded into the input register. A charge proportional to the received PCM word appears on the capacitor array and an 8 kHz sample and hold circuit integrates this charge and holds it for the rest of the sampling period. The receive (D/A) filter provides interpolation filtering on the 8 kHz sample and hold signal from the codec. The filter consists of a 3.4 kHz lowpass fifth-order elliptic section clocked at 128 kHz and performs bandlimiting and smoothing of the 8 kHz "staircase" waveform. In addition, sinx/x gain correction is applied to the signal to compensate for the attenuation of higher frequencies caused by the capacitive sample and hold circuit. The absolute gain of the receive filter can be adjusted from 0 dB to -7 dB in 1 dB steps by means of three binary controlled gain pads. The resulting lowpass characteristics, with the limits shown in Figure 11, meet the CCITT and AT & T recommended specifications. Typical attenuation at 4.6 kHz and above is 30 dB. The filter is followed by a buffer amplifier which will drive 5V peak/peak into a 10k ohm load, suitable for driving electronic 2-4 wire circuits.

82 µs of the sampling cycle. DSTi input data is valid for only 3.9 µs. inactive state. T est modes cannot be entered. affecting the states of the SD outputs. output of PCM data is inhibited. Table 1. Digital Control Modes EE GNDD Normal chip operation. 2V EE Serial Eight-bit control word into Register A. Register B is reset. GNDD Serial Eight-bit control word into register A. Register B is unaffected. VDD Serial Eight-bit control word into register A. Register B is unaffected. Note 2: When operating in Mode 3, PCM input and output is inhibited by CA=VDD .

codec functions as described in Tables 2 and 3. to the sign bit of the PCM word). the data in these registers. transmit filter, receive filter and the codec function.

  • PCM input data at DSTi is latched into the PCM input register and the output of this register is connected to the input of the 3-state PCM output register.
  • The digital input to the PCM digital-to-analog decoder is disconnected, forced to zero (0).
  • The output of the PCM encoder is disabled and thus the encoded data is lost. The PCM output at DST o is determined by the PCM input data. Analog loopback is defined as follows:
  • PCM input data is latched, decoded and filtered as normal but not output at V R .

Table 2. Control States - Register A

  • Analog output buffer at VR has its input shorted to GNDA and disconnected from the receive filter output.
  • Analog input at V X is disconnected from the transmit filter input.
  • The receive filter output is connected to the transmit filter input. Thus the decode signal is fed back through the receive path and encoded in the normal way. The analog output buffer at V R is not tested by this configuration. In both cases of loopback, DSTi is the input and DSTo is the output. BIT 2 BIT 1 BIT 0 TRANSMIT (A/D) FILTER GAIN (dB) 000 0 001 + 1 010 + 2 011 + 3 100 + 4 101 + 5 110 + 6 111 + 7 BIT 5 BIT 4 BIT 3 RECEIVE (D/A) FILTER GAIN (dB) 000 0 001 - 1 010 - 2 011 - 3 100 - 4 101 - 5 110 - 6 111 - 7 BIT 7 BIT 6 FUNCTION CONTROL 0 0 Normal operation 0 1 Digital Loopback 1 0 Analog Loopback 1 1 Powerdown

MT8962/63/66/67 provides all six SD outputs. provide only four control outputs, SD0-3.

2 Wire

Table 3. Control States - Register B 0 Inactive state - logic low (GNDD). 1 Active state - logic high (VDD ). 0 Inactive state - High Impedance. 0 Inactive state - High Impedance.

ISO2-CMOS MT8960/61/62/63/64/65/66/67 6-27 Powerdown Powerdown of the chip is achieved in several ways: Internal Control: 1) Initial Power-up. Initial application of V DD and VEE causes powerdown for a period of 25 clock cycles and during this period the chip will accept input only from C2i. The B-register is reset to zero forcing SD0-5 to be inactive. Bits 0-5 of Register A (gain adjust bits) are forced to zero and bits 6 and 7 of Register A become logic high thus reinforcing the powerdown. 2) Loss of C2i. Powerdown is entered 10 to 40 µs after C2i has assumed a continuous logic high (V DD ). In this condition the chip will be in the same state as in (1) above. Note: If C2i stops at a continuous logic low (GNDD), the digital data and status is indeterminate. External Control: 1) Register A. Powerdown is controlled by bits 6 and 7 ( when both at logic high) of Register A which in turn receives its control word input via CSTi, when F1i is low and CA input is either at VEE or GNDD. Power is removed from the filters and analog sections of the chip. The analog ouput buffer at V R will be connected to GNDA. DST o becomes high impedance and the clocks to the majority of the logic are stopped. SD outputs are unaffected and may be updated as normal. 2) CSTi Input. With CA at VEE and CSTi held at continuous logic high the chip assumes the same state as described in External Control (1) above. Figure 7 - Typical Use of the Special Drive Outputs From ST-BUS From ST-BUS Master Clock to ST-BUS Alignment Register Select CSTi DSTi C2i DSTo V DD F1i CA SD3 SD2 GNDD V Ref GNDA VR ANUL VX VEE SD0 SD1 2.5V 0.1µF -5V MT8960/61/64/65 Gain Section 2/4 Wire Converter Message Waiting (With Relay Drive) Ring Feed (With Relay Drive) -100V DC Telephone Line -48V DC -48V DC 90V RMS Ring Trip Filter (With Relay Drive)

MT8960/61/62/63/64/65/66/67ISO2-CMOS 6-28 Figure 8 - Example Architecture of a Simple Digital Switching System Using the MT8960-67 DSTi DSTo CDTi VX VR SD0 SDn ... Repeated for Lines 2 to 255 Line 1 Line 256 Speech Switch 8980 Controlling Micro- Processor Control & Signalling 8980 DSTi DSTo CDTi V X VR SD0 SDn ... ••• Repeated for Lines 2 to 255 Line Interface Monitoring Circuitry Line Interface Monitoring Circuitry MT8960-67 MT8960-67

ISO2-CMOS MT8960/61/62/63/64/65/66/67 6-29 * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Note 1: T emperature coefficient of VRef should be better than 100 ppm/°C. * Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing. Absolute Maximum Ratings* Parameter Symbol Min Max Units 1 DC Supply Voltages V DD -GNDD -0.3 +6.0 V VEE -GNDD -6.0 +0.3 V

2 Reference Voltage V Ref GNDA V DD V

3 Analog Input V X VEE VDD V

4 Digital Inputs Except CA GNDD-0.3 V DD +0.3 V CA V EE -0.3 V DD +0.3 V 5 Output Voltage SD 0-2 GNDD-0.3 V DD +0.3 V SD 3 VEE -0.3 V DD +0.3 V SD 4-5 VEE -0.3 V DD +0.3 V

6 Current On Any Pin I I 20 mA

7 Storage Temperature T S -55 +125 °C

8 Power Dissipation at 25°C (Derate 16 mW/°C above 75°C) PDiss 500 mW

Recommended Operating Conditions - Voltages are with respect to GNDD unless otherwise stated Characteristics Sym Min Typ* Max Units Comments 1 Supply Voltage V DD 4.75 5.0 5.25 V VRef 2.5 V See Note 1 2 Voltage On Digital Ground VGNDD -0.1 0.0 +0.1 Vdc Ref. to GNDA duration in 125µs cycle

3 Operating Temperature T O 0+ 7 0 ° C

4 Operating Current V DD

3.0 3.0 4.0 4.0 mA mA All digital inputs at VDD or GNDD (or VEE for CA) VRef IRef 2.0 µA Mean current

5 Standby Current V DD

0.25 0.25 1.0 1.0 mA mA All digital inputs at VDD or GNDD (or VEE for CA) TA=0 to 70°C, VDD =5V±5%, VEE =-5V±5%, VRef=2.5V±0.5%, GNDA=GNDD=0V,Clock Frequency =2.048MHz. Outputs unloaded unless otherwise specified. Characteristics Sym Min Typ* Max Units Test Conditions D I G I T A L Input Current Except CA I I 10.0 µAV IN = GNDD to VDD CA I IC 10.0 µAV IN = VEE to VDD 2 Input Low Except CA V IL 0.0 0.8 V Voltage CA V ILC VEE VEE +1.2 V 3 Input High Voltage All Inputs V IH 2.4 5.0 V

4 Input Intermediate CA

VIIC 0.0 0.8 V

5 Output Leakage DSTo

Current (Tristate) SD3-5 I0Z ±0.1 10.0 µA µA Output High Impedance

MT8960/61/62/63/64/65/66/67ISO2-CMOS 6-30 Note 2: V OSIN specifies the DC component of the digitally encoded PCM word. * Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing. Characteristics Sym Min Typ* Max Units Test Conditions D I G I T A L Output Low DSTo V OL 0.4 V I OUT =1.6 mA Voltage SD 0-2 VOL 1.0 V I OUT =1 mA 7 Output High DSTo V OH 4.0 V I OUT =-100µA Voltage SD 0-2 VOH 4.0 V I OUT =-1mA 8 Output Resistance SD 3-5 R OUT 1.0 2.0 K Ω VOUT =+1V 9 Output Capacitance DSTo C OUT 4.0 pF Output High Impedance A N A L O G Input Current V X IIN 10.0 µAV EE ≤ VIN ≤ VCC 11 Input Resistance V X R IN 10.0 M Ω 12 Input Capacitance V X C IN 30.0 pF f IN = 0 - 4 kHz 13 Input Offset Voltage V X VOSIN +1.0 mV See Note 2

14 Output Resistance V R R OUT 100 Ω

15 Output Offset Voltage V R VOSOUT 100 mV Digital Input= +0

TA=0 to 70°C, VDD =5V±5%, VEE =-5V±5%, VRef=2.5V±0.5%, GNDA=GNDD=0V, Clock Frequency=2.048 MHz. Outputs unloaded unless otherwise specified. Characteristics Sym Min Typ* Max Units Test Conditions D I G I T A L Clock Frequency C2i f C 2.046 2.048 2.05 MHz See Note 3

2 Clock Rise Time C2i t CR 50 ns

3 Clock Fall Time C2i t CF 50 ns

4 Clock Duty Cycle C2i 40 50 60 %

5 Chip Enable Rise Time F1i

6 Chip Enable Fall Time F1i tEF 100 ns

7 Chip Enable Setup Time F1i tES 50 ns See Note 4

8 Chip Enable Hold Time F1i tEH 25 ns See Note 4

9 Output Rise Time DSTo t OR 100 ns

10 Output Fall Time DSTo t OF 100 ns

11 Propagation Delay Clock DSTo

ns R L=10K Ω to VCC

12 Propagation Delay DSTo

C L=100 pF

13 Input Rise Time CSTi

14 Input Fall Time CSTi

15 Input Setup Time CSTi

16 Input Hold Time CSTi

ISO2-CMOS MT8960/61/62/63/64/65/66/67 6-31 (See Figures 9a, 9b, 9c) Note 3: The filter characteristics are totally dependent upon the accuracy of the clock frequency providing F1i is synchronized to C2i. The A/D and D/A functions are unaffected by changes in clock frequency. Note 4: This gives a 75 ns period, 50 ns before and 25 ns after the 50% point of C2i rising edge, when change in F1i will give an undetermined state to to the internally synchronized enable signal. * Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing. Characteristics Sym Min Typ* Max Units Test Conditions 17 D I G I T A L Propagation Delay SD Clock to SD Output tPCS 400 ns C L = 100 pF

18 SD Output Fall Time SD t SF 200 ns C L = 20 pF

19 SD Output Rise Time SD t SR 400 ns

20 Digital Loopback

TA=0 to 70°C, VDD =5V±5%, VEE =-5V±5%, VRef=2.5V±0.5%, GNDA=GNDD=0V, Clock Frequency = 2.048MHz, Filter Gain Setting = 0dB. Outputs unloaded unless otherwise specified. Characteristics Sym Min Typ* Max Units Test Conditions A N A L O G Analog Input at VX equivalent to the overload decision level at the codec V IN 4.829 5.000 VPP VPP Level at codec: µ-Law: 3.17 dBm0 A-Law: 3.14 dBm0 See Note 6 2 Absolute Gain (0dB setting) G AX -0.25 +0.25 dB 0 dBm0 @ 1004 Hz

3 Absolute Gain (+1dB to +7dB

settings) -0.35 +0.35 dB from nominal, @ 1004 Hz 4 Gain Variation With Temp G AXT 0.01 dB T A=0°C to 70°C With Supplies G AXS 0.04 dB/V

5 Gain Tracking

(See Figure 12) CCITT G712 (Method 1) GT X1 -0.25 -0.25 -0.50 +0.25 +0.25 +0.50 dB dB dB Sinusoidal Level: +3 to -20 dBm0 Noise Signal Level: -10 to -55 dBm0 -55 to -60 dBm0 CCITT G712 (Method 2) AT&T GT -0.25 -0.50 -1.50 +0.25 +0.50 +1.50 dB dB dB Sinusoidal Level: +3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0

6 Quantization

(See Figure 13) CCITT G712 (Method 1) D QX1 28.00 35.60 33.90 29.30 14.20 dB dB dB dB dB Noise Signal Level: -3 dBm0 -6 to -27 dBm0 -34 dBm0 -40 dBm0 -55 dBm0

MT8960/61/62/63/64/65/66/67ISO2-CMOS 6-32 * Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing. Note 6: 0dBm0=1.185 V RMS for the µ-Law codec. 0dBm0=1.231 V RMS for the A-Law codec. Transmit (A/D) Path (cont’d) Characteristics Sym Min Typ* Max Units Test Conditions A N A L O G Quantization CCITT G712 Distortion (Method 2) (cont’d) AT&T (See Figure 13) D QX2 35.30 29.30 24.30 dB dB dB Sinusoidal Input Level: 0 to -30 dBm0 -40 dBm0 -45 dBm0

7 Idle Channel C-message N

CX 18 dBrnC0 µ-Law Only Noise Psophometric N PX -67 dBm0p CCITT G712

8 Single Frequency Noise N SFX -56 dBm0 CCITT G712

9 Harmonic Distortion

(2nd or 3rd Harmonic) -46 dB Input Signal: 0 dBm0 @ 1.02 kHz

10 Envelope Delay D AX 270 µs @ 1004 Hz

11 Envelope Delay 1000-2600 Hz

Variation With 600-3000 Hz Frequency 400-3200 Hz D DX 60 150 250 µs µs µs Input Signal: 400-3200 Hz Sinewave at 0 dBm0

12 Intermodulation CCITT G712

X1 -55 dB 50/60 Hz @ -23 dBm0 and any signal within 300-3400 Hz at -9 dBm0 CCITT G712 2 tone IMD X2 -41 dB 740 Hz and 1255 Hz @ -4 to -21 dBm0. Equal Input Levels AT&T IMD X3 -47 dB 2nd order products 4 tone IMD X4 -49 dB 3rd order products

13 Gain Relative to ≤50 Hz

Gain @ 1004 Hz 60 Hz (See Figure 10) 200 Hz 300-3000 Hz 3200 Hz 3300 Hz 3400 Hz 4000 Hz ≥4600 Hz G RX -1.8 -0.125 -0.275 -0.350 -0.80 -25 -30 0.00 0.125 0.125 0.030 -0.100 -14 -32 dB dB dB dB dB dB dB dB dB 0 dBm0 Input Signal Transmit Filter Response

14 Crosstalk D/A to A/D CT

RT -70 dB 0 dBm0 @ 1.02 kHz in D/A

15 Power Supply V DD

1.02 kHz 16 Overload Distortion (See Fig.15) Input frequency=1.02kHz

ISO2-CMOS MT8960/61/62/63/64/65/66/67 6-33 * Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing. TA=0 to 70°C, VDD =5V±5%, VEE =-5V±5%, VRef=2.5V±0.5%, GNDA=GNDD=0V, Clock Frequency = 2.048MHz, Filter Gain Setting = 0dB. Outputs unloaded unless otherwise specified. Characteristics Sym Min Typ* Max Units Test Conditions A N A L O G Analog output at V R equivalent to the overload decision level at codec VOUT 4.829 5.000 Vpp Vpp Level at codec: µ-Law: 3.17 dBm0 A-Law: 3.14 dBm0 R L=10 KΩ See Note 7 2 Absolute Gain (0dB setting) G AR -0.25 +0.25 dB 0 dBm0 @ 1004Hz

3 Absolute Attenuation (-1dB

to -7dB settings) -0.35 +0.35 dB From nominal, @ 1004Hz 4 Gain Variation With Temp. G ART 0.01 dB T A=0°C to 70°C With Supplies G ARS 0.04 dB/V

5 Gain T racking CCITT G712

(See Figure 12) (Method 1) GT R1 -0.25 -0.25 -0.50 +0.25 +0.25 +0.50 dB dB dB Sinusoidal Level: +3 to -10 dBm0 Noise Signal Level: -10 to -55 dBm0 -55 to -60 dBm0 CCITT G712 (Method 2) AT & T GT -0.25 -0.50 -1.50 +0.25 +0.50 +1.50 dB dB dB Sinusoidal Level: +3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0

6 Quantization CCITT G712

Distortion (Method 1) (See Fig. 13) D QR1 28.00 35.60 33.90 29.30 14.30 dB dB dB dB dB Noise Signal Level: -3 dBm0 -6 to -27 dBm0 -34 dBm0 -40 dBm0 -55 dBm0 CCITT G712 (Method 2) AT & T D QR2 36.40 30.40 25.40 dB dB dB Sinusoidal Input Level: 0 to -30 dBm0 -40 dBm0 -45 dBm0 CR 12 dBrnC0 µ-Law Only Noise Psophometric N PR -75 dBm0p CCITT G712

8 Single Frequency Noise N SFR -56 dBm0 CCITT G712

(2nd or 3rd Harmonic) -46 dB Input Signal 0 dBm0 at 1.02 kHz

10 Intermodulation CCITT G712

AT & T IMD R3 -47 dB 2nd order products 4 tone IMD R4 -49 dB 3rd order products

MT8960/61/62/63/64/65/66/67ISO2-CMOS 6-34 * Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing. Note 7: 0dBm0=1.185 V RMS for µ-Law codec and 0dBm0=1.231 VRMS for A-Law codec. Figure 9a - Timing Diagram - 125µs Frame Period Receive (D/A) Path (cont’d) Characteristics Sym Min Typ* Max Units Test Conditions A N A L O G Envelope Delay D AR 210 µs @ 1004 Hz

12 Envelope Delay 1000-2600 Hz

Variation with 600-3000 Hz Frequency 400-3200 Hz D DR 90 170 265 µs µs µs Input Signal: 400 - 3200 Hz digital sinewave at 0 dBm0

13 Gain Relative to <200 Hz

Gain @ 1004 Hz 200 Hz (See Figure 11) 300-3000 Hz 3300 Hz 3400 Hz 4000 Hz ≥4600 Hz G RR -0.5 -0.125 -0.350 -0.80 0.125 0.125 0.125 0.030 -0.100 -14.0 -28.0 dB dB dB dB dB dB dB 0 dBm0 Input Signal Receive Filter Response

14 Crosstalk A/D to D/A CT

TR -70 dB 0 dBm0 @ 1.02 kHz in A/D 1.02 kHz

16 Overload Distortion

(See Fig. 15) Input frequency=1.02 kHz AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA A AA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA A A AAA A AAA A AAA A AAA AAAA AA A AA A AA A AA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AA AA AA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AA AA AA AA C2i INPUT F1i INTERNAL ENABLE DSTo OUTPUT DSTi INPUT CA CSTi INPUT LOAD A-REGISTER LOAD B-REGISTER 125 µs 76543210 76543210

76543210 HIGH IMPEDANCE 7

(Mode 3)

ISO2-CMOS MT8960/61/62/63/64/65/66/67 6-35 Figure 9b - Timing Diagram - Output Enable Note: In typical applications, F1i will remain low for 8 cycles of C2i. However, the device will function normally as long as tES and tEH are met at each positive edge of C2i. Figure 9c - Timing Diagram - Input/Output C2i Input F1i Input DSTo Output high impedance

8 CLOCK CYCLES

(See Note) 90% 50% 10% 90% 10% tEF tES tEH tPZL tPZH tCR tCF tER tES tEH tPZLtPZH tES tEH high-Z AA AAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAA A A AA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A AA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AA AA AA AA AA AAAA AAAA A AAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAA A AAAA 90% 50% 10% 90% 50% 10% 90% 50% 10% C2i Input DSTo Output DSTi, CSTi Input tCR tCF tOR tOFtPLH tIFtIR tIH tISH tISL tPLH

ISO2-CMOS MT8960/61/62/63/64/65/66/67 6-37 Figure 12 - Variation of Gain With Input Level A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA A AAA A AAA A AAAA A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A AAAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA AAAA A A A A A A A A A A A AAAA A AAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AA AA AA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA A AAA A AAA A AAAA AAAA A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AA AA AA AAAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA AAAA A A A A A A A A A A A A AAAA A AAA A AAA A AAA A AAA A AAA AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA A AA A AA A AAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA A AA A AA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA A A A A A A AAAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA AAAA AAAA AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAAAA AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA AAAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA A AA A AA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA A A A A A A AAAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA AAAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AA A AA A AAAAAAA AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA AAAA +1.0 +0.5 +0.25 -0.25 -0.5 -1.0 5a. CCITT Method 1 CCITT End-To-End Spec Bandlimited White Noise Test Signal +1.0 +0.5 +0.25 -0.25 -0.5 -1.0 -10 0 -3 Sinusiodal Test Signal

2 Channel Spec

(dBm0) +1.5 +1.0 +0.5 -0.25 -0.5 -1.0 -1.5 +0.25 -60 -50 -40 -30 -20 -10 0 +3 CCITT End-To-End Spec (dBm0) Sinusoidal Test Signal 5b. CCITT Method 2 Gain Variation (dB)Gain Variation (dB)

MT8960/61/62/63/64/65/66/67ISO2-CMOS 6-38 Figure 13 - Signal to Total Distortion Ratio vs Input Level AAAA A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A AAAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA AAAA AAAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AA A AA A AA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AA AA AA AA AA AA AA AA AA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AA AA AA AA AA AA AA AA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA AAA AAA AAA AAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA A AAA AAAA A A A A A A A A A A A A A A A A A A A A A A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA AAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A A A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA -40 14.3 12.6 29.3 27.6 33.9 32.2 35.6 33.9 26.3 28.0 Input Level (dBm0) 6a. CCITT Method 1 -60 -50 -40 -30 -20 -10 0 24.3 25.4 30.4 36.4 36.4 29.3 35.3 35.3 22.0 27.0 33.0 33.0 Input Level (dBm0) 6b. CCITT Method 2 Signal to Total Distortion Ratio (dB) Signal to Total Distortion Ratio (dB)

MT8960/61/62/63/64/65/66/67ISO2-CMOS 6-40 NOTES: