MT8950 MITEL | Alldatasheet
Document overview
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Technical content
Features
- Transparent coding and decoding of 0 to 8, 9.6 and 19.2 kbps data
- Coding compatible to PCM voice channels at 56/64 kbps in ST-BUS format
- Automatic line polarity detection and correction
- Loopback facility for test purposes
- Selectable data formats: RZ or NRZ
- Eight user selectable modes of operation
- Low power ISO-CMOS technology
Applications
- Transparent coder/decoder for synchronous and asynchronous data
- Data terminal (RS-232C, etc.) to ST-BUS interface
- Data switching on digital PBXs
- Channel banks/TDM multiplexers
Ordering Information
MT8950AC 24 Pin Ceramic DIP 0°C to 70°C Figure 1 - Functional Block Diagram DP SCLK D R 1 D R 2 DF D X1 D X2 RxE NRZo SPi PRST NRZ/RZ Output Circuit NRZ/RZ Input Circuit Timing & Mode Control Control Register Decoder VDD Monitoring Interface Encoder Enable Logic ST-BUS Interface VSS C2i F1i CA DSTi DSTo CSTi DA SPo ISSUE 4 November 1990
Description
The MT8950 is a coder/decoder which uses the Transition Encoded Modulation (TEM) technique for encoding/decoding low speed data to and from a 56/ 64 kbps channel (equivalent to PCM Voice). The coding and decoding scheme is transparent and can accept either synchronous or asynchronous data up to 8 kbps (inclusive); at 9.6 kbps and 19.2 kbps. The MT8950 is fabricated in MITEL’s ISO-CMOS technology. MT8950 Data Codec ISO-CMOS ST-BUS FAMILY
Figure 2 - Pin Connections Pin Description Pin # Name Description 1C S T i Control ST-BUS In (TTL Input) - This ST-BUS interface pin accepts a serial input stream which loads the Control Register. The mode of operation of the device, the bits in the Violation word, and, the resetting of Data Activity (DA ) and Scan Point output (SPo) are controlled by this register. The contents of the register are updated once every ST-BUS frame when the interface is enabled. 2D S T i Data ST-BUS In (TTL Input) - Accepts the 8 bits of TEM Data when the ST-BUS interface is enabled. 3C 2 i 2.048 MHz Clock (TTL Input) - This is the input for the 2.048 MHz clock. 4 DSTo ST-BUS Output (Three-State Output) - This is the 2.048 Mbps serial output for theTEM encoded word. It is enabled when both F1i and CA are low. 5F 1 i Framing Type 1 Input (TTL Input) - This active low input, in conjunction with CA, enables the ST-BUS interface (DSTi, DSTo and CSTi). It is internally sampled on every positive edge of the C2i clock and provides frame synchronization. 6C A Control Address (TTL Input) - This active low input (in conjunction with F1i) enables the ST-BUS interface. 7D F Data Format Select (CMOS Input) - When HIGH, the Data Codec accepts and delivers the data in unipolar Return to Zero (RZ) format. When LOW, the data format is unipolar NRZ. 8R x E Received Energy Signal (Schmitt Input) - When RxE goes LOW it establishes the polarity of the input pins DX1 and DX 2 in the RZ mode. The input which received the last pulse before RxE goes LOW is established as the unipolar MARK input. RxE also enables the operation of DA and SPo outputs the loopback modes (Modes 4, 5 and 6) of the codec, RxE is forced to the LOW state internally independent of the pin condition. RxE should be exerted LOW for the duration of a data call. 9D X 1 Data Transmit 1 (Schmitt Input) - If DF= LOW, accepts data in the NRZ format. (HIGH = MARK, LOW = SPACE). If DF=HIGH, accepts active low unipolar pulses representing the digital data in the RZ format. MARK or SPACE polarity is established by the RxE input. 12 13 CSTi DSTi C2i DSTo F1i CA DF RxE DX1 DX2 NRZo VSS VDD NC PRST NC NC DR1 DR2 DA SPo SPi DP SCLK
10 D X 2 Data Transmit 2 (Schmitt Input) - If DF = LOW, accepts data pulses which are
encoded only if there is no activity on the DX1 pin - the data format and restrictions on the use of this input is explained in the text. If DF= HIGH, accepts active low unipolar pulses representing the digital data in the RZ format. MARK or SPACE polarity is established by the RxE input.
11 NRZo Non-Return to Zero Output (Open Drain Output) - The incoming data, in the RZ
format or the NRZ format , is internally converted to inverted NRZ and appears on this open drain output. This output in conjunction with the SPi input can be used for long space detection. 12 V SS Ground (0 Volt).
13 SCLK Secondary Clock (TTL Input) - This is an external clock input that determines the
timing of the Violation Word and the synchronization pulses. If these features are not to be utilized, this input can be tied to VSS .
14 DP Drive Point Output (Totem-pole Output) - This output is exerted high when the
Control Register bits b7, b6 and b5 are set to 110 (decimal 6). The operation of the Codec is normal in every other respect.
15 SPi Uncommitted Scan Point Input (Voltage Comparator Input ) - A LOW to HIGH
transition on this input causes SPo to be set LOW. This is used to detect a long SPACE condition in conjunction with NRZo (pin 11).
16 SPo Uncommitted Scan Point Output (Totem-pole Output ) - This output is set LOW
when the SPi input undergoes a LOW to HIGH transition. The SPo is reset by the presence of a logic "1" in bit b0 of Control Register. This function is active at all times except when RxE is false and during power reset conditions.
17 DA Data Activity (Totem-pole Output ) - The NRZ/RZ input circuitry monitors the
input signal (after polarity is established) and activates this output when it detects a SPACE on the input. This output is reset by the presence of a logic "1" in bit 1 of the Control Register. The DA function is active at all times except when RxE is false and during power reset conditions.
18 D R 2 Data Receive 2 (Totem-pole Output) - If DF = LOW ( NRZ format), outputs the
secondary data signal in the NRZ form as explained in the text. If DF = HIGH (RZ format), outputs unipolar, active high MARK pulses. 19 D R 1 Data Receive 1 (Totem-pole Output) - If DF = LOW (NRZ format) , outputs the NRZ data signal. ( HIGH = MARK, LOW = SPACE) If DF = HIGH (RZ format), outputs unipolar, active low SPACE pulses. 20 NC No connection. 21 NC No connection.
22 PRST
Power Reset (CMOS Schmitt Input ) - A LOW level on this input evokes the power reset condition for the codec. 23 NC No connection. 24 V DD Positive Supply Voltage +5 volts ± 10% . Pin Description (continued) Pin # Name Description
similar to many industry standard voice codecs. stream and regenerates the original digital signal. levels before being input to the codec. Table 1. Summary of Data Codec Capabilities. violation pulses can be on the MARK or SPACE line. bandwidth per channel is reduced to 56 kbps.
2 Stop Bits
Figure 3 - TEM Coding Scheme (Note: Waveforms shown are bipolar RZ equivalent of separate RZ/NRZ inputs) Table 2. TEM Coding Summary † Note: The Level bit (b7) indicates the level (HIGH or LOW) of the input data in timeslot 31 of the current frame. Level† Frame Type b6 b5 First Transition b4 b3 b2 b1 b0 Notes
1 No Pulse 1/0 1 1 1 1 1 1 1
2 2 Data Pulses (T=52 µs) 1/0 1 1 X X X X X X X X X X ≤ 10001 (17) 3 3 Data Pulses (T=52 µs) 1/0 1 1 X X X X X X X X X X ≤ 00100 (4) 4 1 Data Pulse 1/0 1 0 X X X X X X X X X X = 0 to 31
5 Violation Pulse 1/0 1 0 X X X X X X X X X X = 0 to 31
6 2 Data Pulses (T=104 µs) (Timeslot 4 to 31) 1/0 0 1 X X X X X X X X X X > 00011 (3) 7 2 Data Pulses (T=104 µs) (Timeslot 0 to 3) 1/0 0 0 Y Y Y X X XX = 0 to 3 YYY = 0 to 7 b4b3b2b1b0 b4b3b2b1b0 b4b3b2b1b0 b4b3b2b1b0 b4b3b2b1b0 b1b0 b4b3b2 b4b3b2b1b0=11111 125 µs 24 25 26 27 28 29 30 31 02322• • •0123456789 10 Internal Clock b70b7-1 Frame Type b6 b5 1 1 1 1 1 1 1 0 1 0 0 1 0 0 01234 01234567 of seven frames types are possible as shown in Figure 3. In frame type 7, the first five bits (b0 to b4)
(when the chip is operating in the local carrier mode). utilized, the SCLK input can be tied to ground. Table 3. Summary of Control Register Function 4 summarizes the different modes. as explained in the preceding paragraphs.
1 Resets the Data Activity Scan point
0 Resets the Uncommitted Scan point
Table 4. Modes of Operation time interval equal to four clock periods of SCLK. operates normally in this mode.
111 I d l e
Codec converts analog signals into the ST-BUS format while the Data Codec does a similar conversion for low speed data. The information in the ST-BUS format can be switched via the Digital Switch to any of the other interfaces and subsequently transmitted over the appropriate lines to the remote destination. At the remote end, the original signal is regenerated by another codec. The remote equipment can be part of a local area network or it may be accessed through leased T1/ CEPT digital lines. Access to remote equipment via the T1/CEPT leased lines is acquired through the T1/ CEPT interface (MT8976). Full duplex transmission at 1.544 or 2.048 Mbps is possible with this interface. The Digital Network Interface Circuit (DNIC), the MT8972, is capable of providing 160 kbps full duplex transmission over single telephone pair wiring. This device can support two 64 kbps channels, allowing two data codecs to be interfaced to it at the remote end. Simple, low cost data sets can be constructed using the data codec and the DNIC. A simplified interface for transmitting and receiving RS-232 data signals is illustrated in Figure 9. The Codec is selected to receive and transmit low speed data in the NRZ format. The data transmitted by the terminal equipment in the RS-232 format is inverted and level shifted to TTL-compatible levels before being fed into the D X 1 input on the Codec. The signal is converted into the ST-BUS format and transmitted via the DSTo output in one channel timeslot when the ST-BUS interface is enabled by F1i and CA , as dictated by the system channel assignment scheme. During this same time period the Codec accepts the 8 bit data arriving on the incoming ST-BUS stream which is output at the STo1 pin on the MT8980. The data is decoded and the original signal input at the remote end is regenerated and output at the D R 1 pin. This signal is level shifted, inverted and transmitted to the terminal. The codec in this particular application requires no other programming. Loading of the Control Register via the CSTi input is optional. If this input is tied to ground, the Codec will operate in mode 0 (the normal mode). Note that the SCL K input is ti ed low . Thus synchronization pulses will not be transmitted and Figure 9 - Simplified RS-232 Interface using the Data Codec AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AA AA AA AA AA AA AA AA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA AA AA AA AA AA AA AA AA AA AAAA AAAA AAAA AAAA AAAA AAAA A A A A A A A A A AAAAAAAAAAAAAA AA AA AA AA AA AA AA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A A A A A A A AAAAAAAAAAAAAAAAAAA AA AA AA AA AA AA R = 210 KΩ C = 1.0 µF MPU Timing Circuitry Channel Assignment Circuit Scan Point Interface AAAAAAAAAAAAAA AA AA AA AA AA AA AA AA AA AA AA AAAAAAAAAAAAAAA AA AA AA AA AA AA AA AA AA AA Digital Switch MT8980 STi3 STi1 STo0 STo1 C4i F0i Line Drivers /Receivers TxD RxD RS-232 TTL FROM DTE 12 13 CSTi DSTi C2i DSTo F1i CA DF RxE D X1 D X2 NRZo VSS VDD NC PRST NC NC D R 1 D R 2 DA SPo SPi DP SCLK + 5V R C MT8950
- Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. 1. Include DSTi, CSTi, C2i, F1i and SCLK 2. Include DF 3. Include RxE,DX1, DX 2 and PRST Absolute Maximum Ratings*- Voltages are with respect to ground (VSS ) unless otherwise stated. Parameter Symbol Min Max Units 1 Supply Voltage V DD -0.5 7.0 V 2 DC Input Voltage V IN VSS -0.3 V DD +0.3 V 3 DC Output Voltage V OUT VSS -0.3 V DD +0.3 V
4 Input Diode Current ( VI<0 or VI>V DD )I IK ± 10 mA
5 Output Diode Current ( VO <0 or VO >V DD )I OK ± 20 mA
6 DC Output Current, per pin I O ± 25 mA
7 DC Supply or Ground Current I DD /ISS ± 50 mA
8 StorageTemperature T ST -65 150 oC
9 Package Power Dissipation (CERDIP) TA= 25o CP D 1.0 W Recommended Operating Conditions - Voltages are with respect to ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions 1 Supply Voltage V DD 4.5 5.0 5.5 V 2 Operating Frequency f CK 2.048 MHz
3 Operating Temperature T A 07 0 oC
VDD =5.0V±10%; VSS =0V; TA=0oC to 70oC - Voltages are with respect to ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions S U P Quiescent Supply Current I QS 150 µA All outputs unloaded All inputs @ VSS 2 Operating supply current I DD 1.0 mA All outputs unloaded. Input pins 2 and 3 clocked at 2.048 MHz. Pins 1,8,15,20,21 @ V SS Pins 5,6,7,9,10,13 and 22 @V DD I N P U T S TTL inputs1 HIGH voltage LOW voltage VIH VIL 2.0 VSS VDD 0.8 V V
4 CMOS inputs 2
3.5 VSS VDD 1.5 V V
5 CMOS Schmitt inputs 3
3.0 VSS VDD 1.0 V V 6 SPi Comparator ON Voltage V T+ 2.25 2.5 2.75 V V DD = 5V 7 SPi Comparator OFF Voltage V T- 2.0 V V DD = 5V
8 Input Leakage Current I IN ±1 ±10 µA V DD = 5V
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Note 1: R L=10K Ω to VDD , CL=150 pF to VSS VDD =5.0V±10%; VSS =0V; TA=0oC to 70oC - Voltages are with respect to ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions O U T P U T S Output LOW voltage V OL 0.05 V | I O |< 1.0 µA VDD = 5V 2 Output HIGH Voltage V OH 4.95 V | I O |< 1.0 µA VDD = 5V
3 Output LOW Current (On all
outputs except DSTo) IOL 2.2 2.8 mA V OL =0.4V
4 Output HIGH Current (On all
outputs except DSTo) IOH -3.5 -4.2 mA V OH =2.4V
5 Output LOW Current (On
DSTo output) IOL 8.9 11.1 mA V OL =0.4V
6 Output HIGH Current (On
DSTo output) IOH -14.0 -16.8 mA V OH =2.4V
7 Output Leakage Current I OZ ±1 ±10 µA
Characteristics Sym Min Typ ‡ Max Units Test Conditions 1 C2i Clock Frequency f CK 2.028 2.048 2.068 MHz
2 C2i Clock Rise Time t CR 50 ns
3 C2i Clock Fall Time t CF 50 ns
4 Clock Duty Cycle (C2i & SCLK) 50 %
5 SCLK Clock Frequency f
SCLK 00 . 6 1 2 8 k H z
6 SCLK Clock Rise Time t SCLKR 50 ns
7 SCLK Clock Fall Time t SCLKF 50 ns
8F 1 i and CA Rise Time t ER 100 ns 9F 1 i and CA Fall Time t EF 100 ns
10 F1i and CA Setup Time t ES 25 ns
11 F1i and CA Hold Time t EH -25 25 ns
12 DSTo Rise Time t OR 100 ns Note 1
13 DSTo Fall Time t OF 100 ns Note 1
14 Propagation Delay From Clock
(C2i) To Output (DSTo) enable. tPZH tPZL 125 ns Note 1
15 Propagation Delay From Clock
(C2i) To Output (DSTo). tPLH tPHL 125 ns Note 1
16 Input Rise Time (DSTi, CSTi) t IR 100 ns
17 Input Fall Time (DSTi, CSTi) t IF 100 ns
18 DSTi, CSTi Setup Time tISH
19 DSTi, CSTi Hold Time t IH 90 ns
20 PRST Low Time 488 ns
NOTES: