MT8941BP

MT8941B MITEL | Alldatasheet

Document overview

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Technical content

Features

• Provides T1 clock at 1.544 MHz locked to an 8 kHz reference clock (frame pulse)
• Provides CEPT clock at 2.048 MHz and ST -BUS clock and timing signals locked to an internal or external 8 kHz reference clock
• Typical inherent output jitter (unfiltered)= 0.07 UI peak-to-peak
• Typical jitter attenuation at: 10 Hz=23 dB,100 Hz=43 dB, 5 to 40 kHz≥ 64 dB
• Jitter-free “FREE-RUN” mode
• Uncommitted two-input NAND gate
• Low power CMOS technology

Applications

• Synchronization and timing control for T1 and CEPT digital trunk transmission links
• ST - BUS clock and frame pulse source

Description

The MT8941B is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST -BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The timing signals for the CEPT transmission link and the ST -BUS are provided by the second PLL locked to an internal or an external 8 kHz frame pulse signal. The MT8941B offers improved jitter performance over the MT8940. The two devices also have some functional differences, which are listed in the section on “Differences between MT8941B and MT8940”.

Ordering Information

MT8941BE 24 Pin Plastic DIP (600 mil) MT8941BP 28 Pin PLCC -40°C to +85°C Figure 1 - Functional Block Diagram F0i C12i MS0 MS1 MS2 MS3 C8Kb C16i Ai Bi Yo V DD VSS RST CVb CV ENCV F0b C4b C4o ENC4o C2o C2o ENC2o 2:1 MUX Variable Clock Control Mode Selection Logic DPLL #2 Input Selector Clock Generator Frame Pulse Control

4.096 MHz

2.048 MHz

DPLL #1 DS5186 ISSUE 1 June 1999 MT8941B Advanced T1/CEPT Digital Trunk PLL CMOS ST -BUS FAMIL Y

Figure 2 - Pin Connections Pin Description Pin # Name Description DIP PLCC

11 E N CV Variable clock enable (TTL compatible input) - This input directly controls the three states

of CV (pin 22) under all modes of operation. When HIGH, enables CV and when LOW, puts it in high impedance condition. It also controls the three states of CVb signal (pin 21) if MS1 is LOW. When ENCV is HIGH, the pin CVb is an output and when LOW, it is in high impedance state. However, if MS1 is HIGH, CVb is always an input. 2 2 MS0 Mode select ‘0’ input (TTL compatible) -This input in conjunction with MS1 (pin 4) selects the major mode of operation for both DPLLs. (Refer to Tables 1 and 2.) 3 3 C12i 12.352 MHz Clock input (TTL compatible) -Master clock input for DPLL #1. 4 6 MS1 Mode select-1 input (TTL compatible) -This input in conjunction with MS0 (pin 2) selects the major mode of operation for both DPLLs. (Refer to Tables 1 and 2.) F0i Frame pulse input (TTL compatible) -This is the frame pulse input at 8 kHz. DPLL #1 locks to the falling edge of this input to generate T1 (1.544 MHz) clock.

68 F0b Frame pulse Bidirectional (TTL compatible input and Totem-pole output) -Depending

on the minor mode selected for DPLL #2, it provides the 8 kHz frame pulse output or acts as an input to an external frame pulse. 7 9 MS2 Mode select-2 input (TTL compatible) -This input in conjunction with MS3 (pin 17) selects the minor mode of operation for DPLL #2. (Refer to Table 3.) 8 10 C16i 16.384 MHz Clock input (TTL compatible) -Master clock input for DPLL #2. 91 1 E N C4o Enable 4.096 MHz clock (TTL compatible input) -This active high input enables C4o (pin 11) output. When LOW, the output C4o is in high impedance condition. 10 12 C8Kb Clock 8 kHz Bidirectional (TTL compatible input and Totem-pole output) -This is the 8 kHz input signal on the falling edge of which the DPLL #2 locks during its NORMAL mode. When DPLL #2 is in SINGLE CLOCK mode, this pin outputs an 8 kHz internal signal provided by DPLL #1 which is also connected internally to DPLL #2. 11 13 C4o Clock 4.096 MHz (Three state output) - This is the inverse of the signal appearing on pin 13 (C4b) at 4.096 MHz and has a rising edge in the frame pulse ( F0b) window. The high impedance state of this output is controlled by ENC4o (pin 9). 12 14 V SS Ground (0 Volt)

28 PIN PLCC24 PIN PDIP

13 15 C4b Clock 4.096 MHz- Bidirectional (TTL compatible input and Totem-pole output) - When the mode select bit MS3 (pin 17) is HIGH, it provides the 4.096 MHz clock output with the falling edge in the frame pulse ( F0b) window. When pin 17 is LOW,C4b is an input to an external clock at 4.096 MHz. 14 16 C2o Clock 2.048 MHz (Three state output) - This is the divide by two output of C4b (pin 13) and has a falling edge in the frame pulse (F0b) window. The high impedance state of this output is controlled by ENC2o (pin 16). 15 17 C2o Clock 2.048 MHz (Three state output) - This is the divide by two output of C4b (pin 13) and has a rising edge in the frame pulse (F0b) window. The high impedance state of this output is controlled by ENC2o (pin 16). 16 19 EN C2o Enable 2.048 MHz clock (TTL compatible input) -This active high input enables bothC2o and C2o outputs (pins 14 and 15). When LOW, these outputs are in high impedance condition. 17 20 MS3 Mode select 3 input (TTL compatible) -This input in conjunction with MS2 (pin 7) selects the minor mode of operation for DPLL #2. (Refer to Table 3.) 18, 21, Ai, BiInputs A and B (TTL compatible) -These are the two inputs of the uncommitted NAND gate 20 23 Y o Output Y (Totem pole output) -Output of the uncommitted NAND gate. 21 24 CVb Variable clock Bidirectional (TTL compatible input and Totem-pole output) -When acting as an output (MS1-LOW) during the NORMAL mode of DPLL #1, this pin provides the

1.544 MHz clock locked to the input frame pulse

F0i (pin 5). When MS1 is HIGH, it is an input to an external clock at 1.544 MHz or 2.048 MHz to provide the internal signal at 8 kHz to DPLL #2. 22 26 CV Variable clock (Three state output) -This is the inverse output of the signal appearing on pin 21, the high impedance state of which is controlled by ENCV (pin 1). 23 27 RST Reset (Schmitt trigger input) - This input (active LOW) puts the MT8941B in its reset state. To guarantee proper operation, the device must be reset after power-up. The time constant for a power-up reset circuit (see Figures 9-13) must be a minimum of five times the rise time of the power supply. In normal operation, the RST pin must be held low for a minimum of 60nsec to reset the device. 24 28 V DD VDD (+5V) Power supply. 18, NC No Connection. Pin Description (continued) Pin # Name Description DIP PLCC

The MT8941B is a dual digital phase-locked loop providing the timing and synchronization signals to the interface circuits for T1 and CEPT (30+2) Primary Multiplex Digital Transmission links. As shown in the functional block diagram (see Figure 1), the MT8941B has two digital phase-locked loops (DPLLs), associated output controls and the mode selection logic circuits. The two DPLLs, although similar in principle, operate independently to provide T1 (1.544 MHz) and CEPT (2.048 MHz) transmission clocks and ST -BUS timing signals. The principle of operation behind the two DPLLs is shown in Figure 3. A master clock is divided down to 8 kHz where it is compared with the 8 kHz input, and depending on the output of the phase comparison, the master clock frequency is corrected. Figure 3 - DPLL Principle The MT8941B achieves the frequency correction in both directions by using three methods; speed-up, slow-down and no-correction. As shown in Figure 4, the falling edge of the 8 kHz input signal (C8Kb for DPLL #2 or F0i for DPLL # 1) is used to sample the internally generated 8 kHz clock and the correction signal (CS) once in every frame (125µs). If the sampled CS is “1”, then the DPLL makes a speed-up or slow-down correction depending upon the sampled value of the internal 8 kHz signal. A sampled ”0” or “1” causes the frequency correction circuit to respectively stretch or shrink the master clock by half a period at one instant in the frame. If the sampled CS is “0”, then the DPLL makes no correction on the master clock input. Note that since the internal 8 kHz signal and the CS signal are derived from the master clock, a correction will cause both clocks to stretch or shrink simultaneously by an amount equal to half the period of the master clock. Once in synchronization, the falling edge of the reference signal (C8Kb or F0i) will be aligned with either the falling or the rising edge of CS. It is aligned with the rising edge of CS when the reference signal is slower than the internal 8 kHz signal. On the other hand, the falling edge of the Figure 4 - Phase Comparison reference signal will be aligned with the falling edge of CS if the reference signal is faster than the internal 8 kHz signal. Input-to-Output Phase Relationship The no-correction window size is 324 ns for DPLL #1 and 32 µs for DPLL #2. It is possible for the relative phase of the reference signal to swing inside the no- correction window depending on its jitter and the relative drift of the master clock. As a result, the phase relationship between the input signal and the output clocks (and frame pulse in case of DPLL #2) may vary up to a maximum of window size. This situation is illustrated in Figure 4. The maximum phase variation for DPLL #1 is 324 ns and for DPLL #2 it is 32µs. However, this phase difference can be absorbed by the input jitter buffer of Mitel’s T1/CEPT devices. The no-correction window acts as a filter for low frequency jitter and wander since the DPLL does not track the reference signal inside it. The size of the no-correction window is less than or equal to the size of the input jitter buffer on the T1 and CEPT devices to guarantee that no slip will occur in the received T1/CEPT frame. The circuit will remain in synchronization as long as the input frequency is within the lock-in range of the DPLLs (refer to the section on “Jitter Performance and Lock-in Range” for further details). The lock-in range is wide enough to meet the CCITT line rate specification (1.544 MHz±32 ppm and 2.048 MHz ±50 ppm) for the High Capacity Terrestrial Digital Service. The phase sampling is done once in a frame (8 kHz) for each DPLL. The divisions are set at 8 and 193 for DPLL #1, which locks to the falling edge of the input Master clock (12.352 MHz /

16.384 MHz)

Correction ÷ 8 Output (1.544 MHz /

2.048 MHz)

Input(8 kHz) Phase Comparison ÷ 193 / ÷ 256 C8Kb (DPLL #2) or F0i (DPLL #1) sampling edge Internal 8 kHz correction correction CS speed-up region slow-down region tCS tCSFno-correctionF0b (DPLL #2) DPLL #1: DPLL #2: tCSF = 766× TP16 where, TP12 is the 12.352 MHz master clock oscillator period for DPLL #1 and TP16 is the 16.384 MHz master clock period for DPLL #2. tCS = 4× TP12 ± 0.5× TP12 tCS = 512× TP16 ± 0.5× TP16

#2 over the entire temperature range of operation. operating mode of the MT8941B, see Tables 1 to 4. #2. There are no minor modes for DPLL #1. requires a master clock input of 12.352 MHz (C12i). operates in SINGLE CLOCK mode. and the ST -BUS clock and framing signals. RUN mode if the C8Kb pin is tied to VDD or VSS . Table 1. Major Modes of DPLL #1 Table 2. Major Modes of DPLL #2 Table 3. Minor Modes of DPLL #2 the input frame pulse (F0i). the 8 kHz input signal at C8Kb. inputs, except the master clock.

01 SINGLE

11 SINGLE

unless it is in FREE-RUN mode. compatible clock at 2.048 MHz.

4.096 MHz external clock to provide the ST -BUS

the CEPT and ST -BUS compatible timing signals. of the 8 kHz signal on C8Kb. Table 4. Summary of Modes of Operation - DPLL #1 and #2 F0b is an input but has no function in this mode. signals locked to the 8 kHz input signal (C8Kb). 4 0 1 0 0 DIVIDE-1 MODE Same as mode ‘0’. F0b is an input but has no function in this mode. 6 0 1 1 0 DIVIDE-1 MODE Same as mode 2. output is connected to DPLL #2. 8 1 0 0 0 NORMAL MODE Same as mode ‘0’. 10 1 0 1 0 NORMAL MODE Same as mode 2. external inputs except the master clock. 12 1 1 0 0 DIVIDE-2 MODE Same as mode ‘0’. F0b is an input but has no function in this mode. 14 1 1 1 0 DIVIDE-2 MODE Same as mode 2. output is connected to DPLL#2.

determined by the other mode select pins. Table 5. Functions of the Bidirectional Signals for both DPLLs of the MT8941B is shown in Figure 5.

100 Hz - 10 kHz : 20 dB/decade roll-off

the tolerance value, the larger the lock-in range. Table 6. Lock-in Range vs. Oscillator Frequency Range” for recommended oscillator tolerances for DPLL #1 & #2.

oscillators of DPLL #1 and DPLL #2 to have maximum tolerances of ±32ppm and ±50ppm respectively. However, if DPLL #1 and DPLL #2 are daisy-chained as shown in Figures 9 and 10, the output clock tolerance of DPLL #1 will be equal to that of the DPLL #2 oscillator when DPLL #2 is free-running. In this case, the oscillator tolerance of DPLL #1 has no impact on its output clock tolerance. For this reason, it is recommended to use a±32 ppm oscillator for DPLL #2 and a±100 ppm oscillator for DPLL #1. Differences between MT8941B and MT8940 The MT8941B and MT8940 are pin and mode compatible for most applications. However, the user should take note of the following differences between the two parts. Figure 8 - Application Differences between the MT8940 and MT8941B a) Distributed Timing M U X MT8940 MT8940 8 kHz Reference Signal 8 kHz Reference Signal Line Card 1 Clocks Line Card n Clocks Data Bus Line Card 1 Line Card n MT8941B M U X 8 kHz Reference Signal 8 kHz Reference Signal Clocks b) Centralized Timing Data Bus

Besides the improved jitter performance, the MT8941B differs from the MT8940 in three other areas: 1. Input pins on the MT8941B do not incorporate internal pull-up or pull-down resistors. In addition, the output configuration of the bidirectional C8Kb pin has been converted from an open drain output to a Totem-pole output. 2. The MT8941B includes a no-correction window to filter out low frequency jitter and wander as illustrated in Figure 4. Consequently, there is no constant phase relationship between reference signal F0i of DPLL # 1 or C8Kb of DPLL #2 and the output clocks of DPLL #1 or DPLL #2. Figure 4 shows the new phase relationship between C8Kb and the DPLL #2 output clocks. Figure 8 illustrates an application where the MT8941B cannot replace the MT8940 and suggests an alternative solution. 3. The MT8941B must be reset after power-up in order to guarantee proper operation, which is not the case for the MT8940. 4. For the MT8941B, DPLL #2 locks to the falling edge of the C8Kb reference signal. DPLL#2 of the MT8940 locks on to the rising edge of C8Kb. 5. While the MT8940 is available only in a 24 pin plastic DIP , the MT8941B has an additional 28 pin PLCC package option. The following figures illustrates how the MT8941B can be used in a minimum component count approach in providing the timing and synchro- nization signals for the Mitel T1 or CEPT interfaces, and the ST -BUS. The hardware selectable modes and the independent control over each PLL adds flexibility to the interface circuits. It can be easily reconfigured to provide the timing and control signals for both the master and slave ends of the link. Synchronization and Timing Signals for the T1 Transmission Link Figures 9 and 10 show examples of how to generate the timing signals for the master and slave ends of a T1 link. At the master end of the link (Figure 9), DPLL #2 is the source of the ST -BUS signals derived from the crystal clock. The frame pulse output is looped back to DPLL #1 (in NORMAL mode), which locks to it to generate the T1 line clock. The timing relationship between the 1.544 MHz T1 clock and the

2.048 MHz ST -BUS clock meets the requirements of

the MH89760/760B. The crystal clock at 12.352 MHz is used by DPLL #1 to generate the 1.544 MHz clock, while DPLL #2 (in FREE-RUN mode) uses the

16.384 MHz crystal oscillator to generate the ST -

BUS clocks for system timing. The generated ST - BUS signals can be used to synchronize the system and the switching equipment at the master end. Figure 9 - Synchronization at the Master End of the T1 Transmission Link Crystal Clock (16.384 MHz) Crystal Clock (12.352 MHz) MT8941B MS0 MS1 MS2 MS3 F0i C12i EN CV C8Kb C16i EN C4o EN C2o VSS VDD CVb C4b C2o F0b RST MH89760B C1.5i C2i F0i DSTi DSTo CSTi CSTo TxT TxR RxT RxR MT8980/81 ST-BUS SWITCH LINK (1.544 Mbps) TRANSMIT RECEIVE Mode of Operation for the MT8941B DPLL #1 - NORMAL (MS0 = X; MS1 = 0) DPLL #2 - FREE-RUN (MS0=1; MS2=1; MS3=1) VDD RC

• Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Absolute Maximum Ratings*- Voltages are with respect to ground (VSS ) unless otherwise stated. Parameter Symbol Min Max Units 1 Supply Voltage V DD -0.3 7.0 V 2 Voltage on any pin V I VSS -0.3 V DD +0.3 V

3 Input/Output Diode Current I IK/OK ±10 mA

4 Output Source or Sink Current I O ±25 mA

5 DC Supply or Ground Current I DD /ISS ±50 mA

6 Storage Temperature T ST -55 125 oC

7 Package Power Dissipation Plastic DIP

Recommended Operating Conditions - Voltages are with respect to ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions 1 Supply Voltage V DD 4.5 5.0 5.5 V 2 Input HIGH Voltage V IH 2.0 V DD V 3 Input LOW Voltage V IL VSS 0.8 V

4 Operating Temperature T A -40 25 85 oC

VDD =5.0V±5%; VSS =0V; TA=-40 to 85°C. Characteristics Sym Min Typ ‡ Max Units Test Conditions S U P Supply Current IDD 81 5 m A Under clocked condition, with the inputs tied to the same supply rail as the corresponding pull-up /down resistors. I N Input HIGH voltage (For all the inputs except pin 23) VIH 2.0 V

3 Positive-going threshold

voltage (For pin 23) V+ 3.0 4.0 V

4 Input LOW voltage (For all the

inputs except pin 23) VIL 0.8 V

5 Negative-going threshold

voltage (For pin 23) V- 1.0 1.5 V 6 O U T Output current HIGH I OH -4 mA V OH =2.4 V 7 Output current LOW I OL 4m A V OL =0.4 V

8 Leakage current on bidirect-

ional pins and all inputs except C12i, C16i, RST, MS1, MS0 IIL -100 -30 µA V IN=VSS

9 Leakage current on pins MS1,

IIL 35 120 µAV IN=VDD

10 Leakage current on all three-

state outputs and C12i, C16i, RST inputs IIL -10 ±1 +10 µAV I/O=VSS or VDD

† Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Figure 14 - Timing Information for DPLL #1 in NORMAL Mode † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. Characteristics Sym Min Typ ‡ Max Units Test Conditions D P L L CVb output (1.544 MHz) rise time t r1.5 6n s 85 pF Load 2 CVb output (1.544 MHz) fall time tf1.5 6 ns 85 pF Load 3 CVb output (1.544 MHz) clock period tP15 607 648 689 ns 4 CVb output (1.544 MHz) clock width (HIGH) tW15H 318 324 ns 5 CVb output (1.544 MHz) clock width (LOW) tW15L 277 363 ns

6 CV delay (HIGH to LOW) t 15HL 01 0 n s

7 CV delay (LOW to HIGH) t 15LH -7 3 ns

Characteristics Sym Min Typ ‡ Max Units Test Conditions D P L L C8Kb output (8kHz) delay (HIGH to HIGH) t C8HH 0 10 25 ns 85 pF Load

2 C8Kb output (8 kHz) delay

(LOW to LOW ) tC8LL 13 34 ns 85 pF Load

3 C8Kb output duty cycle 66

4 Inverted clock output delay

(HIGH to LOW ) tICHL 01 0 2 5n s

5 Inverted clock output delay

(LOW to HIGH) tICLH 0 7 18 ns CVb CV VOH VOL VOH VOL tf1.5 t15HL t15LH tr1.5 tP15 tW15H tW15L

† Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Characteristics Sym Min Typ ‡ Max Units Test Conditions D P L L C4b output clock period t P4o 213 244 275 ns 85 pF Load

2 C4b output clock width (HIGH) tW4oH 85 159 ns

3 C4b output clock width (LOW) tW4oL 116 122 ns

4 C4b output clock rise time trC4 6 ns 85 pF Load

5 C4b clock output fall time tfC4 6 ns 85 pF Load

6 Frame pulse output delay

(HIGH to LOW) fromC4b tFPL 01 3 n s 85 pF Load

7 Frame pulse output delay

(LOW to HIGH) fromC4b tFPH 08 n s 85 pF Load

8 Frame pulse ( F0b) width t WFP 225 245 ns

9 C4o delay - LOW to HIGH t 4oLH 01 5 n s

10 C4o delay - HIGH to LOW t 4oHL 02 0 n s

11 C4b to C2o delay (LOW to

HIGH) t42LH 03 n s

12 C4b to C2o delay (HIGH to

LOW) t42HL 06 n s

13 C2o clock period t P2o 457 488 519 ns 85 pF Load

14 C2o clock width ( HIGH ) t W2oH 207 280 ns

15 C2o clock width ( LOW ) t W2oL 238 244 ns

16 C2o clock rise time t rC2 6 ns 85 pF Load

17 C2o clock fall time t fC2 6 ns 85 pF Load

18 C2o delay - LOW to HIGH t 2oLH -5 2 ns

19 C2o delay - HIGH to LOW t 2oHL 057n s

† Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * Please review the section on "Jitter Performance and Lock-in Range". Figure 17 - Master Clock Inputs † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. Figure 18 - External Inputs onC4b and F0b for the DPLL #2 Characteristics Sym Min Typ ‡ Max Units Test Conditions C L O C K S Master clocks input rise time t r 10 ns

2 Master clocks input fall time tf 10 ns

3 Master clock period

(12.352MHz)* tP12 80.943 80.958 80.974 ns For DPLL #1, while operating to provide the T1 clock signal.

4 Master clock period

(16.384MHz)* tP16 61.023 61.035 61.046 ns For DPLL #2, while operating to provide the CEPT and ST-BUS timing signals.

5 Duty Cycle of master clocks 45 50 55 %

6 Lock-in Range DPLL #1

DPLL #2 -2.33 -1.69 +2.33 +1.69 Hz With the Master frequency tolerance at±32 ppm. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 F0b input pulse width (LOW) t WFP 244 ns

2 C4b input clock period t P4o 244 ns

3 Frame pulse (F0b) setup time t FS 50 ns

4 Frame pulse (F0b) hold time t FH 25 ns

2.4 V 1.5 V 0.4 V tr tf tP12 or tP16 F0b C4b VIH VIL VIH VIL tFS tWFP tFH tP4o

† Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Figure 19 - Three State Outputs and Enable Timings † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. Characteristics Sym Min Typ ‡ Max Units Test Conditions O U T P U T Delay from Enable to Output (HIGH to THREE STATE) tPHZ 16 ns 85 pF Load

2 Delay from Enable to Output

(LOW to THREE STATE) tPLZ 12 ns 85 pF Load

3 Delay from Enable to Output

(THREE STATE to HIGH) tPZH 11 ns 85 pF Load

4 Delay from Enable to Output

(THREE STATE to LOW) tPZL 50 16 ns 85 pF Load Voltages are with respect to ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Propagation delay (LOW to

HIGH), input Ai or Bi to outputtPLH 11 ns 85 pF Load

2 Propagation delay (HIGH to

LOW), input Ai or Bi to outputtPHL 15 ns 85 pF Load Enable Input Output LOW to OFF Output HIGH to OFF 10% 90% 1.3 V 1.3 V Outputs Enabled Outputs Enabled Outputs Disabled tPLZ tPHZ tPZL tPZH tf 6 ns t r 6 ns 3.0 V 2.7 V 1.3 V 0.3 V

Plastic J-Lead Chip Carrier - P-Suffix F D 1 D H I A 1 A G D 2 E Dim 20-Pin 28-Pin 44-Pin 68-Pin 84-Pin Min Max Min Max Min Max Min Max Min Max A 0.165 (4.20) 0.180 (4.57) 0.165 (4.20) 0.180 (4.57) 0.165 (4.20) 0.180 (4.57) 0.165 (4.20) 0.200 (5.08) 0.165 (4.20) 0.200 (5.08) A 1 0.090 (2.29) 0.120 (3.04) 0.090 (2.29) 0.120 (3.04) 0.090 (2.29) 0.120 (3.04) 0.090 (2.29) 0.130 (3.30) 0.090 (2.29) 0.130 (3.30) D/E 0.385 (9.78) 0.395 (10.03) 0.485 (12.32) 0.495 (12.57) 0.685 (17.40) 0.695 (17.65) 0.985 (25.02) 0.995 (25.27) 1.185 (30.10) 1.195 (30.35) D 1/E1 0.350 (8.890) 0.356 (9.042) 0.450 (11.430) 0.456 (11.582) 0.650 (16.510) 0.656 (16.662) 0.950 (24.130) 0.958 (24.333) 1.150 (29.210) 1.158 (29.413) D 2/E2 0.290 (7.37) 0.330 (8.38) 0.390 (9.91) 0.430 (10.92) 0.590 (14.99) 0.630 (16.00) 0.890 (22.61) 0.930 (23.62) 1.090 (27.69) 1.130 (28.70) F 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) G 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) H 0.050 BSC (1.27 BSC)

0.050 BSC

(1.27 BSC) (1.27 BSC) (1.27 BSC) (1.27 BSC) I 0.020 (0.51) 0.020 (0.51) 0.020 (0.51) 0.020 (0.51) 0.020 (0.51) Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) 4) For D & E add for allowable Mold Protrusion 0.010" e: (lead coplanarity) General-10

Plastic Dual-In-Line Packages (PDIP) - E Suffix NOTE: Controlling dimensions in parenthesis ( ) are in millimeters. DIM 8-Pin 16-Pin 18-Pin 20-Pin Plastic Plastic Plastic Plastic Min Max Min Max Min Max Min Max C 0.008 (0.203) 32 1 E n-2 n-1 n L D D 1 A 2 e b C eA Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) A eB eC General-8

Plastic Dual-In-Line Packages (PDIP) - E Suffix DIM 22-Pin 24-Pin 28-Pin 40-Pin Plastic Plastic Plastic Plastic Min Max Min Max Min Max Min Max eA 0.300 BSC (7.62) eB 0.430 (10.92) α 15° 15° 15° 15° 32 1 E n-2 n-1 n L D D 1 A 2 e b C eA Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) A eB α Shaded areas for 300 Mil Body Width 24 PDIP only

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