MT8940

MT8940 MITEL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 16

Technical content

Features

• Provides T1 clock at 1.544 MHz locked to input frame pulse
• Sources CEPT (30+2) Digital Trunk/ST -BUS clock and timing signals locked to internal or external 8 kHz signal
• TTL compatible logic inputs and outputs
• Uncommitted 2-input NAND gate
• Single 5 volt power supply
• Low power ISO-CMOS technology

Applications

• Synchronization and timing control for T1 and CEPT digital trunk transmission links
• ST - BUS clock and frame pulse source

Description

The MT8940 is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST -BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The timing signals for the CEPT transmission link and the ST -BUS are provided by the second PLL locked to an internal or an external 8 kHz frame pulse signal. The MT8940 is fabricated in MITEL ’s ISO-CMOS technology.

Ordering Information

MT8940AE 24 Pin Plastic DIP (600 mil) -40°C to +85°C Figure 1 - Functional Block Diagram F0i C12i MS0 MS1 MS2 MS3 C8Kb C16i Ai Bi Yo V DD VSS RST CVb CV ENCV F0b C4b C4o ENC4o C2o C2o ENC2o 2:1 MUX Variable Clock Control Mode Selection Logic DPLL #2 Input Selector Clock Generator Frame Pulse Control

4.096 MHz

2.048 MHz

DPLL #1 ISSUE 8 March 1997 MT8940 T1/CEPT Digital Trunk PLL ISO-CMOS ST -BUS FAMIL Y

Figure 2 - Pin Connections Pin Description Pin # Name Description 1E N CV Variable clock enable (TTL compatible input) - This input (pulled internally to VDD ) directly controls the three states of CV (pin 22) under all modes of operation. When HIGH, enables CV and when LOW, puts it in high impedance condition. It also controls the three states of CVb signal (pin 21) if MS1 is LOW. When EN CV is HIGH, the pin CVb is an output and when LOW, it is in high impedance state. However, if MS1 is HIGH, CVb is always an input.

2 MS0 Mode select ‘0’ input (TTL compatible) -This input (pulled internally to VSS ) in conjunction

with MS1 (pin 4) selects the major mode of operation for both DPLLs. (Refer to Tables 1 and 2). 3 C12i Clock 12.355 MHz input (TTL compatible) -Master clock input at 12.355 MHz±100ppm for DPLL #1.

4 MS1 Mode select-1 input (TTL compatible) -This input (pulled internally to V

SS ) in conjunction with MS0 (pin 2) selects the major mode of operation for both DPLLs. (Refer to Tables 1 and F0i Frame pulse input (TTL compatible) -This is the frame pulse input (pulled internally to VDD ) at 8 kHz. The DPLL #1 locks to the falling edge of this input to generate T1 (1.544 MHz) clock.

6 F0b Frame pulse Bidirectional (TTL compatible input and Totem-pole output) -Depending

on the minor mode selected for the DPLL #2, it provides the 8 kHz frame pulse output or acts as an input (pulled internally to V DD ) to an external frame pulse.

7 MS2 Mode select-2 input (TTL compatible) -This input (pulled internally to VDD ) in conjunction

with MS3 (pin 17) selects the minor mode of operation for the DPLL #2. (Refer to Table 3.) 8 C16i Clock 16.388 MHz input (TTL compatible) -Master clock input at 16.388 MHz±32 ppm for DPLL #2. 9E N C4o Enable 4.096 MHz clock (TTL compatible input) - This active high input (pulled internally to VDD ) enables C4o (pin 11) output. When LOW, the output C4o is in high impedance condition. 12 13 ENVC MS0 C12i MS1 F0i F0b MS2 C16i ENC4o C8Kb C4o VSS VDD RST CV CVb Yo Bi Ai MS3 ENC2o C2o C2o C4b

10 C8Kb Clock 8 kHz- Bidirectional (TTL compatible input and open drain output with 100K

internal resistor to VDD ) - This is the 8 kHz input signal on the rising edge of which DPLL #2 locks during its NORMAL mode. When DPLL #2 is in SINGLE CLOCK mode, this pin outputs an 8 kHz signal provided by DPLL #1, which is also connected internally to DPLL #2. 11 C4o Clock 4.096 MHz (Three state output) -This is the inverse of the signal appearing on pin 13 ( C4b) at 4.096 MHz and has a rising edge in the frame pulse (F0b) window. The high impedance state of this output is controlled by ENC4o (pin 9).

12 V SS Ground (0 Volt)

13 C4b Clock 4.096 MHz- Bidirectional (TTL compatible input and Totem-pole output) - When the mode select bit MS3 (pin 17) is HIGH, it provides the 4.096 MHz clock output with the falling edge in the frame pulse ( F0b) window. When pin 17 is LOW,C4b is an input (pulled internally to VDD ) to an external clock at 4.096 MHz. 14 C2o Clock 2.048 MHz (Three state output) - This is the divide by two output of C4b (pin 13) and has a falling edge in the frame pulse (F0b) window. The high impedance state of this output is controlled by ENC2o (pin 16). 15 C2o Clock 2.048 MHz (Three state output) - This is the divide by two output of C4b (pin 13) and has a rising edge in the frame pulse (F0b) window. The high impedance state of this output is controlled by ENC2o (pin 16). 16 EN C2o Enable 2.048 MHz clock (TTL compatible input) - This active high input (pulled internally to VDD ) enables bothC2o and C2o outputs (pins 14 and 15). When LOW, these outputs are in high impedance condition.

17 MS3 Mode select 3 input (TTL compatible) -This input (pulled internally to VDD ) in conjunction

with MS2 (pin 7) selects the minor mode of operation for DPLL #2. (Refer to Table 3.) 18,19 Ai, Bi Inputs A and B (TTL compatible) -These are the two inputs (pulled internally to VSS ) of the uncommitted NAND gate. 20 Y o Output Y (Totem pole output) -Output of the uncommitted NAND gate.

21 CVb Variable clock Bidirectional (TTL compatible input and Totem-pole output) -When

acting as an output (MS1-LOW) during the NORMAL mode of DPLL #1, this pin provides the

1.544 MHz clock locked to the input frame pulse

F0i (pin 5). When MS1 is HIGH, it is an input (pulled internally to VDD ) to an external clock at 1.544 MHz or 2.048 MHz to provide the internal signal at 8 kHz to DPLL #2.

22 CV Variable clock (Three state output) -This is the inverse output of the signal appearing on

pin 21, the high impedance state of which is controlled ENCV (pin 1).

23 RST Reset (Schmitt trigger input) -This input (active LOW) evokes reset condition for the

device. 24 V DD VDD (+5V)Power supply. Pin Description (continued) Pin # Name Description

The MT8940 is a dual digital phase-locked loop providing the timing and synchronization signals to the interface circuits for T1 and CEPT (30+2) Primary Multiplex Digital Transmission links. As shown in Figure 1, it has two digital phase-locked loops (DPLLs), associated output controls and the mode selection logic circuits. The two DPLLs, although similar in principle, operate independently to provide T1 (1.544 MHz) and CEPT (2.048 MHz) transmission clocks, and ST -BUS timing signals. The principle of operation behind the two DPLLs is shown in Figure 3. A master clock is divided down to 8 kHz where it is compared with the 8 kHz input, and depending on the output of the phase comparison, the master clock frequency is corrected. The MT8940 achieves the frequency correction in both directions by using the master clock at a slightly higher frequency and dividing it unaltered or stretching its period (at two discrete instants in a frame) before the division depending on the phase comparison output. When the input frequency is Figure 3 - DPLL Principle higher, the unchanged master clock is divided, thus effectively speeding-up the locally generated clock and eventually pulling it in synchronization with the input. If the input frequency is lower than the divided master clock, the period of the master clock is stretched by half a cycle, at two discrete instants in a phase sampling period. This introduces a total delay of one master clock period over the sampling duration, which is then divided to generate the local signal synchronous with the input. Once the output is phase-locked to the active edge of the input, the circuit will maintain the locked condition as long as the input frequency is within the lock-in range (±1.04 Hz) of the DPLLs. The lock-in range is wide enough to meet the CCITT line rate specification (1.544 MHz ±130ppm and 2.048 MHz ±50ppm) for the High Capacity Terrestrial Digital Service. The phase sampling is done once in a frame (8 kHz) and the divisions are set at 8 and 193 for DPLL #1, which locks on to the falling edge of the input at 8 kHz to generate T1 (1.544 MHz) clock. Although the phase sampling duration is the same for DPLL #2, the divisions are set at 8 and 256 to provide the CEPT/ST -BUS clock at 2.048 MHz synchronized to the rising edge of the input signal (8 kHz). The master clock source is specified to be at 12.355 MHz ±100 ppm for DPLL #1 and 16.388 MHz±32 ppm for DPLL #2 over the entire temperature range of operation. The inputs MS0 to MS3 are used to select the operating mode of the MT8940, see Tables 1 to 4. All the outputs are individually controlled to the high impedance condition by their respective enable controls. The uncommitted NAND gate is available for use in applications involving MITEL ’s MT8976/MH89760 (T1 interfaces) and MT8979/MH89790 (CEPT interfaces). Modes of Operation The operation of the MT8940 is categorized into major and minor modes. The major modes are defined for both DPLLs by the mode select pins MS0 and MS1. The minor modes are selected by MS2 and MS3, and are applicable only to DPLL #2. There are no minor modes for DPLL #1. Major modes of the DPLL #1 DPLL #1 can be operated in three major modes as selected by MS0 and MS1 (Table 1). When MS1 is LOW, it is in NORMAL mode, which provides a T1 (1.544 MHz) clock signal locked to the falling edge of the input frame pulse F0i (8 kHz). DPLL#1 requires a master clock input of 12.355 MHz±100 ppm (C12i). In the second and third major modes (MS1 is HIGH), DPLL #1 is set to DIVIDE an external 1.544 MHz or 2.048 MHz signal applied at CVb (pin 21). The division can be set by MS0 to be either 193 (LOW) or 256 (HIGH). In these modes, the 8 kHz output is connected internally to DPLL #2, which operates in SINGLE CLOCK mode. Major modes of the DPLL #2 There are four major modes for DPLL #2 selectable by MS0 and MS1, as shown in Table 2. In all these modes DPLL #2 provides the CEPT PCM 30 timing, and the ST -BUS clock and framing signals. In NORMAL mode, DPLL #2 provides the CEPT and ST -BUS compatible timing signals locked to the rising edge of the 8 kHz input signal (C8Kb). These Master Clock (12.355 MHz/

16.388 MHz)

Correction ÷8 Output (1.544 MHz / Input (8 kHz) Phase Comparison ÷193 / ÷256

2.048 MHz)

2.048 MHz (C2o andC2o) clocks, and the 8 kHz

Table 1. Major Modes of the DPLL #1 compatible to the ST -BUS format without any jitter. inputs except the master clock set at 16.388 MHz. timing signals compatible to the ST -BUS format. the CEPT and ST -BUS compatible timing signals. of the 8 kHz signal on C8Kb. Table 2. Major Modes of the DPLL #2 major modes as selected by MS0 and MS1.

4.096 MHz on

(F0b) compatible with the ST -BUS format. Table 3. Minor Modes of the DPLL #2 depending on the major mode selected.

4.096 MHz clock and 8 kHz frame pulse to

at 2.048 MHz and 8 kHz, respectively.

select pins MS0, MS1 and MS3. Table 4. Summary of Modes of Operation - DPLL #1 and #2 F0b is an input but has no function in this mode. signals locked to the 8 kHz input signal (C8Kb). 4 0100 DIVIDE-1 MODE Same as mode ‘0’. 6 0110 DIVIDE-1 MODE Same as mode 2. output is connected to DPLL #2. 8 1000 NORMAL MODE Same as mode ‘0’. 10 1010 NORMAL MODE Same as mode 2. external inputs except the master clock. 12 1100 DIVIDE-2 MODE Same as mode ‘0’. 14 1110 DIVIDE-2 MODE Same as mode 2. output is connected to DPLL#2.

The following figures illustrate how the MT8940 can be used in a minimum component count approach to providing the timing and synchronization signals for the Mitel T1 and CEPT interfaces, and the ST -BUS. The hardware selectable modes and the independent control over each PLL adds flexibility to the interface circuits. It can be easily reconfigured to provide the timing and control signals for both at the master and slave ends of the link. Synchronization and Timing Signals for the T1 Transmission Link Figures 4 and 5 show examples of how to generate the timing signals for the master and slave ends of a T1 link. At the master end of the link (Figure 4), DPLL #2 is the source of the ST -BUS signals derived from the 4.096 MHz system clock. The frame pulse output is looped back to DPLL #1 (in NORMAL mode), which locks to it to generate the T1 line clock. The timing relationship between the 1.544 MHz T1 clock and the

2.048 MHz ST -BUS clock meets the requirements of

the MH89760/760B. The crystal clock at 12.355 MHz is used by DPLL #1 to generate the 1.544 MHz clock, while DPLL #2 uses the 4.096 MHz system clock to provide the ST -BUS timing signals. The ST -BUS signals can also be obtained from DPLL #2 in FREE- RUN mode, using a crystal clock at 16.388 MHz instead of 4.096 MHz system clock. The uncommitted NAND gate converts the received signals, RxA and RxB of the MH89760 to a single Return to Zero (RZ) input for the clock extraction circuits of the MH89760. This is not required for the MH89760B. The generated ST -BUS signals can be used to synchronize the system and the switching equipment at the master end. At the slave end of the link (Figure 5) both the DPLLs are in NORMAL mode with DPLL #2 providing the ST -BUS timing signals locked to the 8 kHz frame pulse (E8Ko) extracted from the received signal on the T1 line. The regenerated frame pulse is looped back to DPLL #1 to provide the T1 line clock as at the master end. The 12.355 MHz and 16.388 MHz crystal clock sources are necessary for DPLL #1 and #2. Synchronization and Timing Signals for the CEPT Transmission Link The MT8940 can be used to provide the timing and synchronization signals for the MH89790/790B, MITEL ’s CEPT(30+2) digital trunk interface hybrid. Since the operational frequencies of the ST -BUS and the CEPT primary multiplex digital trunk are same, only DPLL #2 is required to achieve synchronization between the two Figures 6 and 7 show how the MT8940 can be used to synchronize the ST -BUS and the CEPT transmission link at the master and slave ends, respectively. Figure 4 - Synchronization at the Master End of the T1 Transmission Link Crystal Clock (12.355 MHz ±100 ppm) (ST-BUS compatible) MT8940 MS0 MS1 MS2 MS3 F0i C12i EN CV C8Kb C16i EN C4o EN C2o Ai Bi VSS VDD CV C4b C2o F0b Yo RST MH89760 C1.5i C2i F0i RxA RxB RxD DSTi DSTo CSTi CSTo TxT TxR RxT RxR MT8980/81 ST-BUS SWITCH LINK (1.544 Mbps) TRANSMIT RECEIVE MODE OF OPERATION FOR THE MT8940 DPLL #1 - NORMAL (MS0 = X; MS1 = 0) DPLL #2 - OVERRIDE THE MAJOR MODES (MS2 = 1; MS3 = 0)

Figure 5 - Synchronization at the Slave End of the T1 Transmission Link Figure 6 - Synchronization at the Master End of the CEPT Digital Transmission Link Crystal Clock (12.355 MHz ± 100 ppm) MT8940 MS0 MS1 MS2 MS3 F0i C12i EN CV C8Kb C16i EN C4o EN C2o Ai Bi VSS VDD CV C4b C2o F0b Yo RST MH89760 C1.5i C2i F0i RxA RxB RxD DSTi DSTo CSTi CSTo TxT TxR RxT RxR MT8980/81 ST-BUS SWITCH LINK (1.544 Mbps) Mode of Operation for the MT8940 DPLL #1 - NORMAL (MS1=0) DPLL #2 - NORMAL (MS0=0; MS1=0; MS2=1; MS3=1) Crystal Clock (16.388 MHz ± 32 ppm) TRANSMIT RECEIVE MT8940 MS0 MS1 MS2 MS3 F0i C12i EN CV C8Kb C16i EN C4o EN C2o Ai Bi VSS VDD C4b C2o F0b Yo RST MH89790 C2i F0i RxA RxB RxD DSTi DSTo CSTi0 CSTi1 CSTo OUTA OUTB RxT TRANSMIT RECEIVE MT8980/81 ST-BUS SWITCH RxR CEPT PRIMARY MULTIPLEX DIGITAL LINK (ST-BUS Compatible) Mode of Operation for the MT8940 DPLL #1 - NOT USED DPLL #2 - OVERRIDE MAJOR MODES (MS0=X; MS1=X MS2=1; MS3=0) Generation of ST-BUS Timing Signals The MT8940 can source the properly formatted ST - BUS timing and control signals with no external inputs except the crystal clock. This can be used as the standard timing source for ST -BUS systems or any other system with similar clock requirements. Figure 8 shows two such applications using only DPLL #2. In one case, the MT8940 is in FREE-RUN mode with an oscillator input of 16.388 MHz. This forces the DPLL to correct at a rate of 4 kHz to maintain the ST -BUS clocks, which therefore, will be jittered. In the other case, the oscillator input is

16.384 MHz (exactly eight times the output

frequency) and DPLL #2 operates in NORMAL mode with C8Kb input tied HIGH. Since no corrections are necessary, the output is free from jitter. DPLL #1 is completely free in both cases and available for any other purpose.

• Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Absolute Maximum Ratings*- Voltages are with respect to ground (VSS ) unless otherwise stated. Parameter Symbol Min Max Units 1 Supply Voltage V DD -0.3 7.0 V 2 Voltage on any pin V I VSS -0.5 V DD +0.5 V

3 Input/Output Diode Current I IK/OK ±10 mA

4 Output Source or Sink Current I O ±25 mA

5 DC Supply or Ground Current I DD /ISS ±50 mA

6 Storage Temperature T ST -65 150 oC

7 Package Power Dissipation LCC P D 600 mW

Recommended Operating Conditions - Voltages are with respect to ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions 1 Supply Voltage V DD 4.75 5.0 5.25 V 2 Input HIGH Voltage V IH 2.4 V DD V For 400 mV noise margin 3 Input LOW Voltage V IL VSS 0.4 V For 400 mV noise margin

4 Operating Temperature T A -40 25 85 oC

VDD =5.0 V±5%; VSS =0V; TA=-40 to 85°C. Characteristics Sym Min Typ ‡ Max Units Test Conditions S U P Supply Current IDD IDDS 81 5 100 mA Under clocked condition, with the inputs tied to the same supply rail as the corresponding pull-up / down resistors. I N Input HIGH voltage (For all the inputs except pin 23) VIH 2.0 V

3 Positive-going threshold

voltage (For pin 23) V+ 2.8 V

4 Input LOW voltage (For all the

inputs except pin 23) VIL 0.8 V

5 Negative-going threshold

voltage (For pin 23) V- 1.5 V O U T Output current HIGH (For all the outputs except pin 10) IOH -9.5 mA V OH =2.4 V

7 Output current LOW (For all the

outputs except pin 10) IOL 4.5 mA V OL =0.4 V 8 Output current LOW (pin 10) I OL 2.0 mA V OL =0.4 V

9 Leakage current on bidirect-

ional pins and all inputs except C12i, C16i, RST IIZ/OZ ±150 µAV I/O=VSS or VDD

10 Leakage current on all outputs

and C12i, C16i,RST inputs IIZ/OZ ±1 ±10 µAV I/O=VSS or VDD

† Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Figure 9 - Timing Information for DPLL #1 in NORMAL Mode † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. Characteristics Sym Min Typ ‡ Max Units Test Conditions D P L L Frame pulse input ( F0i) to CVb output (1.544 MHz) delay tF15H -40 75 ns 2 CVb output (1.544 MHz) rise time tr1.5 10 15 ns Test load circuit 1 (Fig. 17). 3 CVb output (1.544 MHz) fall time tf1.5 12 15 ns Test load circuit 1 (Fig. 17). 4 CVb output (1.544 MHz) clock period tP15 648 690 ns 5 CVb output (1.544 MHz) clock width (HIGH) tW15H 320 386 ns 6 CVb output (1.544 MHz) clock width (LOW) tW15L 314 327 ns

7 CV delay (HIGH to LOW) t 15HL 53 0n s

8 CV delay (LOW to HIGH) t 15LH -12 10 ns

Characteristics Sym Min Typ ‡ Max Units Test Conditions D P L L C8Kb output (8kHz) delay (HIGH to HIGH) t C8HH 130 ns Test load circuit 2 (Fig. 17).

2 C8Kb output (8 kHz) delay

(LOW to LOW) tC8LL 50 130 ns Test load circuit 2 (Fig. 17).

3 C8Kb output duty cycle 66

4 Inverted clock output delay

(HIGH to LOW) tICHL 40 75 ns

5 Inverted clock output delay

(LOW to HIGH) tICLH 35 60 ns F0i CVb CV VIH VIL VOH VOL VOH VOL tF15H tf1.5 t15HL t15LH tr1.5 tP15 tW15H tW15L

† Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Figure 12 - ST-BUS Timings from DPLL #2 and C8Kb Input/Output Characteristics Sym Min Typ ‡ Max Units Test Conditions D P L L C4b output delay (HIGH to LOW) from C8Kb input/output t84H -25 75 ns Test load circuit 2 (Fig. 17) on C8Kb. 2 C4b output clock period t P4o 240 282 ns Test load circuit 1 (Fig. 17).

3 C4b output clock width (HIGH) tW4oH 123 165 ns

4 C4b output clock width (LOW) tW4oL 110 123 ns

5 C4b output clock rise time trC4 10 ns Test load circuit 1 (Fig. 17). 6 C4b clock output fall time tfC4 10 ns Test load circuit 1 (Fig. 17).

7 Frame pulse output delay

(HIGH to LOW) fromC4b tFPL 50 ns Test load circuit 1 (Fig. 17).

8 Frame pulse output delay

(LOW to HIGH) fromC4b tFPH 40 ns Test load circuit 1 (Fig. 17).

9 Frame pulse ( F0b) width t WFP 200 245 ns

10 C4o delay - LOW to HIGH t 4oLH 45 ns

11 C4o delay - HIGH to LOW t 4oHL 45 ns

12 C4b to C2o delay (LOW to

HIGH) t42LH -10 +10 ns

13 C4b to C2o delay (HIGH to

LOW) t42HL 20 ns 14 C2o clock period t P2o 486 523 ns Test load circuit 1 (Fig. 10).

15 C2o clock width (HIGH) t W2oH 244 291 ns

16 C2o clock width (LOW) t W2oL 233 244 ns

17 C2o clock rise time t rC2 10 ns Test load circuit 1 (Fig. 10). 18 C2o clock fall time t fC2 10 ns Test load circuit 1 (Fig. 10).

19 C2o delay - LOW to HIGH t 2oLH 20 ns

20 C2o delay - HIGH to LOW t 2oHL -5 30 ns

† Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Figure 13 -F0b from DPLL #2 is Looped Back as Input to DPLL #1 (T1 Line synchronized to ST-BUS) † Timing is over recommended temperature & power supply voltages ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Figure 14 - Master Clock Inputs Characteristics Sym Min Typ ‡ Max Units Test Conditions 1 CV/CVb (1.544 MHz) Setup time t S15 25 ns 2 CV/CVb (1.544 MHz) Hold time t H15 110 ns Characteristics Sym Min Typ ‡ Max Units Test Conditions C L O C K S Master clocks input rise time tr 10 ns

2 Master clocks input fall time t f 10 ns

3 Master clock period

(12.355MHz) tP12 80.930 80.938 80.946 ns For DPLL #1, while operating to provide the T1 clock signal.

4 Master clock period

(16.388MHz) tP16 61.018 61.020 61.022 ns For DPLL #2, while operating to provide the CEPT and ST-BUS timing signals.

5 Duty Cycle of master clocks 45 50 55 %

6 Lock-in Range (For each PLL) -1.5 +1.04 Hz With the Master clocks as shown above. F0b C2o CV CVb VOH VOL VOH VOL VOH VOL VOH VOL tS15 tH15 Boundary between ST-BUS channel 2 bit 4 and channel 2 bit 3

20 CYCLES

2.4 V 1.5 V 0.4 V tr tf tP12 or tP16

† Timing is over recommended temperature & power supply voltages ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Figure 15 - External Inputs onC4b and F0b for the DPLL #2 † Timing is over recommended temperature & power supply voltages ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Figure 16 - Three State Outputs and Enable Timings Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 F0b input pulse width (LOW) t WFP 40 ns

2 C4b input clock period t P4o .080 50 µs

3 Frame pulse (F0b) setup time t FS 25 ns

4 Frame pulse (F0b) hold time t FH 5n s

Characteristics Sym Min Typ ‡ Max Units Test Conditions O U T P U T Delay from Enable to Output (HIGH to THREE STATE) tPHZ 15 65 ns Test load circuit 3 (Fig.17)

2 Delay from Enable to Output

(LOW to THREE STATE) tPLZ 10 55 ns Test load circuit 3 (Fig.17)

3 Delay from Enable to Output

(THREE STATE to HIGH) tPZH 40 ns Test load circuit 3 (Fig.17)

4 Delay from Enable to Output

(THREE STATE to LOW) tPZL 50 ns Test load circuit 3 (Fig.17) F0b C4b VIH VIL VIH VIL tFS tWFP tFH tP4o Enable Input Output LOW to OFF Output HIGH to OFF t f 6 ns t r 6 ns 10% 90% 1.3 V 1.3 V Outputs Enabled Outputs Enabled Outputs Disabled 3.0 V 2.7 V 1.3 V 0.3 V tPLZ tPHZ tPZL tPZH

† Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Figure 17 - Test Load Circuits Voltages are with respect to ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Propagation delay (LOW to

HIGH), input Ai or Bi to outputtPLH 25 40 ns Test load circuit 1 (Fig. 17)

2 Propagation delay (HIGH to

LOW), input Ai or Bi to outputtPHL 20 40 ns Test load circuit 1 (Fig. 17) From output under test Test point C L=50pF Test load circuit- 1 VDD R L=1kΩ Test point From output under test Test load circuit- 2 Test load circuit- 3 From output under test C L=50pFC L=50pF Test point VDD VSS R L=1kΩ Note: S1 is in position A when measuring tPLZ and tPZ and in position B when measuring tPHZ and tPZH A B