MT8931CE

MT8931C ZARLINK | Alldatasheet

Document overview

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Technical content

Features

ETS 300-012, CCITT I.430 and ANSI T1.605 S/T interface
Full-duplex 2B+D, 192 kbit/s transmission
Link activation/deactivation
D-channel access contention resolution
Point-to-point, point-to-multipoint and star configurations
Master (NT)/Slave (TE) modes of operation
Exceeds loop length requirements
Complete loopback testing capabilities
On chip HDLC D-channel protocoller
8 bit Motorola/Intel microprocessor interface
Microprocessor-controlled operation
Zarlink ST-BUS interface
Low power CMOS technology
Single 5 volt power supply

Applications

ISDN NT1
ISDN S or T interface
ISDN Terminal Adaptor (TA)
Digital sets (TE1) - 4 wire ISDN interface
Digital PABXs, Digital Line Cards (NT2)

Description

The MT8931C Subscriber Network Interface Circuit (SNIC) implements the ETSI ETS 300-012, CCITT I.430 and ANSI T1.605 Recommendations for the ISDN S and T reference points. Providing point-to- point and point-to-multipoint digital transmission, the SNIC may be used at either end of the subscriber line (NT or TE). An HDLC D-channel protocoller is included and controlled through a Motorola/Intel microprocessor port. The MT8931C is fabricated in Zarlink’s CMOS process. Figure 1 - Functional Block Diagram DSTi DSTo F0od C4b F0b STAR/Rsto XTAL1/NT XTAL2/NC LTx VBias LRx VDD VSS ST-BUS Interface Timing and Control D-channel Priority Mechanism PLL HDLC Transceiver S-Bus Link Interface Link Activation Controller Microprocessor Interface Rsti HALF AD0-7 R/W /WR DS/RD AS/ALE CS IRQ/NDA

Ordering Information

MT8931CE 28 Pin Plastic DIP MT8931CP 44 Pin PLCC -40°C to +85°C ISSUE 4 November 1997 MT8931C Subscriber Network Interface Circuit CMOS ST-BUS FAMILY Data Sheet

Figure 2 - Pin Connections Pin Description Pin # Name Description DIP PLCC

12 H A L F HALF Input/Output: this is an input in NT mode and an output in TE mode identifying

which half of the S-interface frame is currently being written/read over the ST-BUS (HALF = 0 sampled on the falling edge of C4b within the frame pulse low window, identifies the information to be transmitted/received in the first half of the S-Bus frame while HALF=1 identifies the information to be transmitted/received into the second half of the S-Bus frame). Tying this pin to V SS or VDD in NT mode will allow the device to free run. This signal can also be accessed from the ST-BUS C-channel. 23 C 4 b 4.096 MHz Clock: a 4.096 MHz ST-BUS Data Clock input in NT mode. In TE mode an output 4.096 MHz clock phase-locked to the line data signal.

34 F 0 b Frame Pulse: an active low frame pulse input indicating the beginning of active ST-

BUS channel times in NT mode. Frame pulse output in TE mode.

47 F 0 o d Delayed Frame Pulse Output: an active low delayed frame pulse output indicating

the end of active ST-BUS channels for this device. Can be used to daisy chain to other ST-BUS devices to share an ST-BUS stream.

58 D S T i Data ST-BUS Input: a 2048 kbit/s serial PCM/data ST-BUS input with D, C, B1, and B2

channels assigned to the first four timeslots. These channels contain data to be transmitted on the line and chip control information.

69 D S T o Data ST-BUS Output: a 2048 kbit/s serial PCM/data ST-BUS output with D, C, B1 and

B2 channels assigned to the first four timeslots, respectively. The remaining timeslots are placed into high impedance. These channels contain data received from the line and chip status information. 7 13 XTAL2/IC Crystal 2/Internal Connection: in TE mode, XTAL1 and XTAL2 are to be connected to an external 4.096 MHz parallel resonant crystal for the on-chip oscillator. If XTAL1 is connected directly to a 4.096 MHz clock, this pin must be left unconnected. In NT mode, this pin must be left unconnected. 81 4 X T A L 1 / N T Crystal 1/Network Termination Mode Select Input: for TE mode mode selection, a 4.096 MHz crystal is to be connected between the XTAL1 and XTAL2 pins, or a 4.096 MHz clock can be connected directly to XTAL1. For NT mode selection, this pin must be tied to VDD. A pull-up resistor is needed when driven by a TTL device. 14 15 HALF C4b F0b F0od DSTi DSTo XTAL2/NC XTAL1/NT R/W/WR DS/RD AS/ALE CS IRQ/NDA VSS VDD VBias LTx LRx STAR/Rsto Rsti AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

28 PIN PDIP

44 PIN PLCC

16 5 4 3 2 4 44 34 24 1 40 2318 19 20 21 22 24 25 26 27 28 17 29

91 6 R / W /WR Read/Write or Write Input: defines the data bus transfer as a read (R/W=1) or a write (R/W=0) in Motorola bus mode. Redefined to WR in Intel bus mode. 10 17 DS/RD Data Strobe/Read Input: active high input indicates to the SNIC that valid data is on the bus during a write operation or that the SNIC must output data during a read operation in Motorola bus mode. Redefined to RD in Intel bus mode. 11 19 AS/ALE Address Strobe/Address Latch Enable Input: in Motorola bus mode the falling edge is used to strobe the address into the SNIC during microprocessor access. Redefined to ALE in Intel bus mode. 12 20 CS Chip Select Input: active low, used to select the SNIC for microprocessor access. 13 21 IRQ NDA Interrupt Request (Open Drain Output): an output indicating an unmasked HDLC interrupt. The interrupt remains active until the microprocessor clears it by reading the HDLC Interrupt Status Register. This interrupt source is enabled with B2=0 of Master Control Register. New Data Available (Open Drain Output): an active low output signal indicating availability of new data from the S-Bus. This signal is selected with B2=1 of Master Control Register. This pin must be tied to V DD with a 10kΩ resistor. 14 22 V SS Ground. 15- 24-26, 30-32, 34-35 AD0-7 Bidirectional Address/Data Bus: electrically and logically compatible to either Intel or Motorola micro-bus specifications. If DS/RD is low on the rising edge of AS/ALE then the chip operates to Motorola specs. If DS/RD is high on the rising edge of AS/ALE Intel mode is selected. Taking Rsti low sets Motorola mode. 23 37 Rsti Reset Input: Schmitt trigger reset input. If ’0’, sets all control registers to the default conditions, resets activation state machines to the deactivated state, resets HDLC, clears the HDLC FIFO‘s. Sets the microport to Motorola bus mode. 24 38 STAR/Rsto Star/Reset (Open Drain Output): 192kbit/s Rx data output fixed relative to the ST-BUS timebase. A group of NTs, in fixed timing mode, can be wire or’ed together to create a Star configuration. Active low reset output in TE mode indicating 128 consecutive marks have been received. Can be connected directly to Rsti to allow NT to reset all TEs on the bus. This pin must be tied to VDD with a 10 kΩ resistor. 25 40 LRx Receive Line Signal Input: this is a high impedance input for the pseudoternary line signal to be connected to the line through a 2:1 ratio transformer. See Figures 20 and 21. A DC bias level on this input equal to V Bias must be maintained. 26 42 LTx Transmit Line Signal Output: this is a current source output designed to drive a nominal 50 ohm line through a 2:1 ratio transformer. See Figures 20 and 21. 27 43 V Bias Bias Voltage: analog ground for Tx and Rx transformers. This pin must be decoupled to VDD through a 10µF capacitor with good high frequency characteristics. 28 44 V DD Power Supply Input. 1,5-6,10- 12,15,18, 23,27-29, 33, 36, 39, 41 NC No Connection. Pin Description (continued) Pin # Name Description DIP PLCC

The MT8931C Subscriber Network Interface Circuit (SNIC) is a multifunction transceiver providing a complete interface to the S/T Reference Point as specified in ETS 300-012, CCITT Recommendation I.430 and ANSI T1.605. Implementing both point-to-point and point-to-multipoint voice/data transmission, the SNIC may be used at either end of the digital subscriber loop. A programmable digital interface allows the MT8931C to be configured as a Network Termination (NT) or as a Terminal Equipment (TE) device. The SNIC supports 192 kbit/s (2B+D + overhead) full duplex data transmission on a 4-wire balanced transmission line. Transmission capability for both B and D channels, as well as related timing and synchronization functions, are provided on chip. The signalling capability and procedures necessary to enable customer terminals (TEs) to be activated and deactivated, form part of the MT8931C’s functionality. The SNIC handles D-channel resource allocation and prioritization for access contention resolution and signalling requirements in passive bus line configurations. Control and status information allows implementation of mainten-ance functions and monitoring of the device and the subscriber loop. An HDLC transceiver is included on the SNIC for link access protocol handling via the D-channel. Depacketized data is passed to and from the transceiver via the microprocessor port. Two 19 byte deep FIFOs, one for transmit and one for receive, are provided to buffer the data. The HDLC block can be set up to transmit or receive to/from either the S-interface port or the ST-BUS port. Further, the transmit destination and receive source can be independently selected, e.g., transmit to S-interface while receiving from ST-BUS. The transmit and receive paths can be separately enabled or disabled. Both, one and two byte address recognition is supported by the SNIC. A transparent mode allows data to be passed directly to the D channel without being packetized. A block diagram of the MT8931C is shown in Figure 1. The SNIC has three interface ports: a 4-wire CCITT compatible S/T interface (subscriber loop interface), a 2048 kbit/s ST-BUS serial port, and a general purpose parallel microprocessor port. This 8-bit parallel port is compatible with both Motorola or Intel microprocessor bus signals and timing. The three major blocks of the MT8931C, consisting of the system serial interface (ST-BUS), HDLC transceiver, and the digital subscriber loop interface (S-interface) are interconnected by high speed data busses. Data sent to and received from the S-interface port (B1, B2 and D channels) can be accessed from either the parallel microprocessor port or the serial ST-BUS port. This is also true for SNIC control and status information (C-channel). Depacketized D-channel information to and from the HDLC section can only be accessed through the parallel microprocessor port. S-Bus Interface The S-Bus is a four wire, full duplex, time division multiplexed transmission facility which exchanges information at 192 kbit/s rate including two 64 kbit/s PCM voice or data channels, a 16 kbit/s signalling channel and 48 kbit/s for synchronization and overhead. The relative position of these channels with respect to the ST-BUS is shown in Figures 4 and 5. The SNIC makes use of the first four channels on the ST-BUS to transmit and receive control/status and data to and from the S-interface port. These are the B, D and C-channels (see Figure 4). Figure 3 - SNIC Pin Connections 14 15 HALF C4bi F0bi F0od DSTi DSTo Cmode NT R/W/WR DS/RD AS/ALE CS IRQ/NDA VSS VDD VBias LTx LRx STAR Rsti AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 14 15 HALF C4bo F0bo F0od DSTi DSTo XTAL2 XTAL1 R/W /WR DS/RD AS/ALE CS IRQ/NDA VSS VDD VBias LTx LRx Rsto Rsti AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NT MODE TE MODE

Figure 5 - S-Bus Frame Structure and Functional Timing F = Framing bit L = DC balancing bit D = Bit within D-channel E = D-echo channel bit Fa & N (NT to TE) = Auxiliary framing bits Fa (TE to NT) = Auxiliary framing bit or Q-channel bit B1 = Bit within B1-channel B2 = Bit within B2-channel A = Activation bit M = Multiframing bit S = S-channel bit B1 B1 B1B1 B1 B1 E B1 D0 B2 B2 B2 B2 B2 B2 B2 B2 ES D1 L F L B1 B1FL B 1 B1 B1 B1 B1 B 1 B 1 E D 0 A F a N B 2B 2B 2B 2B1 B2 B2 B2 B2 E D1 M B1 B1 B1 B2 L L D1 B1 B1 B1 B1 B1 B1 B1 L D0 L B2 B2 B2 B2B1 B2 B2 B2 B2 L D1 LB2 L L D1 L FB 1 B1 B1 B1 B1 B1 B1 L D0 L Fa LB1 B2 B2 B2 B2 B2 B2 B2 FL 62.5 µs62.5 µs 62.5 µs62.5 µs B1 B1B1 NT to TE N T X T C T E R V M N T R V M T E X T C TE to NT F0b DSTi HALF Input NDA F0b DSTo HALF Input F0b DSTi HALF NDA F0b DSTo HALF Output Output Note: Shaded areas reveal data mapping

Fa-bit to be transmitted with the Q-bit. is even, the L-bit will be a space. section of the D-channel priority mechanism. multiframes must be performed externally. Table 1. Q-channel Allocation least significant bit first). port, will transmit the least significant bit first. sign bit as the least significant bit. particular channel of either serial port.

11 Q3 0

16 Q4 0

The C-channel bit mapping from the parallel port to the ST-BUS is organized such that the most significant bit is transmitted or received first. State Activation The state activation controller activates or deactivates the SNIC in response to line activity or external command. The controller is completely hardware driven and need not be initialized by the microprocessor. The state diagram for initialization is shown in Figure 7. The protocol used by the state activation controller is defined as follows: 1) In the deactivated state, neither the NT nor TE assert a signal on the line (Info0). 2) If the TE wants to initiate activation, it must begin transmitting a continuous signal consisting of a positive zero, a negative zero followed by six ones (Info1). 3) Once the NT has detected Info1, it begins to transmit Info2 which consists of an S-Bus frame Figure 7 - Link Activation Protocol, State Diagram Signals from NT to TE Signals from TE to NT Info0 Info2 Info4 No Signal Valid frame structure with all B, D, D-echo and A bits set to ‘0’ Valid frame with data in B, D, D-echo channels. Bit A is set to 1. Info1 Continuous Signal of +‘0’, -‘0’ and six ‘1’s (1) Info3 Valid frame with data in B & D Bits Where: BA (2) = Bus Activity DR = Deactivation Request AR = Activation Request Sync(2) = Frame Sync Signal A = Activation bit Time out = 32 ms Timer Signal Note 1: signal is not timebase locked to NT. Note 2: Sync/BA bit of the Status Register is configured as Sync bit when AR = 1 and DR = 0, or as BA bit when AR = 0 or DR = 1. A change in the state of the AR and/or DR bits will cause a change in the function of the Sync/BA bit in the following ST-BUS frame. TE State Activation Diagram NT State Activation Diagram DR = 1 AR = 1 Sync = 1 BA = 0 Sync = 1 DR = 1 DR = 1 BA = 0 A = 1 & Sync = 1 Sync = 0 A = 0 Activation Request send Info1 if BA = 0 send Info0 if BA = 1 Deactivated send Info0 Synchronized send Info3 if Sync = 1 send Info0 if Sync = 0 Activated send Info3 BA = 1 AR = 1 BA =0 Time out DR = 1 AR = 1 Sync = 1 Sync = 0 DR = 1 Deactivated send Info0 Pending Activation send Info2 Pending Deactivation Send Info0 Activated send Info4 Info0 No Signal

transmitted by the various TEs. synchronization state (IS0, IS1=1), in case of a TE. Motorola or Intel multiplexed bus signals and timing. Figures 24 & 25), then Intel bus timing is selected. port transparently to the user. 0 of the Master Control Register provides this option. Table 2. SNIC Address Map

00000 M a s t e r C o n t r o l R e g i s t e r v e r i f y

00110 H D L C A d d r e s s B y t e # 1 R e g i s t e r v e r i f y

00111 H D L C A d d r e s s B y t e # 2 R e g i s t e r v e r i f y

01000 C - c h a n n e l C o n t r o l R e g i s t e r

01001 C - c h a n n e l S t a t u s R e g i s t e r

10000 C o n t r o l R e g i s t e r 1 N o t A v a i l a b l e

10010 N o t A v a i l a b l e M a s t e r S t a t u s R e g i s t e r

01000 D S T i C - c h a n n e l

01001 D S T o C - c h a n n e l

01110 S - B u s T x B 2 - c h a n n e l D S T i B 2 - c h a n n e l

01111 D S T o B 2 - c h a n n e l S - B u s R x B 2 - c h a n n e l

The parallel port on the SNIC allows complete control of the HDLC transceiver and access to all data, control and status registers. Reading these registers allows the microprocessor to monitor incoming data on the S or ST-BUS without interrupting the normal data flow. Some registers are classified as asynchronous and others as synchronous. Synchronous registers are single-buffered and require synchronous access. Not all the synchronous registers have the same access times, but all can be accessed synchronously in the time during which the NDA signal is low (refer to Fig. 5). Therefore, it is recommended that the user make use of the NDA signal to access these registers. Since the synchronous registers use common circuitry, it is essential that the register be read before being written. This sequence is important as a write cycle will overwrite the last data received. These parallel accesses must be refreshed every frame. Asynchronous registers, on the other hand, can be accessed at any time. The data in TE or NT Mode Status Register, depending upon the mode selected, is always sent out on the C-channel of DSTo. However, in microprocessor control mode the user can overwrite this data by writing to the DSTo C-channel Register. This access can be done anytime outside the frame pulse interval of the ST-BUS frame. Data written in the current ST-BUS frame will only appear in the C- channel of the following frame. The least significant bit (B0) of the C-channel Register, selects between the control register or the diagnostic register. Setting the B0 of the C-channel Register to ’0’ allow access to the control register. Setting the LSB of the C-channel Register to ’1’ allow access to the diagnostic register. The interpretation of each register is defined in Tables 13 and 14 for NT mode or Tables 16 and 17 for the TE mode. It is important to note that in TE mode, the C-channel Diagnostic Register should be cleared while the device is not in the active state (IS0, IS1 ≠ 1,1). This is accomplished by setting the ClrDia bit of the C- channel Control Register to 1 until the device is activated. In serial control mode, the C-channel on the ST-BUS is loaded into the C-channel Control Register in every ST-BUS frame; the user should make sure that a 1 is written to the ClrDia bit in every frame. However, in parallel control mode the user needs to set the ClrDia bit only once to keep the Diagnostic Register cleared. Once full activation is achieved the Diagnostic Register can be written to in order to enable the various test functions. HDLC Transceiver The HDLC Transceiver handles the bit oriented protocol structure and formats the D-channel as per level 2 of the X.25 packet switching protocol defined by CCITT. It transmits and receives the packetized data (information or control) serially in a format shown in Figure 15, while providing data transparency by zero insertion and deletion. It generates and detects the flags, various link channel states and the abort sequence. Further, it provides a cyclic redundancy check on the data packets using the CCITT defined polynomial. In addition, it can recognize a single byte, dual byte or an all call address in the received frame. There is also a provision to disable the protocol functions and provide transparent access to either serial port through the microprocessor port. Other features provided by the HDLC include, independent port selection for transmit and received data (e.g. transmit on S-Bus and receive from ST-BUS), selectable 16 or 64 kbit/s D-channel as well as an HDLC loopback from the transmit to the receive port. These features are enabled through the HDLC control registers (see Tables 6 and 7). HDLC Frame Format All frames start with an opening flag and end with a closing flag as shown in Figure 15. Between these two flags, a frame contains the data and the frame check sequence (FCS). Figure 15 - Frame Format i) Flag The flag is a unique pattern of 8 bits (01111110) defining the frame boundary. The transmit section generates the flags and appends them automatically to the frame to be transmitted. The receive section searches the incoming packets for flags on a bit-by-bit basis and establishes frame synchronization. The flags are used only to identify and synchronize the received frame and are not transferred to the FIFO. FLAG DATA FIELD FCS FLAG One Byte n Bytes (n ≥ 2) Two Bytes One Byte

ii) Data The data field refers to the Address, Control and Information fields defined in the CCITT recommendations. A valid frame should have a data field of at least 16 bits. The first and second byte in the data field is the address of the frame. iii) Frame Check Sequence (FCS) The 16 bits following the data field are the frame check sequence bits. The generator polynomial is: G(x)=x 16+x12+x5+1 The transmitter calculates the FCS on all bits of the data field and transmits the complement of the FCS with most significant bit first. The receiver performs a similar computation on all bits of the received data but also includes the FCS field. The generating polynomial will assure that if the integrity of of the transmitted data was maintained, the remainder will have a consistent pattern and this can be used to identify, with high probability, any bit errors occurred during transmission. The error status of the received packet is indicated by B7 and B6 bits in the HDLC Status Register. iv) Zero Insertion and Deletion The transmitter, while sending either data from the FIFO or the 16 bits FCS, checks the transmission on a bit-by-bit basis and inserts a ZERO after every sequence of five contiguous ONEs (including the last five bits of FCS) to ensure that the flag sequence is not imitated. Similarly the receiver examines the incoming frame content and discards any ZERO directly following the five contiguous ONEs. v) Abort The transmitter aborts a frame by sending a zero followed by seven consecutive ONEs. The FA bit in the HDLC Control Register 2 along with a write to the HDLC Transmit FIFO enables the transmission of an abort sequence instead of the byte written to the register (to have a valid abort there must be at least two bytes in the packet). On the receive side, a frame abort is defined as seven or more contiguous ONEs occurring after the start flag and before the end flag of a packet. An interrupt can be generated on reception of the abort sequence using FA bit in the HDLC Interrupt Mask/Vector Registers (refer to Tables 9 and 10). Interframe Time Fill When the HDLC Tranceiver is not sending packets, the transmitter can be in one of two states mentioned below depending on the status of the IFTF bit in the HDLC Control Register 1. i) Idle State The Idle state is defined as 15 or more contiguous ONEs. When the HDLC Protocoller is observing this condition on the receiving channel, the Idle bit in the HDLC Status Register is set HIGH. On the transmit side, the Protocoller ends the transmission of all ones (idle state) when data is loaded into the transmit FIFO. CCITT I.430 Specification requires every TE that does not have layer 2 frames to transmit, to send binary ONEs on the D-channel. In this manner, other TEs on the line will have the opportunity to access the D-channel using the priority mechanism circuitry. ii) Flag Fill State The HDLC Protocoller transmits continuous flags (7E Hex) in Interframe Time Fill state and ends this state when data is loaded into the transmit FIFO. The reception of the interframe time fill will have the effect of setting the idle bit in the HDLC Status Register is set to ’0’. HDLC Transmitter On power up, the HDLC transmitter is disabled and in the idle state. The transmitter is enabled by setting the TxEN bit in the HDLC Control Register 1. To start a packet, the data is written into the 19 byte Transmit FIFO starting with the address field. All the data must be written to the FIFO in a bytewide manner. When the data is detected in the transmit FIFO, the HDLC protocoller will proceed in one of the following ways: 1) If the transmitter is in idle state, the present byte of ones is completely transmitted before sending the opening flag. The data in the transmit FIFO is then transmitted. A TE transmitting on the D-channel will use the contention circuitry described previously in D- channel Priority Mechanism to access this channel. 2) If the transmitter is in the flag fill state,

the flag presently being transmitted is used as the opening flag for the packet stored in the transmit FIFO. 3) If the HDLC transmitter is in transparent data mode, the protocol functions are disabled and the data in the transmit FIFO is transmitted without a framing structure. To indicate that the particular byte is the last byte of the packet, the EOP bit in the HDLC Control Register 2 must be set before the last byte is written into the transmit FIFO. The EOP bit is cleared automatically when the data byte is written to the FIFO. After the transmission of the last byte in the packet, the frame check sequence (16 bits) is sent followed by a closing flag. If there is any more data in the transmit FIFO, it is immediately sent after the closing flag. That is, the closing flag of a packet is also used as the opening flag the the next packet. However, CCITT I.430 and ANSI T1.605 Recommendations state that after the successful transmission of a packet, a TE must lower its priority level within the specified priority class. The user can meet this requirement by loading the Tx FIFO with no more than one packet and then waiting for the DCack bit to go to zero, or for an HDLC interrupt by the TEOP bit in the HDLC Interrupt Status Register, before attempting to load a new packet. If there is no more data to be transmitted, the transmitter assumes the selected link channel state. During the transmission of either the data or the frame check sequence, the Protocol Controller checks the transmitted information on a bit by bit basis to insert a ZERO after every sequence of five consecutive ONEs. This is required to eliminate the possibility of imitating the opening or closing flag, the idle code or an abort sequence. i) Transmit Underrun A transmit underrun occurs when the last byte loaded into the transmit FIFO was not ‘flagged’ with the ‘end of packet’ (EOP) bit and there are no more bytes in the FIFO. In such a situation, the Protocol Controller transmits the abort sequence (zero and seven ones) and moves to the selected link channel state. Conversely, in the event that the transmit FIFO is full, any further writes will overwrite the last byte in the Transmit FIFO. ii) Abort Transmission If it is desired to abort the packet currently being loaded into the transmit FIFO, the next byte written to the FIFO should be ‘flagged’ to cause this to happen. The FA bit of the HDLC Control Register 2 must be set HIGH, before writing the next byte into the FIFO. This bit is cleared automatically once the byte is written to the Transmit FIFO. When the ‘flagged’ byte reaches the bottom of the FIFO, a frame abort sequence is sent instead of the byte and the transmitter operation returns to normal. The frame abort sequence is ignored if the packet has less then two bytes. iii) Transparent Data Transfer The Trans bit (B4) in the HDLC Control Register 2 can be set to provide transparent data transfer by disabling the protocol functions. The transmitter no longer generates the Flag, Abort and Idle sequences nor does it insert the zeros and calculate the FCS. It should be noted that none of the protocol related status or interrupt bits are applicable in transparent data transfer state. However, the FIFO related status and interrupt bits are pertinent and carry the same meaning as they do while performing the protocol functions. HDLC Receiver After a reset on power up, the receive section is disabled. Address detection is also disabled when a reset occurs. If address detection is required, the Receiver Address Registers are loaded with the desired address and the ADRec bit in the HDLC Control Register 1 is set HIGH. The receive section can then be enabled by RxEN bit in this same Control Register 1. All HDLC interrupts are masked, thus the desired interrupt signal must be unmasked through the HDLC Interrupt Mask Register. All active interrupts are cleared by reading the HDLC Interrupt Status Register. i) Normal Packets After initialization as explained above, the serial data starts to be clocked in and the receiver checks for the idle channel and flags. If an idle channel is detected, the ‘Idle’ bit in the HDLC Status Register is set HIGH. Once a flag is detected, the receiver synchronizes itself in a bytewide manner to the incoming data stream. The receiver keeps resynchronizing to the flags until an incoming packet appears. The incoming packet is examined on a bit-by-bit basis, inserted zeros are deleted, the FCS is calculated and the data bytes are written into the

19 byte Receive FIFO. However, the FCS and other control characters, i.e., flag and abort , are never stored in the Receive FIFO. If the address detection is enabled, the address field following the flag is compared to the bytes in the Receive Address Registers. If one byte address recognition is enabled, the address field is one byte long and it is compared with the six most significant bits in address recognition register 1. If two byte address recognition is enabled, the address field is two bytes long and is compared with the address recognition registers 1 and 2. The address byte can also be recognized if it is an all call address (i.e., seven most significant bits are 1). If a match is not found, the entire packet is ignored, nothing is written to the Receive FIFO and the receiver waits for the next packet. If the active address byte is valid, the packet is received in normal fashion. All the bytes written to the receive FIFO are flagged with two status bits. The status bits are found in the HDLC status register and indicate whether the byte to be read from the FIFO is the first byte of the packet, the middle of the packet, the last byte of the packet with good FCS or the last byte of the packet with bad FCS. This status indication is valid for the byte which is to be read from the Receive FIFO. The incoming data is always written to the FIFO in a bytewide manner. However, in the event of data sent not being a multiple of eight bits, the software associated with the receiver should be able to pick the data bits from the LSB positions of the last byte in the received data written to the FIFO. The Protocoller does not provide any indication as to how many bits this might be. ii) Invalid Packets In TE mode, if there are less than 25 data bits between the opening and closing flags, the packet is considered invalid and the data never enters the receive FIFO (inserted zeros do not form part of the valid bit count). This is true even with data and the abort sequence, the total of which is less than 25 bits. The data packets that are at least 25 bits but less than 32 bits long are also invalid, but not ignored. They are clocked into the receive FIFO and tagged as having bad FCS. In NT mode, however, all the data packets that are less than 32 bits long are considered invalid. They are clocked into the receive FIFO with “Bad FCS” status. iii) Frame Abort When a frame abort is received, the EOPD and FA bits in the HDLC Interrupt Status Register are set. The last byte of the aborted packet is written to the FIFO with a status of “Packet Byte”. If there is more than one packet in the FIFO, the aborted packet is distinguished by the fact that it has no “Last Byte” status on any of its bytes. iv) Idle Channel While receiving the idle channel, the idle bit in the HDLC status register remains set. v) Transparent Data Transfer By setting the Trans bit in the HDLC Control Register 2 to select the transparent data transfer, the receive section will disable the protocol functions like Flag/ Abort/Idle detection, zero deletion, CRC calculation and address comparison. The received data is shifted in from the active port and written to receive FIFO in bytewide format. It should be noted that none of the protocol related status or interrupt bits are applicable in transparent data transfer state. However, the FIFO related status and interrupt bits are pertinent and carry the same meaning as they do while performing the protocol functions. vi) Receive Overflow Receive overflow occurs when the receive section attempts to load a byte to an already full receive FIFO. All attempts to write to the full FIFO will be ignored until the receive FIFO is read. When overflow occurs, the rest of the present packet is ignored as the receiver will be disabled until the reception of the next opening flag.

Table 3. Master Control Register (Read/Write Add. 00000 B) Note 1: These bits have no designated memory space and will read as the last values written to the microprocessor port. Note 2: The transmission of M=1 is used for a second level of multiframing. Table 4. Control Register 1 (Write Add. 10000 B) B7 NA A ‘1’ will allow access to Control Register 1 and Master Status Register. B6-B3 NA (1) Keep at ’0’ for normal operation. B2 IRQ /NDA The state of this pin will select the mode of the IRQ/NDA pin. A ’0’ will enable the IRQ pin for HDLC interrupts. (refer to functional timing). A ’1’ will disable this feature forcing the M and S bits to binary zero. Register is accessed through the microprocessor port. B7 NA Keep at ‘0’ for normal operation. B5-B0 NA Keep at ‘0’ for normal operation.

Table 5. ST-BUS Control Register (Read/Write Add. 00001 B) Note 3: All ST-BUS channels are enabled in controllerless mode. Table 6. HDLC Control Register 1 (Read/Write Add. 00010 B) Note 1: The HDLC receiver must be enabled as well as the designated channel. B7 CH3i (3) If ’1’, then the ST-BUS channel 3 input port is enabled (B2-channel). If ’0’, then the channel is disabled, and will read FFH. B6 CH2i (3) If ’1’, then the ST-BUS channel 2 input port is enabled (B1-channel). If ’0’, then the channel is disabled, and will read FFH. B5 CH1i (3) If ’1’, then the ST-BUS channel 1 input port is enabled (C-channel). If ’0’, then the channel is disabled, and will read 00H. B4 CH0i (3) If ’1’, then the ST-BUS channel 0 input port is enabled (D-channel). If ’0’, then the channel is disabled, and will read FFH. B3 CH3o (3) If ’1’, then the ST-BUS channel 3 output port is enabled (B2-channel). If ’0’, then the channel is disabled and it will be placed in High impedance. B2 CH2o (3) If ’1’, then the ST-BUS channel 2 output port is enabled (B1-channel). If ’0’, then the channel is disabled and it will be placed in High impedance. B1 CH1o (3) If ’1’, then the ST-BUS channel 1 output port is enabled (C-channel). B0 CH0o (3) If ’1’, then the ST-BUS channel 0 output port is enabled (D-channel). If ’0’, then the channel is disabled and it will be placed in High impedance. B7 TxEn A ’1’ enables the HDLC transmitter for the selected D-channel (i.e., ST-BUS or S-Bus). A ’0’ disables the HDLC transmitter (i.e., an all 1s signal will be sent). B6 RxEn A ’1’ enables the HDLC receiver for the selected D-channel (i.e., ST-BUS or S-Bus). A ’0’ disables the HDLC receiver (i.e., an all 1s signal will be received). Registers or if the address byte is the All-Call address (all 1s). B4 TxPrtSel This bit selects the port of the HDLC transmitted D-channel. A’1’ selects the S-Bus port. A ’0’ selects the ST-BUS port. B3 RxPrtSel This bit selects the port of the HDLC received D-channel. A ’1’ selects the S-Bus port. A ’0’ selects the ST-BUS port. B2 IFTF This bit selects the Inter Frame Time Fill. A ’1’ selects continuous flags. A ’0’ selects an all 1’s idle state. B1 NA Keep at ’0’ for normal operation. the packet to be transmitted to the S-Bus. A ’0’ disables the loopback.

Table 7. HDLC Control Register 2 (Write Add. 00011 B) Figure 8. HDLC Status Register (Read Add. 00011 B) B7-B5 NA Keep at ’0’ for normal operation. by the port selection bits in the HDLC Control Register 1. be transmitted once it reaches the bottom of the FIFO. sequence to be transmitted once it reaches the bottom of the FIFO. B1 Idle If ’1’, an idle channel state has been detected. B0 Int If ’1’ an unmasked asynchronous interrupt has been detected.

Table 9. HDLC Interrupt Mask Register (Write Add. 00100 B) Table 10. HDLC Interrupt Status Register (Read Add. 00100 B) Note 1: All interrupts will be reset after a read to the HDLC Interrupt Status Register. B7 EnDcoll A ’1’ will enable the D-channel collision interrupt. A ’0’ will disable it. This bit is available only in TE mode. B6 EnEOPD A ’1’ will enable the received End of Packet interrupt. B5 EnTEOP A ’1’ will enable the transmit End of Packet interrupt. B4 EnFA A ’1’ will enable the Frame Abort interrupt. B3 EnTxFL A ’1’ will enable the Transmit FIFO Low interrupt. B2 EnTxFun A ’1’ will enable the Transmit FIFO Underrun interrupt. B1 EnRxFF A ’1’ will enable the Receive FIFO Full interrupt. B0 EnRxFov A ’1’ will enable the Receive FIFO Overflow interrupt. HDLC transmitter is enabled. It always reads ’0’ in NT mode. in the form of a flag, an abort sequence or as an invalid packet. the Tx FIFO, and the internal priority level is reduced from high to low. significance only when the Tx FIFO is being depleted and not when it is getting loaded. B2 TxFun (1) A ’1’ indicates that the Tx FIFO is empty without being given the ’end of packet’ indication. The HDLC will transmit an abort sequence after encountering an underrun condition. B0 RxFov (1) A ’1’ indicates that the Rx FIFO has overflown (i.e., an attempt to write to a full Rx FIFO). The HDLC will always disable the receiver once the receive overflow has been detected. The receiver will be re-enabled upon detection of the next flag.

Table 11. HDLC Address Recognition Register 1 (Read/Write Add. 00110 B) Table 12. HDLC Address Recognition Register 2 (Read/Write Add. 00111 B) Table 13. NT Mode C-channel Control Register (2) (Write Add. 01000 B and B0 = 0) Note 1: Allow one ST-BUS frame to input the C-channel and one ST-BUS frame to establish the connection. more than once per frame, otherwise, the last access will override previous ones. B7-B2 R1A7-R1A2 A six bit mask used to interrogate the first byte of the received address (where B7 is MSB). B1 NA Not applicable to address recognition. B0 A1En If ’0’, the first byte of the address field will not be used during address recognition. address byte will be compared with the first six bits of this register. B0 A2En If ’0’, the second byte of the address field will not be used during address recognition. address byte will be compared with the first seven bits of this register. B7 AR Setting this bit will initiate the activation of the S-Bus. If ’0’, the device will remain in the present state. B6 DR Setting this bit will initiate the deactivation of the S-Bus. If ’0’, the device will remain in the present state. This bit has priority over AR. compensation for line length). S-Bus. The operation of this signal is similar to that of the HALF pin. register. A ’0’ give access to the control register.

Table 14. NT Mode C-channel Diagnostic Register (Write Add. 01000 B and B0 = 1) Table 15. NT Mode Status Register (2) (Read Add. 01001 B) consecutive ones are received. been detected without error. B4 FLv If ’1’, the frame sync sequence will violate the bipolar violation encoding rule. If ’0’, the framing pattern resumes normal operation, i.e., Framing bit is a bipolar violation. B3 Idle Setting this bit to ’1’ will force an all 1s signal to be transmitted on the line. B2 Echo Setting this bit to ’1’ will force all D-echo bits (E) to zero. terminal equipment end of the line while receiving its clocks from an external source. register. A ’0’ gives access to the control register. identifies the reception of INFO frames (INFO1 or INFO3). B6-B5 IS0-IS1 Binary encoded state sequence. position during multiframing). This bit will always read ‘1’ if multiframing is not used.

Table 16. TE Mode C-channel Control Register (2) (Write Add. 01000 B and B0 = 0) Note 1: Allow one ST-BUS frame to input the C-channel and one ST-BUS frame to establish the connection. more than once per frame, otherwise, the last access will override previous ones. Table 17. TE Mode Diagnostic Register (Write Add. 01000 B and B0 = 1) B7 AR Setting this bit will initiate the activation of the S-Bus. If ’0’, the device will remain in the present state. B6 DR Setting this bit will initiate the deactivation of the S-Bus. If ’0’, the device will remain in the present state. This bit has priority over AR. high priority and a ’0’ selects the low priority. source is the ST-BUS. A ’1’ will request the D-channel, a ’0’ will relinquish it. Keep at ’0’ when the D-channel source is the HDLC transmitter. B2 TxMCH The state of this bit will be transmitted in the maintenance channel (Q-channel). B1 ClrDia A ’1’ will clear the contents of the Diagnostics Register. A ’0’ will enable the maintenance functions found in the Diagnostic Register. This bit should be set to 1 as long as the device is not fully active (IS0, IS1 ≠ 1,1). Register. A ’0’ gives access to the Control Register. transmitted even if the frame sync sequence in the received signal is lost). B4 FLv If ’1’, the frame sync sequence will violate the normal bipolar encoding rule. B3 Idle If ’1’, an all 1s signal is transmitted on the line. If ’0’, the transmitter will resume normal operation. register. A ’0’ gives access to the control register.

Table 18. TE Mode Status Register (2) (Read Add. 01001 B) consecutive ones are received. Table 19. Master Status Register (Read Add. 10010 B) TE mode. Please refer to “State Machine” section of Application Note MSAN-141 for further details. identifies the reception of INFO frames (INFO2 or INFO4). B6-B5 IS0-IS1 Binary encoded state sequence. B2 RxMFR A ’1’ when HALF=0 indicates that the multiframe pattern on Fa and N has been detected. B1* INFO1 In TE mode, this bit is set to ‘1’ only when the device is transmitting INFO1. B0* INFO0 In NT or TE mode, this bit is set to ‘1’ only when the device is transmitting INFO0.

The MT8931C is useful in a wide variety of ISDN applications. Being used at both the Network Termination (NT) and Terminal Equipment (TE) ends of the line, the SNIC finds application on digital subscriber line cards and in full featured digital telephone sets. The SNIC can be combined with the MT8971B/72B to implement an NT1 function(with biphase line code on the U interface) as shown in Figure 16. It can also be combined with the MT8910 to implement an ISDN NT1 function (with 2B1Q line code on the U interface) as shown in Figure 17. The MT8931C is configured in NT mode, acting as a master to the S- interface line, while the MT8971B/72B or the MT8910 operates in slave mode and derives its timing from the U-interface line originating from the central office. Figure 18 illustrates the use of the SNIC in conjunction with the MT9094 to implement a 2B+ D, ISDN telephone set. The MT9094 provides such features as A/D and D/A conversion, handset interface, handsfree operation and tone ringer. PCM encoded voice is passed from the MT9094 to the SNIC via the ST-BUS port for transmission on one of the B-channels. The second B-channel is available for transmission of data. These two devices have been designed to connect together with virtually no interconnection components. Both the MT8931C and MT9094 are controlled and monitored by a microprocessor to implement various features and control functions. Signalling may be performed by scanning the keypad and generating appropriate messages to be packetized by the HDLC section of the SNIC and transmitted via the D- channel. A twelve segment, non-multiplexed LCD display can be connected directly to the S12-S1 outputs to provide various status and call progress indicators. It must be noted, that the pseudo-ternary line code will tolerate line reversals within the LRx and LTx pair between the NT and TE. However, reversal of the TE transmit pair between two or more TEs will make the S-interface inoperable. In multidrop applications, a powered-off TE must not load the line and prevent communications between the NT and other TEs. To avoid such a situation, one mechanical relay should be used to disconnect the LTx pin and the LRx pin from the line transformers. Interfacing to Non-Multiplexed Busses The microprocessor interface for the SNIC was designed around a multiplexed bus architecture which may be found with most Intel processors/ controllers or a few Motorola processors. In the event that your choice of processors is restricted, a simple application circuit can convert the non- multiplexed bussing to that of a multiplexed architecture. Figure 19 provides an to interface the MC6802 or the MC6809 microprocessors. Figure 16 - NT1 Function DSTi DSTo F0b C4b MS0 MS1 MS2 VREF VBias LOUT LIN OSC1 OSC2 DSTo DSTi F0b C4b NT Rsti Star LTx LRx VBias MT8931C MT8971B/72B DC to DC Converter +5V 2:1 +5V +5V +5V RTx 1:2* 1:2* 10µF 10kΩ 0.33µF 0.33µF 1.5 nF 22 nF390 Ω 47 Ω

10.24 MHz XTAL

0.33 µF 1.0 µF ‡100Ω terminating resistor Microprocessor

TS 300-012 NT&TE Line Interface Figures 20, 21 and 22 show the recommended line interface circuits for meeting the ETS 300-012 requirements. These circuits assume that test measurements are made using the "standard reference cord" which has the following specifications: C = 315pF to 350pF R = 2.7 Ω to 3.0 Ω Z > 75 Ω Length < 10m Several types of transformers can be used:

Filtran TPW-3852-4 (Figure 20)
VAC T60403-L4096-X028 (Breakdown Voltage 4KV) (Figure 21)
VAC T60403-L4096-X027 Breakdown Voltage 2KV) (Figure 21)
VAC T60403-L4096-X029 (Breakdown Voltage 4KV) (Figure 22)
VAC T60403-L4096-X030 (Breakdown Voltage 2KV) (Figure 22) L4096-X029 and L4096-X030 are equivalent to L4096-X028 and L4096-X027 with the exceptions of pin out; L4096-X029 and L4096-X030 are pin compatible with L4096-X028-80. In Figure 20, T1, 2 (Filtran TPW-3852-4) provides isolation, longitudinal balance, impedance matching and voltage level conversion. D5 and 6 (germanium) ensure that the pulse shape lies within the center of the various pulse templates. D1-4 protect the MT8931C from line transients. C2, 3 decouple the VBias voltage and optimize the receiver sensitivity. R1 and C4 make up a low-pass filter recommended for delaying the signal in TE applications, this filter can also be used for NT applications allowing common hardware for TE and NT applications. K1 isolates the MT8931C from the line for multidrop applications in cases where the device is powered down. L1 is 4-winding 5mH common mode choke to suppress EMI on the 4-wire line. The TPW-3852-4 is available from: Filtran Ltd.

229 Colonnade Road

Nepean, Ontario Canada Telephone: (613) 226-1626 Figure 19 - Interfacing to the MC6802 Microprocessor MT8931C AD0-AD7 CS DS R/W AS DIR B A G A B DIR G QD Address Decoder VDD 74HCT245 VDD 74HCT245 MC6802 (MC6809) A0 - A7 VMA D0 - D7 R/W E EXTAL (Q) Connections to interface to MC6809

In Figure 21, two types of diodes (germanium 1N270 or schottky MBD301) can be used for D5,6. 1N270 will leave more margin for pulse template and longitudinal conversion loss. However, MBD301 will leave more margin for impedance template. All other components are as described previously for Figure 20. The VAC Transformers are available from: Germany Vacuumschmelze GMBH Postfach 22 53 D-63412 Hanau Telephone: (49) 6181 380 Canada Votron Electronic Ltd.

250 Rayette Road

Concord, Ontario L4K 2G6 Telephone: (905) 669-9870 USA Vacuumschmelze Corporation

4027 Will Rogers Parkway

Oklahoma City, OK 73108 Telephone: (405) 943-9651 Proprietary NT&TE Line Interface For proprietary applications, where stringent requirements such as ETS 300-012 do not have to be met, the line interface circuit may be simpler and consequently less expensive. Figure 23 shows such a line interface circuit. R1 should be chosen according to the transformer selected and the desired output signal level, typical values of R1 may vary from 30 Ω to 75 Ω. Numerous types of transformers may be used, including the following: APC 8016D (dual with common mode choke) Filtran TEW-5660 (surface mount) Filtran TPW-3852-4 (single) Pulse PE-65495 (dual) VAC L4097-X028-80 (single) In Figure 22, everything is the same as in Figure 21, except transformer pin out. Figure 20 - ETS 300-012 NT & TE Line Interface for Filtran TPW-3852-4 VDD VDD LTx VDD VBias VDD VDD LRx VSS MT8931C Tx+ Tx- Rx- Rx+ K1 VDD Parts List: C1, 3 = 0.1 µF Ceramic C2 = 10µF Tantalum C4 = 22pF D1-4 = IN914 D5, 6 = IN270 Germanium D7 = IN4003 K1 = 2 Form A or C Relay (eg., Aromat TQ2E-5V) L1 = VAC N4025-X034 R1 = 3k01 1% R2, 3 = 100 Ω 1% T1, 2 = Filtran TPW-3852-4

Figure 23 - Proprietary NT & TE Line Interface VDD VDD LTx VDD VBias VDD VDD LRx VSS MT8931C Tx+ Tx- Rx- Rx+ Parts List: C1, 3 = 0.1 µF Ceramic C2 = 10µF Tantalum D1-4 = IN914 R1 = see circuit description R2 = 2k to 4k R3, 4 = 100 Ω T1, 2 = see circuit description

Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. * Except for XTAL1/NT pin. See below. ** Including the transformer DC resistance. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. Absolute Maximum Ratings* Parameters Symbol Min Max Units 1 Supply Voltage V DD -0.3 7.0 V 2 Voltage on any I/O pin V I/O -0.3 V DD + 0.3 V

3 Current on any I/O pin I I/O 20 mA

4 Storage Temperature T ST -65 150 °C

5 Package Power Dissipation P D 1000 mW

Recommended Operating Conditions - Voltages are with respect to ground (V SS) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions 1 Supply Voltage V DD 4.75 5.0 5.25 V 2 Input High Voltage* V IH 2.4 V DD V For 400mV noise margin 3 Input Low Voltage* V IL 0 0.4 V For 400mV noise margin

4 Load Resistance (LTx) R L 250** Ω With reference to VBias

5 Load Capacitance (LTx) C L 32 pF With reference to V Bias

6 Operating Temperature T OP -40 85 °C

Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Supply Current

I DDNA IDDND IDDTA IDDTD mA mA mA mA Outputs loaded Outputs unloaded Outputs loaded Outputs unloaded

2 Input High Voltage except for pin

V IH 2.0 V Digital inputs

3 Input High Voltage for pin

4 Input Low Voltage except for pin

VIL 0.8 V Digital inputs

5 Input Low Voltage for pin

6 Output High Current I OH 10 15 mA V OH=2.4V digital outputs 7 Output Low Current I OL 57 . 5 m A V OL=0.4V digital outputs

8 Input Leakage (except pin 8) I iI 10 µAV IN = VSS to VDD

9 Input Current for pin 8 25 µAV IN = VSS to VDD

10 Output Leakage High Imped. I OZ 10 µAV OUT = VSS to VDD Characteristics Sym Min Typ ‡ Max Units Test Conditions 1 Input Voltage (LRx) V IN 1.5 V Peak with Ref. to V Bias 2 Input Current (LRx) I IN 70 µAV I=1.5Vp Ref. VBias @ f=0 - 100 kHz 3 Output Voltage (LTx) V O 1.5 V Ref. V Bias, RL=250Ω 4 Output Current (LTx) I O 7.5 mA V O=1.5Vp Ref. VBias, RL=250Ω

5 Input Impedance (LRx) Z IN 20 k Ω f = 100 kHz

2 Frame pulse (F0b ) set-up time t FPS 35 ns

3 Frame pulse (F0b ) hold time t FPH 50 ns

4C 4 b input clock period t P4o 244 ns 5C 4 b pulse width High or Low t C4W 122 ns 6C 4 b transition time t C4T 20 ns 7F 0 o d delay t DFD 20 87 ns 40 pF Load 8F 0 o d pulse width t DFW 244 ns

9 Serial input set-up time t SIS 70 ns

10 Serial input hold time t SIH 0n s

11 Serial output delay t SOD 160

50 pF load (HDLC connected to ST-BUS)

12 HALF input setup time t

13 HALF input hold time t HAH 200 ns

† Timing is over recommended temperature & power supply voltages ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. Figure 23 - ST-BUS Timing TE Mode Characteristics Sym Min Typ ‡ Max Units Test Conditions 1F 0 b output pulse width t FPW 244 ns 50 pF load 2C 4 b to (F0b) delay t CFD 10 50 ns 50 pF load 3C 4 b to (F0b) hold time t CFH 10 50 ns 50 pF load 4C 4 b output clock period t P4o 244 ns 50 pF load 5C 4 b pulse width High or Low t C4W 110 122 ns 50 pF load (activated state) 6C 4 b transition time t C4T 20 ns 50 pF load 7F 0 o d delay t DFD 10 50 ns 8F 0 o d pulse width t DFW 220 244 ns

9 Serial input setup time t SIS 150 ns

11 Serial output delay t SOD 125 ns 50 pF load

12 HALF output Delay t HAD 150 ns 50 pF load

† Timing is over recommended temperature & power supply voltages ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. Figure 24 - Intel Bus Interface Timing (Write Cycle) Figure 25 - Intel Bus Interface Timing (Read Cycle) Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Chip select setup time t CSS 10 ns

2 Chip select hold time t CSH 25 ns

3 Address Latch pulse width t ALW 50 ns

4 Address setup time t ADS 20 ns

5 Address hold time t ADH 20 ns

6 Data setup time - Write t DWS 35 ns

7 Data hold time - Write t DHW 20 ns

8 Data output delay - Read t DOD 240 ns 50 pF load

9 Data hold time - Read t DHR 25 90 ns 50 pF load

10 Write pulse width t WPW 60 ns

11 RD , WR delay t RWD 60 ns

12 Read pulse width t RPW 240 ns

13 Read setup time t RDS 20 ns

† Characteristics are for clocked operation over the ranges of recommended operating temperature and supply voltage. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. Figure 26 - Motorola Bus Interface Timing Characteristics Sym Min Typ ‡ Max Units Test Conditions

2 Chip select hold time t CSH 10 ns

3 Address strobe pulse width t ASW 50 ns

4 Data strobe setup time t DSS 20 ns

5 Data strobe hold t DSH 20 ns

6 Data strobe pulse width - Write

Read tDSW 100 240 ns ns

7 Read/Write setup time t RWS 40 ns

8 Read/Write hold time t RWH 10 ns

9 Address setup time t ADS 20 ns

10 Address hold time t ADH 20 ns

11 Data setup time - Write t DWS 35 ns

12 Data hold time - Write t DHW 30 ns

13 Data output delay t DOD 240 ns 50 pF load

14 Data hold time - Read t DHR 25 90 ns 50 pF load

-AD7 (Write) AD0 -AD7 (Read) VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VI/OH VI/OL tCSS tCSH tASW tDSS tDSH tDSW tRWS tRWH tADS tADH tDWS tDHW tADS tADH tDOD tDHR Address Data Output Address Data Input

† Characteristics are for clocked operation over the ranges of recommended operating temperature and supply voltage. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. Figure 27 - INT & Rsti Timing Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Interrupt release delay t IRD 100 ns

2 Reset pulse width t RSW 1 µs

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Summary

Subscriber Network Interface Circuit

Description

Source title MT8931CE Datasheet(PDF) - Zarlink Semiconductor Inc

Read MT8931CE online.

MT8931C ZARLINK | Alldatasheet

Document overview

Technical content

Features

Applications

Description

Ordering Information

12 H A L F HALF Input/Output: this is an input in NT mode and an output in TE mode identifying

34 F 0 b Frame Pulse: an active low frame pulse input indicating the beginning of active ST-

47 F 0 o d Delayed Frame Pulse Output: an active low delayed frame pulse output indicating

58 D S T i Data ST-BUS Input: a 2048 kbit/s serial PCM/data ST-BUS input with D, C, B1, and B2

69 D S T o Data ST-BUS Output: a 2048 kbit/s serial PCM/data ST-BUS output with D, C, B1 and

28 PIN PDIP

44 PIN PLCC

11 Q3 0

16 Q4 0

00000 M a s t e r C o n t r o l R e g i s t e r v e r i f y

00110 H D L C A d d r e s s B y t e # 1 R e g i s t e r v e r i f y

00111 H D L C A d d r e s s B y t e # 2 R e g i s t e r v e r i f y

01000 C - c h a n n e l C o n t r o l R e g i s t e r

01001 C - c h a n n e l S t a t u s R e g i s t e r

10000 C o n t r o l R e g i s t e r 1 N o t A v a i l a b l e

10010 N o t A v a i l a b l e M a s t e r S t a t u s R e g i s t e r

01000 D S T i C - c h a n n e l

01001 D S T o C - c h a n n e l

01110 S - B u s T x B 2 - c h a n n e l D S T i B 2 - c h a n n e l

01111 D S T o B 2 - c h a n n e l S - B u s R x B 2 - c h a n n e l

10.24 MHz XTAL

229 Colonnade Road

250 Rayette Road

4027 Will Rogers Parkway

3 Current on any I/O pin I I/O 20 mA

4 Storage Temperature T ST -65 150 °C

5 Package Power Dissipation P D 1000 mW

4 Load Resistance (LTx) R L 250** Ω With reference to VBias

5 Load Capacitance (LTx) C L 32 pF With reference to V Bias

6 Operating Temperature T OP -40 85 °C

1 Supply Current

2 Input High Voltage except for pin

3 Input High Voltage for pin

4 Input Low Voltage except for pin

5 Input Low Voltage for pin

8 Input Leakage (except pin 8) I iI 10 µAV IN = VSS to VDD

9 Input Current for pin 8 25 µAV IN = VSS to VDD

5 Input Impedance (LRx) Z IN 20 k Ω f = 100 kHz

2 Frame pulse (F0b ) set-up time t FPS 35 ns

3 Frame pulse (F0b ) hold time t FPH 50 ns

9 Serial input set-up time t SIS 70 ns

10 Serial input hold time t SIH 0n s

11 Serial output delay t SOD 160

12 HALF input setup time t

13 HALF input hold time t HAH 200 ns

9 Serial input setup time t SIS 150 ns

11 Serial output delay t SOD 125 ns 50 pF load

12 HALF output Delay t HAD 150 ns 50 pF load

1 Chip select setup time t CSS 10 ns

2 Chip select hold time t CSH 25 ns

3 Address Latch pulse width t ALW 50 ns

4 Address setup time t ADS 20 ns

5 Address hold time t ADH 20 ns

6 Data setup time - Write t DWS 35 ns

7 Data hold time - Write t DHW 20 ns

8 Data output delay - Read t DOD 240 ns 50 pF load

9 Data hold time - Read t DHR 25 90 ns 50 pF load

10 Write pulse width t WPW 60 ns

11 RD , WR delay t RWD 60 ns

12 Read pulse width t RPW 240 ns

13 Read setup time t RDS 20 ns

2 Chip select hold time t CSH 10 ns

3 Address strobe pulse width t ASW 50 ns

4 Data strobe setup time t DSS 20 ns

5 Data strobe hold t DSH 20 ns

6 Data strobe pulse width - Write

7 Read/Write setup time t RWS 40 ns

8 Read/Write hold time t RWH 10 ns

9 Address setup time t ADS 20 ns

10 Address hold time t ADH 20 ns

11 Data setup time - Write t DWS 35 ns