MT8926 MITEL | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 26
Technical content
Features
- ANSI T1.403 and T1.408 Performance Monitoring and Maintenance Functions
- Operates in conjunction with Mitel's T1/ESF framer circuits (MT8976/77 and MH89760B)
- D3/D4 (SF), and ESF modes of operation
- One and two second timers
- Supports bit-oriented and message-oriented data transfer over the Facility Data Link (FDL)
- ESF and D3/D4 Yellow Alarms, Alarm Indication Signal and Loss of Signal Indication
- Framing Error, CRC Error and Bipolar Violation Error counters
- Alarm interrupts and counter overflow interrupts
Applications
- T1 line performance data collection
- CSU performance monitoring
- ISDN Primary Rate maintenance controller
Description
The MT8926 Performance Monitoring Adjunct Circuit (PMAC) interworks with Mitel's MT8976/77 and MH89760B to provide performance monitoring data, alarms and T1 maintenance features. It meets the performance monitoring and maintenance requirements of ANSI T1.403 and T1.408, and also supports Channel Service Unit (CSU) requirements. Figure 1 - Functional Block Diagram FDLi E8Ki IRQ C2i CSTi0 CSTi1 CSTo RESET DSTi0 DSTi1 DSTo F0i Transmit BOM Register Receive BOM Register & RAI Debounce ST-BUS Interface Payload & Line Loopback Control Snap- Shot Registers
8 Bit CRC
4 Bit SE
4 Bit FE
8 Bit BPV
Framer, SE/FE Detector Line Loopback Integrator B8ZS Recovery, BPV Detector AIS/LOS Detector 1SEC ECLK RxB RxA VSS VDD FDLo E8Ko
Ordering Information
MT8926AE 28 Pin Plastic DIP MT8926AP 28 Pin PLCC -40°C to 85°C ISSUE 3 July 1993 MT8926 T1 Performance Monitoring Adjunct Circuit (PMAC) ISO-CMOS ST-BUS FAMILY
Figure 2 - Pin Connections Pin Description Pin # Name Description 1V SS System Ground. 2E C L K Extracted Clock Input. A 1.544 MHz clock derived from the received data. This signal is used to clock in the data on pins RxA and RxB. See Figure 11 for timing information. 3R x A Receive A Input. A unipolar active low signal decoded from the received T1 signal. See Figure 11 for timing information. 4R x B Receive B Input. A unipolar active low signal decoded from the received T1 signal. See Figure 11 for timing information. 5I C Internal Connection. Must be tied to VSS for normal operation. 6E 8 K i Extracted 8 kHz Input. A low going pulse on this input is used by the PMAC to locate the framing bit in the received signal. The device uses this information to detect errors in the received framing bits. Connect to E8Ko of the MT8976/77. See Figure 12 for timing information. 7E 8 K o 8 kHz clock output. The 8 kHz signal input at E8Ki is output on this pin when bit 2 (8KEn) of the PMAC Control Word is set. The output is pulled high when 8KEn is reset. See Figure 12 for timing information. SS System Ground. 9 CSTo Control ST-BUS Output. The data that enters the PMAC on CSTi0 will exit the device on this pin. Data derived by the PMAC will be inserted into specific channels of this output stream. See Figures 13 and 14 for timing information and Figure 5 for channel allocation. 10 CSTi0 Control ST-BUS Input 0. Accepts the serial ST-BUS stream output on CSTo of the MT8976/77. The data that enters the PMAC on this pin exits the device on CSTo. The contents of specific CSTi0 channels is replaced by data derived by the PMAC. See Figures 13 and 14 for timing information and Figure 4 for channel allocation. 11 CSTi1 Control ST-BUS Input 1. Channel 11 of this ST-BUS input stream is used to control specific features in the device (Table 14). Channel 7 is used for the transmit bit-oriented message (Table 13), and channel 15 is used to control loopback functions (Table 4). See Figure 13 for timing information and Figure 3 for channel allocation.
12 F0i
Frame Pulse Input. This input accepts an 8 kHz signal, which is used to delineate the ST- BUS frame boundary. See Figure 15 for timing information. 14 15
28 PIN PLASTIC DIP
262728 VSS
28 PIN PLASTIC J-LEAD
13 C2i 2.048 MHz Clock Input. This input accepts a 2.048 MHz clock signal, which is used to clock ST-BUS control and data streams into and out of the PMAC. See Figures 13 and 14 for timing information. 14 V SS System Ground. 15 V DD Supply Voltage Input (+5 V). 16 RESET RESET Input. Must be high for normal operation. When low, the functions of the MT8926 will be suspended. 17 FDLi Facility Data Link Input. This input accepts a 4 kbit/sec. facility data link transmit signal, which is routed back out transparently on FDLo if message-oriented signal transmission is enabled (i.e., PMAC Control Word bit 0, FDLEn, is low). This signal is not clocked into the PMAC. If bit-oriented messaging is enabled (FDLEn high), data on this input will not be routed to FDLo (see pin 18, FDLo, below). 18 FDLo Facility Data Link Output. When bit-oriented messaging is enabled (i.e., PMAC Control Word bit 0, FDLEn, is high), data in the Transmit BOM register will be appended to a 1111 1111 (FF) flag and clocked out of the device at this output. The output timing for this signal is shown in Figure 18. When bit-oriented messaging is disabled (FDLEn low), data received at the FDLi pin is routed back out transparently on this pin (it is not re-timed). See Figure 19 for timing information. 19 1SEC 1 Second Output. A one second timing signal derived from the ST-BUS F0i signal is output on this pin. The output is low for 0.5 seconds and high for 0.5 seconds. It can be used as an interrupt source to generate T1.403 message-oriented performance reports. See Figure 16 for timing information.
20 IRQ
Interrupt Request Output. An open drain output that is to be externally connected to VDD through a pull-up resistor. The PMAC will pull this pin low to assert an interrupt request. Interrupting events and their groupings are described in Tables 16 and 17. IRQ is released by making bit 1 (Interrupt Acknowledge - INTA) of the PMAC Control Word low. Once INTA is set, all interrupting signals of a particular group must be inactive before the next interrupt of that group can assert IRQ . See Figure 17 for functional timing information. 21 IC Internal Connection. Must be left open for normal operation. 22 V SS System Ground. 23 IC Internal Connection. Must be left open for normal operation. 24 DSTo Data ST-BUS Output. A 2.048 MBit/sec. serial output stream, which contains the 24 PCM or data channels to be transmitted on the T1 trunk. This data stream is multiplexed from either input DSTi0 (Normal Mode) or input DSTi1 (Payload Loopback Mode). The selection of either the Normal or Payload Loopback mode is made through the Loopback Control Word. This output should be connected to DSTi of the MT8976/ 77. When the loopback control word is set for line loopback code generation, the 24 PCM channels will contain the line loopback activate or deactivate code stream. See Figure 14 for timing information. 25 DSTi0 Data ST-BUS Input 0. A 2.048 MBit/sec. serial input stream, which contains the 24 PCM or data channels to be transmitted on the T1 trunk in Normal Mode. This input should be connected to the system side output stream. 26 DSTi1 Data ST-BUS Input 1. A 2.048 MBit/sec. serial input stream, which contains the 24 PCM or data channels to be transmitted on the T1 trunk in Payload Loopback Mode. This input should be connected to DST o of the MT8976/77. 27 IC Internal Connection. Must be tied to V SS for normal operation. 28 V DD Supply Voltage Input (+5 V). Pin Description (Continued) Pin # Name Description
The MT8926 Performance Monitoring Adjunct Circuit (PMAC) is designed to enable a MT8976/77 based T1 interface to gather performance data and perform maintenance functions as per ANSI T1.403 and T1.408. Performance data collection includes CRC errors, severely errored framing events, frame synchronization-bit errors, line code violations, and controlled slips. Maintenance functions include the detection of alarms, SF line loopback code generation and detection, ESF payload loopback, as well as the transport of bit-oriented and message- oriented signals over the Facility Data Link (FDL). The control and status data of the MT8926 is transported over spare channels of the existing MT8976/77 ST-BUS streams. Therefore, no new ST- BUS streams are required to upgrade with the PMAC. The PMAC has an on-board framer that uses the received signal and extracted 8 kHz clock to achieve synchronization. The result of this frame alignment is logically ANDed with the SYN bit of the MT8976/77 CST o stream to give FECV (see T able 5). This will ensure that the PMAC can only declare synchronization after the framer is synchronized. The MT8926 will align to SF or ESF framing without user selection. An interrupt (IRQ output) system is also provided to reduce the requirement to monitor ST-BUS channels continuously for exception conditions. Interrupt sources are divided into group one (G1) for service affecting events and group two (G2) for counter overflows. A timer has been included to allow scheduling of T1.403/408 message-oriented performance reports for transmission over the facility data link. This timer provides a two second output (register accessed) and a one second output pin. Two eight bit counters with overflow bits and resets (resets counter and overflow bit) are provided to record line code violations (BPV) and CRC errors. The BPV counter will not count B8ZS encoding violations. When either overflow bit goes high it will generate a group two (G2) interrupt. Two four bit counters are used to record framing error events (FE) and severely errored framing events (SE). The FE counter has an overflow indication bit and can be cleared (resets counter and overflow bit) by the user. Its overflow bit will generate a group two (G2) interrupt when it goes high. A G2 interrupt will also be issued whenever the SE counter is incremented. The alarms that the PMAC monitors are alternate SF yellow alarm (i.e., twelfth SF framing bit =1, ALRM), ESF facility data link yellow alarm (RAI), loss of signal (i.e., reception of 128 or more consecutive zeros), and alarm indication signal (AIS, blue alarm or all ones alarm). Therefore, the MT8926/MT8976/ 77 combination supports a comprehensive alarm package. The PMAC alarm registers and counters are updated as the corresponding events occur. Once per frame (8000 times a second) the state of these registers and counters is recorded in a set of snap-shot registers. This data in the snap-shot registers is then inserted into the appropriate bit positions of the ST- BUS status stream CSTo. FDL bit-oriented messages can be communicated via the PMAC transmit and receive bit-oriented message registers. The user gains access to these registers through the ST-BUS control streams. Valid bit-oriented messages consist of a series of FIgure 3 - CSTi1 Channel Allocation Versus T1 Channels CSTi1 0-2 PCCW X 4-6 PCCW Tx BOM 8-10 PCCW PC W 12-14 PCCW LC W 16-18 PCCW X 20-22 PCCW X 24-26 PCCW X 28-30 PCCW X T1 1-3 4-6 7-9 10-12 13-15 16-18 19-21 22-24 Transmit Bit-Oriented Message Register PMAC Control Word Loopback Control Word Bit Function Transmitted First Transmitted Last Bit Function SER FER CRCR BPVR FSel 8KEn INTA FDLEn Bit 1 Function Normal Bit 0 Payload Loopback Line Loopback Enable Code (00001) Line Loopback Disable Code (001) PCCW = Per Channel Control Word
0XXXXXX0, where XXXXXX is the message content. PMAC’s DSTi0 pin is transferred to the PMAC DSTo. pin of the MT8976/77 framer. extracted clock and data from the T1 line interface. link extraction, and line loopback code detection. PMAC, therefore, CSTi1 will connect to both devices. references for both devices. E8Ko, under control of CSTi1.
- This is outlined in T ables 1 and 2.
Table 2. Master Status Word 2 Data Substitution Application section Figure 9 for FDL connections. loopback disable code generator, DSTi0 or DSTi1.
7 YLALR YLALR
6 MIMIC MIMIC
5 ERR ALRM
4 ESFYLW RAI
3 MFSYNC
2 BPV LOS
1 SLIP SLIP
7 BlAlm BlAlm
5 Xst Xst
4 BPVCnt SEI
3 BPVCnt FSI
2 CRCCNT CSI
1 CRCCNT BSI
0 CRCCNT AIS
Table 3. Master Status Word 1 (CSTo Channel 15) Note: Bits 2 to 7 of the Loopback Control Word are not used. Channel 11) is low, the ALRM bit will always be low. reset if more than three of 10 messages are in error. When receiving an SF signal, this bit will always be low. unaltered by the MT8926. See Master Status Word 1 of the MT8976 data sheet. ones density (48 ones in two or less frames) in the received signal. MT8976/77 is routed through the PMAC to the DSTi input of the MT8976/77. placed in the 24 T1 channels of DSTo, so it may be transmitted by the framer. placed in the 24 T1 channels of DSTo, so it may be transmitted by the framer. BPV counters may record errors.
interrupts for the control of the RAI interrupt. data link while the payload loopback is activated. calculated for each direction of transmission). Table 5. PMAC Miscellaneous Status Word (CSTo Channel 7) framed or unframed) is detected in the received T1 signal for at least five frames. (MT8976/77 Remote Loopback). loopback (MT8976/77 Remote Loopback). to a framed T1 signal. The framing error count is frozen if this bit is not set. checking for framing bits. If bit FSel is reset, then only FT bits are examined. 1 TMR Two Second Timer. This bit changes state once per second.
will connect to DSTi of the MT8976/77. seconds or more before the loopback action is taken. must be implemented for this feature to function. MT8976/77 Remote Loopback function. criteria is not met, FECV will be low. of-synchronization state (see Table 5). message-oriented performance data over the FDL. T1.403/408 FDL Message Transfer. 1SEC output, and thus, has a two second period. Table 6. D3/D4 or SF Frame Pattern
Table 7. Framing Bits which Affect the SE and are counted, bits marked "X" are excluded. always be low if FSel is low. bipolar code violation is received on the T1 interface. Table 8. Framing Error and Severely Errored Framing Event Counters (CSTo Channel 19) 14, CSTi1 channel 11) from high to low.
Table 9. CRC-6 Error Counter (CSTo Channel 11) Table 10. Bipolar Violation Counter (CSTo Channel 23) Table 11. Master Status Word 2 (CSTo Channel 31) Word and will remain clear as long as the INTA bit is low. high to low. Valid for ESF only. synchronization is regained.
- When the BPV counter wraps around the
channel 11 CSTi1, T able 14.
Table 12. Receive Bit-Oriented Message Register (CSTo Channel 27) Table 13. Transmit Bit-Oriented Message Register (CSTi1 Channel 7) sequence, which are 0XXXXXX0. out until bit 0 in the Control word is reset. The order of transmission is Bit 7 first. Bits 7 and 0 should be zero for a code word to be valid. must be transmitted for 32n + 32 ST-BUS frames.
Table 14. PMAC Control Word (CSTi1 Channel 11) (SEI bit, CSTo channel 31 bit 4). signal input at E8Ki will be output on E8Ko. See Figure 12 for timing. When 8KEn = 0, the E8Ko output will be high. (active low). See Pin Description, pin 20. 13, CSTi1 Channel 7). See Figure 7 for illustration. on FDLo. See Figure 19 for timing. to initiate the transmission of these messages. of Master Status Word 1 will be zero.
2 TO 1 MUX
PCW FDLEn = 1 - Transmission of a Bit-oriented Message over the FDL. PCW FDLEn = 0 - Transmission of an MT8952 (HDLC Controller) assembled message-oriented signal over the FDL. is in master mode. See the MT8976/77 data sheet. Figure 8. Functional Schematic of Interrupt Mechanism
- SEI is reset to 0 when INTA = 0.
** Delayed Frame Pulse occurs during Bit 7 of ST-BUS Channel 1.
cleared by some means external to the MT8926. and 17 for further information. Table 15. Interrupt States will remain in a high impedance condition. Armed state and the interrupt persists (see Figure 8). and MT8926 CRC error counters. ‡ G1 interrupts are cleared when SYN, ALRM, and RAI = 0. † The SYN interrupt indicates that a LOS or a AIS condition may exist. Note: AND denotes a logical and. Table 16. Group One (G1) Interrupt Activation and Clearing quiescent AND IRQ high impedance. quiescent and IRQ high impedance.
‡ G2 interrupts are cleared when SEI, FSI, CSI and BSI = 0. Note: AND denotes a logical and. Table 17. Group Two (G2) Interrupt Activation and Clearing from high to low. Valid for ESF only.
T able 18 for the ESF Framing Pattern. Table 18. ESF Frame Pattern
10 CB3
14 CB4
18 CB5
22 CB6
more complete definition of this protocol.
Figure 10 - Message-Oriented Performance Report Structure (from T1.403 and T1.408) FLAG SAPI C/R EA TEI EA CONTROL G3 LV G4 U1 U2 G5 SL G6 FE SE LB G1 R G2 Nm NI G3 LV G4 U1 U2 G5 SL G6 FE SE LB G1 R G2 Nm NI G3 LV G4 U1 U2 G5 SL G6 FE SE LB G1 R G2 Nm NI G3 LV G4 U1 U2 G5 SL G6 FE SE LB G1 R G2 Nm NI FCS 87 6 5 43 2 1 01111110 00111000 or 00111010 00000001 00000011 ONE-SECOND REPORT to to-1 to-2 to-3 ADDRESS 00111000 00111010 00000001 CONTROL 00000011 ONE-SECOND REPORT FCS Variable INTERPRETATION SAPI = 14, C/R = 0 (CI) EA = 0 SAPI = 14 C/R = 1 (Carrier) EA = 0 TEI = 0, EA = 1 INTERPRETATION Unacknowledged Information Transfer INTERPRETATION CRC Error Event = 1 1<CRC Error Event ≤ 5 5<CRC Error Event ≤ 10 10<CRC Error Event ≤ 100 100<CRC Error Event ≤ 319 CRC Error Event ≥ 320 Severely-Errored Framing Event ≥ (FE shall = 0) Frame Synchronization Bit Error Event ≥ 1 (SE shall = 0) Line Code Violation Event ≥ 1 Slip Event ≥ 1 Payload Loopback Activated Under study for synchronization Reserved (Default value is 0) One second report modulo 4 counter INTERPRETATION CRC 16 Frame Check Sequence G1 = 1 G2 = 1 G3 = 1 G4 = 1 G5 = 1 G6 = 1 SE = 1 FE = 1 LV = 1 SL = 1 LB = 1 U1, U2 = 0 R = 0 NmNI = 00, 01, 10, 11 OCTET # OCTET LABEL OCTET CONTENT
- Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. † Timing is over recommended temperature ranges and power supply voltages. † Timing is over recommended temperature & power supply voltage ranges. ‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. Absolute Maximum Ratings* Parameter Symbol Min Max Units 1 Power Supplies with respect to VSS VDD -0.3 7 V 2 Voltage on any pin other than supplies V SS -0.3 V DD +0.3 V
3 Current at any pin other than supplies 40 mA
4 Storage Temperature T
ST -40 125 °C
5 Continuous Power Dissipation P D 500 mW
Recommended Operating Conditions - Voltages are with respect to ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions
1 Operating Temperature T OP -40 85 °C
2 Power Supplies V DD 4.5 5.0 5.5 V 3 Input High Voltage V IH 2.4 V DD V Noise margin = 150 mV 4 Input Low Voltage V IL VSS 0.4 V Noise margin = 400 mV Parameters Sym Min Typ ‡ Max Units Test Conditions
1 Supply Current I DD 5 mA Outputs Unloaded
2 Input High Voltage V IH 2.25 V DD V 3 Input Low Voltage V IL VSS 0.8 V
4 Input Leakage Current I IL ±10 µA Digital Inputs
VIN=0 to VDD 5 Output High Current I OH 8m A V OH =2.4V 6 Output Low Current I OL 8m A V OL =0.4V Parameters Sym Min Typ ‡ Max Units Test Conditions
1 Input Pin Capacitance C I 10 pF
2 Output Pin Capacitance C O 10 pF
Parameters Sym Min Typ ‡ Max Units Test Conditions
1 Receive Data Setup Time t RS 0n s
2 Receive Data Hold Time t RH 30 ns
3 Extracted Clock Width t ECW 250 324 ns
4 Extracted 1.5 MHz Clock Period t P1.5 500 649 ns
† Timing is over recommended temperature & power supply voltage ranges. ‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. Note➀ - The PMAC is overwriting some of the bits received on CSTi0, and transmitting the aggregate on CST o. Line loopback codes are being transmitted on DSTo. Note② - The ST-BUS stream being received on CSTi0 is not being overwritten, but passes through the PMAC unaltered. DSTi0 and DSTi1 are not overwritten, but passes through the PMAC unaltered to the DST o output. Figure 13 - ST-BUS Timing - CSTo/DSTo Altered by PMAC Figure 14 - ST-BUS Timing - CSTo/DSTo Unaltered by PMAC Parameters Sym Min Typ ‡ Max Units Test Conditions
1 Clock to Output Delay ➀ tCOD 125 ns 150 pF load
2 ST-BUS Setup Time t STS 15 ns
3 ST-BUS Hold Time t STH 50 ns
4 Serial Output Delay② tSOD 35
CSTo, DSTo CSTi0/1 2.25V 0.8V 2.4V 0.4V 2.25V 0.8V BIT CELL BOUNDARIES tCOD tCOD tSTS tSTH DSTi0/1, CSTi0 DSTo, CSTo 2.25V 0.8V 2.4V 0.4V tSOD
† Timing is over recommended temperature & power supply voltage ranges. ‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. Figure 15 - ST-BUS Clock and Frame Pulse Timing † Timing is over recommended temperature & power supply voltage ranges. ‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing Figure 16 - 1SEC Timing Parameters Sym Min Typ ‡ Max Units Test Conditions
1 C2i Clock Period t 2P 400 488 600 ns
2 C2i Clock Width High or Low t 2W 200 244 300 ns
3 Frame Pulse Setup Time t FPS 50 ns
4 Frame Pulse Width High t FPH 50 ns
5 Frame Pulse Width Low t FPL 50 ns
Parameters Sym Min Typ ‡ Max Units Test Conditions 1 1SEC Output Delay t 1SD 95 ns 150 pF load C2i F0i 2.25V 0.8V 2.25V 0.8V t2P t2W t2W tFPS tFPH tFPL F0i C2i 1SEC 2.25V 0.8V 2.25V 0.8V 2.4V 0.4V t1SD t1SD
Figure 17 - Interrupt Functional Timing † Timing is over recommended temperature & power supply voltage ranges. ‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. Figure 18 - FDL Bit-oriented Message Timing Figure 19 - FDL Message-oriented Signal Timing Parameters Sym Min Typ ‡ Max Units Test Conditions
1 Data Link Output Delay t DOD 45 ns 150 pF load
2 Data Link Propagation Delay t DPD 40 ns 150 pF load
10 7 6 2 1 * 07 6* * t IOD tIOD Note: INTA Bit. IRQ is returned to High Z by INTA=0, INTA=1 in the previous frames. This can occur in frame n+1 or in a later frame. Condition initiating interrupt t IOD (IRQ Output Delay) is dependent on the IRQ pull-up resistor. Ch 11 Ch 12 Ch 31 Ch 0 1 * 76 2 1076 54 C2i F0i FDLo 2.4V 0.4V FDLi Data TxBOM Data tDOD *FDLEn = 1, FDLEn=0 in the previous frames. A AAA AA AAAAA A AAA A AAA A AAA A AAA A AAA A AAA FDLi FDLo 2.25V 0.8V 2.4V 0.4V tDPD Note: FDLEn = 0
Control and Status Register Summary Master Control Word 1 (Channel 15, CSTi0) Master Control Word 2 (Channel 31, CSTi0) Per Channel Control Words (All Channels on CSTi0 Except Channels 3, 7, 11, 15, 19, 23, 27 and 31) Transmit Bit-Oriented Message Register (Channel 7, CSTi1) PMAC Control Word (Channel 11, CSTi1) Loopback Control Word (Channel 15, CSTi1) Per Channel Control Words (All Channels on CSTi1 Except Channels 3, 7, 11, 15, 19, 23, 27 and 31) Phase Status Word (Channel 3, CSTo) 76 543 210 Debounce
1 Disabled
0 Enabled
1 B8ZS
0 Jammed
1 Set High
0 Cleared
1 Enabled
0 Disabled
ALL 1’s
1 ESF
0 D3/D4
Maint. 1 4/12 0 2/4 UNUSED - KEEP AT 0 Polarity
1 No Inversion
0 Inversion
1 Ch. looped back
0 Normal
S, FT, FPS
0 FT only
0 Disabled/
1 TxBOM-to-
0 FDLi-to-FDLo
00 Normal
01 Payload
10 LL Enable
11 LL Disable
Txt. Sig. Bit B Txt. Sig. Bit C Txt. Sig. Bit D Txt. Sig. Bit CHANNEL COUNT BIT COUNT
Appendix (continued) Control and Status Register Summary PMAC Miscellaneous Status Word (Channel 7, CSTo) Cyclic Redundancy Check-6 Error Counter (Channel 11, CSTo) Master Status Word 1 (Channel 15, CSTo) Severely Errored Framing Event and Error Counters (Channel 19, CSTo) Bipolar Violation Error Counter (Channel 23, CSTo) Receive Bit-Oriented Message Register (Channel 27, CSTo) Master Status Word 2 (Channel 31, CSTo) Per Channel Status Word (All Channels on CSTo Except Channels 3, 7, 11, 15, 19, 23, 27, 31) Note 1: In ESF mode: 1: CRC calc. ignored during Sync. 0: CRC checked for Sync. In D3/D4 mode: 1: Sync. to first correct S-bit pattern. 0: Will not Sync. if Mimic detected. 76 5 4 3 2 1 0 UNUSED LLDD
1 Detected
1 In-Sync
0 Out-of-Sync
1 Valid
0 Invalid
1 Not Detected
0 Detected
1 Out-of-Sync.
0 In-Sync
SEVERELY ERRORED FRAMING EVENT COUNTER (SE) FRAM ING ERROR COUNTER (FE) BPV ERROR COUNT Received First RxBOM Received Last BlAlm
0 XSt Low
1 SE Toggles
0 SER High-
1 FE F-to-0
0 FEF High-
1 CRC FF-
0 CRCR High-
1 BPV FF-to-
0 BPVR High-
Rec’d. Sig. Bit B Rec’d. Sig. Bit C Rec’d. Sig. Bit D Rec’d. Sig. Bit