MT8910-1 MITEL | Alldatasheet
Document overview
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Technical content
Features
- Compatible with ISDN U-Interface standard
- Over 40dB ( @ 40 kHz) of loop attenuation
- Full duplex transmission over single twisted pair
- Advanced echo cancelling technology
- High performance 2B1Q line code
- Full activation/deactivation state machine
- QSNR and line attenuation diagnostics
- Frame and superframe synchronization
- On-chip 15 second timer
- Insertion loss measurement test signal & quiet mode
- Mitel ST-BUS compatible
- Single 5V power supply
Applications
- ISDN NT1 and NT2 DSL interface
- Digital PABX line cards and telephone sets
- Digital multiplexers and concentrators
- Pair gain system
Description
The MT8910-1 Digital Subscriber Line Interface Circuit (DSLIC) is designed to provide ISDN basic rate access (2B+D) at the U-interface. Full duplex digital transmission at 160 kbit/s on a single twisted pair is achieved using echo cancelling hybrid (ECH) technology. This, in conjunction with the high performance 2B1Q line code, allows the DSLIC to meet the loop length requirements of the digital subscriber loops at the U-interface over the entire non-loaded telephone loop plant. The MT8910-1 is compatible with the complete range of Mitel Semiconductor ISDN components through the use of the ST-BUS interface. Figure 1 - Functional Block Diagram DSTi CDSTi MRST F0b C4b SFb F0od MS0 MS1 NT/LT CDSTo DSTo VSS AVSS VDD AVDD OSC2 OSC1 TSTin TSTout TSTen VRef VBias Lin+ Lin- Lout- Lout+Transmit Interface Control Register TRANSMIT/ RECEIVE TIMING & CONTROL INTERFACE Status Register Receive Interface Scrambler & Encoder Framing Maintenance Descrambler, Decoder & Diagnostics Jitter Compen- Linear Echo Canceller Non- Linear Compen- Decision Feedback Equalizer Quantizer DAC and Tx Filter Timing Adaptation Circuit Ton e Detector sator sator 2nd Order PDM ADC FIR Digital Filter Bias & Voltage Ref.
Ordering Information
MT8910-1AC 28 Pin Ceramic DIP MT8910-1AP 44 Pin PLCC 0°C to +70°C ISSUE 1 August 1993 MT8910-1 Digital Subscriber Line Interface Circuit Preliminary Information CMOS ST-BUS FAMILY
MT8910-1 Preliminary Information 9-4 Figure 2 - Pin Connections Pin Description Pin # Name Description DIP PLCC 11 L out- Line Out Minus. One of a pair of differential analog outputs for the 80 kbaud/s 2B1Q signal, biased at VBias. 23 L out+ Line Out Plus. One of a pair of differential analog outputs for the 80 kbaud/s 2B1Q signal, biased at VBias. 35A V SS Analog Ground. Tie to VSS . 46T S T i n I/O Structure Test Input. When TSTen is high, TSTin is used as a source to all output drivers. Refer to “I/O Structure Test" in functional description for more details. Tie to VSS for normal operation. 5 8 CDSTi Control/Data ST-BUS Input. A 2048 kbit/s serial PCM/data input for the D- and C-channels in Dual mode. Unused in Single mode and should be connected to VSS . 61 2 D S T i Data ST-BUS Input. A 2048 kbit/s serial PCM/data input for the D-, C-, B1- and B2- channels in Single mode. In Dual mode, only the B-channels are input. 71 3 V SS Ground. 81 4D S T o Data ST-BUS Output. A 2048 kbit/s serial PCM/data output for the D-, C-, B1- and B2- channels in Single mode. In Dual mode, only the B-channels are output. This output is placed in high impedance during the unused channel times. 9 15 CDSTo Control/Data ST-BUS Output. A 2048 kbit/s serial PCM/data output for the D- and C- channels in Dual mode. It is placed in high impedance in Single mode, and during the unused channel times in Dual mode. 10 16 F0od Delayed Frame Pulse Output. A 244 ns wide negative going pulse indicating the end of the active ST-BUS channel times of the device to allow for daisy-chaining of other ST-BUS devices. Active after channel 0 in Dual Port mode and Channel 3 in Single Port Mode. 11 18 TSTout I/O Structure Test Output. When TSTen is high, the TSTout provides the output of an XOR chain which is sourced from all digital inputs. Refer to “I/O Structure Test" in functional description for more details. Leave unconnected for normal operation. 12 19 MS0 Mode Select 0. CMOS input. Refer to Table 1. 13 20 MS1 Mode Select 1. CMOS input. Refer to Table 1.
44 PIN PLCC
28 PIN CERDIP
2318 19 20 21 22 24 25 26 27 28 17 29 NC AVDD NC NC NC IC VDD MRST OSC1 OSC2 NC NC CDSTi NC NC NC DSTi VSS DSTo CDSTo F0od NC
Preliminary Information MT8910-1 9-5 14 21 NT/LT NT/LT Mode Select. CMOS Input. When high, the DSLIC is setup in NT mode. When low, LT mode is selected. 15 22 TST en I/O Structure Test Enable Input. This active high input enables the built-in test of all digital input and output structures. Refer to “I/O Structure Test" in functional description for more details. Tie to V SS for normal operation. 16 23 SFb Superframe Pulse. In LT mode, an input pulse once every superframe (12 ms) which, when low during a falling edge of C4b within an F0b low pulse, sets the transmit superframe boundary. In NT mode, a 244 ns wide output pulse once every 12 ms indicating the boundary of the transmit superframe. In NT mode, the superframe timing is generated from the line signal time base and, as such, SFb will only be valid once the transceiver has achieved full activation. 17 25 C4b 4096 kHz Data Clock. In LT mode, a 4096 kHz ST-BUS clock input. In NT mode, a 4096 kHz ST-BUS clock output frequency locked to the line signal. 18 27 F0b Frame Pulse. In LT mode, an 8 kHz input pulse indicating the start of the active ST-BUS channel times. In NT mode, an 8 kHz output pulse extracted from the line signal indicating the start of the active ST-BUS channel times. 19 30 OSC2 Oscillator Output. When the MT8910-1 operates with an External Clock (typically LT mode) connect OSC2 to the output of an external inverter providing a 10.24 MHz ±5ppm clock (see “10.24 MHz Clock Interface" section). When operating with a crystal (typically NT mode) connect one lead of the fundamental mode parallel resonator crystal (10.24 MHz ±50ppm in case of NT mode). 20 31 OSC1 Oscillator Input. When the DSLIC operates with an External Clock (typically LT mode) connect OSC1 to the input of an external inverter (see Fig.11). When operating with a crystal (typically NT mode) connect the other lead of the fundamental mode parallel resonator crystal (10.24 MHz ±50ppm in case of NT mode). 21 32 MRST Master Reset. Active low CMOS input performs a master reset of the DSLIC. 22 33 V DD Power Supply Input. 23 34 IC Internal Connection. Leave unconnected. 24 38 AV DD Analog Power Supply. Connect to VDD . 25 41 V Bias Bias Voltage. Decouple to AVSS through a 1.0 µF ceramic capacitor. 26 42 V Ref Reference Voltage. Decouple to AVSS through a 1.0 µF ceramic capacitor. 27 43 L in- Line Signal Input Minus. Internally biased at VBias. 28 44 L in+ Line Signal Input Plus. Internally biased at VBias. 2,4,7, 9 -11, 17,24 26,28 29,35 36,37 39,40 NC No Connection. Leave circuit open. Pin Description (continued) Pin # Name Description DIP PLCC
MT8910-1 Preliminary Information 9-6 Functional Description The MT8910-1 Digital Subscriber Line Interface Circuit (DSLIC) is a high performance, full duplex transceiver which provides a complete interface to the U-reference point as specified in ANSI T1.601- 1988. Operating in either master Line Terminator (LT) mode or slave Network Terminator (NT) mode, the DSLIC can be configured to operate at either end of the Digital Subscriber Line (DSL). The DSLIC supports full duplex transmission of a 2B + D- channel format at 160 kbit/s over a single twisted pair with about 40 dB of loop attenuation at 40 kHz. T o achieve this transmission performance, the DSLIC uses a 2B1Q line code which is a four level pulse amplitude modulated (PAM) signal with no redundancy. This line code was approved by the American National Standards Institute technical committee T1E1. Using this line code, two binary bits are converted into one four level quaternary symbol. This results in an effective baud rate reduction from 160 to 80 kbaud/s allowing the transmission to benefit from reduced line attenuation and improved immunity to near end crosstalk (NEXT). T o complement the performance of the 2B1Q line code, the DSLIC uses an advanced echo cancelling hybrid (ECH) technique, by means of a transversal filter, that provides greater than 60 dB of echo cancellation. This cancellation, along with all equalization, is performed in the digital domain using dedicated DSP hardware. Since a digital transversal echo canceller gives a linear representation of the echo, the MT8910-1 also has a non-linear echo canceller which works in parallel with the transversal filter to compensate for non-linearities in the transmit path and the passive line termination. In addition, a jitter compensator is used to correct errors in the echo estimates which are sourced from corrections in the received timebase. The jitter compensator will interact directly with the echo taps in the transversal filter. A block diagram of the DSLIC is shown in Figure 1. The DSLIC has two ports consisting of a serial system interface (Mitel's standard ST-BUS), and a line port which interfaces directly to the single twisted pair via a passive termination hybrid and a line pulse transformer. The two B-channels and the D-channel to be transmitted on the line are input to the DSLIC (on the ST-BUS) into the transmit interface block. The sync word and maintenance bits are added to the data which is then formatted, scrambled and digitally encoded into 2B1Q symbols. This digital representation is passed through a finite impulse response filter which converts the digital representation into an analog waveform. The transmitted pulse is then passed through a smoothing filter whose output is passed to a differential line driver which is driving the line through a passive hybrid network and line pulse transformer. On the receive side, the pre-cancelled signal drives a balanced receiver which feeds the input to an over- sampled second-order delta sigma A/D converter. The digital representation of the received signal yields a Pulse Density Modulated (PDM) stream which is digitally filtered and decimated to the 80 kHz baseband. Intersymbol interference (ISI) introduced by the loop is cancelled by a decision feedback equalizer. This is achieved by taking a convolution of the received pulse with the estimated impulse response of the loop. The cancellation of ISI is performed in parallel with the echo cancellation. Estimated received echo is obtained by taking the convolution of the transmit signal with the estimated impulse response of the loop. Feedback from the jitter compensator and the non-linear corrector interact with the coefficients of the echo canceller to reduce the error introduced by jitter and non- linearities in the analog circuitry. The output of all these blocks is summed together and the result is the received data which is passed through a decoder and descrambler before being sent out in TDM bursts on the ST-BUS. Line Port The DSLIC interfaces to the U-reference point as defined in the ISDN Basic Access Reference model. As such, the transceiver transfers full duplex, time division multiplexed data at 160 kbit/s. This includes two 64 kbit/s PCM voice or data channels (B- channels), a 16 kbit/s signalling channel (D-channel) and 16 kbit/s for synchronization and overhead. The two 64 kbit/s channels are defined as the B1- and B2-channels and they carry subscriber information such as digitally encoded voice, circuit switched data or packet switched data. The DSLIC will transfer both B-channels transparently from the ST-BUS port to the line port and vice versa once the device has acquired superframe synchronization. The 16 kbit/s D-channel is primarily intended to carry signalling information for circuit switching the B- channels through the ISDN network. The D-channel can optionally carry packetized information and telemetry services. The D-channel is transmitted transparently through the DSLIC from the ST-BUS port to the line port and vice versa once the device has acquired superframe synchronization. It is to be
Preliminary Information MT8910-1 9-7 noted that the system interface has dedicated a full 64 kbit/s for the D-channel of which only the two first bits (D0 and D1) are actually carrying information. The other bits of the ST-BUS D-channel are reserved for future use. A third type of channel, the C-channel, is a non- bearer channel which provides a means for the system to control and monitor the functionality of the DSLIC. This control/status channel is accessed by the system through the ST-BUS. The C-channel provides access to three control registers and four status registers which provide complete control or status of all built-in features. Access to the control register is provided by two bits in the Control Register itself (CRS0 and CRS1). Selection of the desired status register is performed using two bits in Control Register 1 (SRS0 and SRS1). The C- channel also carries a control and status register for the 4 kbit/s M-channel which can be used as an additional maintenance channel. A detailed description of these registers is discussed in the ST- BUS port interface section. Line Code The DSLIC transceiver uses the 2B1Q line code which is a four level Pulse Amplitude Modulated (PAM) code with no redundancy. The generation of the 2B1Q signal is achieved by grouping two consecutive bits into a bit field of which the first bit represents the sign bit and the second represents the magnitude. This yields four possible output codes as shown in Figure 3 (note that +3, +1, -1 and -3 are only symbols and they do not reflect the voltage on the line). The bit fields are grouped relative to the borders of the defined channels where the first bit field consists of bit 1 and bit 2 of the B1-channel, the second bit field consists of bit 3 and bit 4 of the B1-channel and so on. Before converting the bit fields into output symbols, all bits except the framing pattern are scrambled with polynomials: ⊕ x-5 ⊕ x-23 for LT 1 ⊕ x-18 ⊕ x-23 for NT (where ⊕ is modulo two summation) Framing The frame structure in the DSLIC is 1.5 ms long and consists of twelve 2B+D-channels delimited by the framing pattern at the start of the frame and the maintenance channel at the end. Framing for both the LT and the NT is performed using a 9 symbol synchronization word. This sync word (SW) has the following structure: Eight DSLIC frames are grouped into a superframe delimited by inverting the sync word (ISW):-3,-3, +3, +3, +3, -3, +3, -3, -3. This second level of framing is used to assign the M-channel bits as defined in the ANSI T1.601-1988. The framing structure is shown in Figure 4. Transmission between the LT and NT is fully synchronous. As such, the frame/superframe boundaries between the NT receive frame and the NT transmit frame have a fixed phase relationship. The transmitted frame/superframe from the NT is delayed by 60 ± 2 quaternary symbols (quats) with respect to its received frame/superframe. Since the NT extracts all its timing from the line, the DSLIC will maintain the required phase relationship between the frames and superframes and will insert the SW and ISW during the proper time interval. Figure 3 - Example of 2B1Q Quaternary Symbols time BITS 0 1 1 0 1 1 0 0 0 0 1 1 1 0 0 0 0 1 0 1 1 1 0 1 0 0 1 0 1 0 0 1 1 1
Preliminary Information MT8910-1 9-9 T1.601-1988 standards. The activation sequence for the DSLIC is mode dependent and is outlined in Figures 6a) and b). In the LT mode, the request for activation can be initiated in two ways. Setting the start/stop bit in the Control Register 1 will result in the generation of a repeated pattern of four +3 symbols followed by four -3 symbols producing a 10 kHz activation tone (TL) for 3 milliseconds. The DSLIC can also be activated by receiving a 10 kHz activation tone from the NT (TN). Once the NT has generated a tone, progression through the state machine follows the algorithm as shown in Figure 6a. In the NT mode, the request for activation can be initiated in two ways. Setting the start/stop bit in the Control Register 1 will result in the generation of a repeated pattern of four +3 symbols followed by four -3 symbols resulting in the transmission of the NT activation tone (TN). The DSLIC can also be activated by receiving TL from the LT to which the NT will respond with its own activation tone (TN). Progression through the state machine will follow the algorithm as shown in Figure 6b. During the activation sequence, there is an extensive exchange of signals between the LT and the NT . This handshaking of information is required to allow individual transceivers to train both their echo cancellers and decision feedback equalizers. All possible signals are described below.
- TN: A 10 kHz activation tone sourced by the NT which is generated by sending a continuous pattern of four +3 symbols followed by four -3 symbols.
- SN0: SN0 is a no signal condition which is used to indicate to the LT that the NT has finished training its echo canceller.
- SN1: An NT generated signal consisting of a framed (but not superframed), scrambled 2B1Q signal which carries all 1s in the B-, D- and M-channels. This signal is used to train the NT’s echo canceller.
- SN2: An NT generated signal consisting of a framed (but not superframed), scrambled 2B1Q signal which carries all 1s in the B-, D- and M-channels. This signal is used to train the LT’s DFE.
- SN3: An NT generated signal consisting of a fully framed and superframed scrambled 2B1Q signal which carries information in all the B-, D- and M-channels. Figure 6a - Activation/Deactivation State Diagram - LT Mode Alerting Tx-TL (3ms) Awaiting Reply Tx-SL0 MRST Pin Full Reset Tx-SL0 Awake Tx-SL0 EC Training Tx-SL1 Framing Tx-SL2 Active Tx-SL3 RCV Reset Tx-SL0 Pending Deact. Tx-SL0 LAR ST.T0 Expiry of T2 RCV TN ST.T0 STP.T2 Expiry of T0 Expiry of T0 Expiry of T0 BFS Lost > 480ms1 or LDR ST.T3 ST.T3 (Loss of signal and LDR), ST.T2 STP.T3 (Loss of signal and LDR) or Expiry of T3 RCV TN ST.T0 End SN1 EC Converged SFS STP .T0 Expiry of RCV TN STP.T1 Expiry of T0 ST.T3 ST.Tx = Start Timer x STP.Tx = Stop Timer x LAR = Local Activation Request LDR = Local Deactivation Request SFS = Superframe Synchronization Acquired T0 = 15 sec timer T1 = 480 ms timer T2 = 40 ms timer T3 = 520 ms timer Note 1: Loss of received signal will result in loss of sync. ST.T1
MT8910-1 Preliminary Information 9-10
- TL: A 10 kHz activation tone sourced by the LT which is generated by sending a continuous pattern of four +3 symbols followed by four -3 symbols.
- SL0: SL0 is a no signal condition generated from the LT .
- SL1: An LT generated signal consisting of a framed (but not superframed), scrambled 2B1Q signal which carries all 1s in the B-, D- and M-channels. This signal is used to train the LT’s echo canceller.
- SL2: An LT generated signal consisting of a fully framed and superframed scrambled 2B1Q signal which carries all 0s in the B- and D-channels with information in the M-channel. This signal is used to train the NT’s DFE.
- SL3: An LT generated signal consisting of a fully framed and superframed scrambled 2B1Q signal which carries information in all the B-, D- and M-channels. Figure 6b - Activation/Deactivation State Diagram - NT Mode MRST Pin Full Reset (Power down Tx-SNO RCV TL or LAR ST.T0 Expiry of T2 RCV Reset Tx-SN0 Alerting Tx-TN (9 ms) EC Training Tx-SN1 Expiry of T0 Expiry of T1 Quiet Tx-SN0 Expiry of T0 Signal Detected STP.T1 Expiry of T0Train DFE/Timing Tx-SN0 SL2 Detected Framing Tx-SN2 SFS Active Tx-SN3 LDR ST.T3 Pending Deact. Tx-SN3 Loss of far-end signal STP.T3 ST.T2 ST.T3 ST.T3 Expiry of T3 Loss of signal STP.T3 ST.T2 Tear Down Tx-SN0 Loss of BFS > 480ms1 ST.T3 ST.Tx = Start Timer x STP.Tx = Stop Timer x LAR = Local Activation Request LDR = Local Deactivation Request SFS = Superframe Synchronization Acquired T0 = 15 sec timer T1 = 480 ms timer T2 = 40 ms timer T3 = 520 ms timer Note 1: Loss of received signal will result in a loss of sync. EC Converged ST.T1 RCV TL ST.T0 STP.T2
Preliminary Information MT8910-1 9-11 The reset state consists of two substates, the receive reset state and full reset state. The full reset state is entered following a power-up or after the expiry of the receive reset timer (40 ms). The receive reset state is a transient state which is entered once the DSLIC has detected a loss of received signal while the transceiver is not transmitting. In this state, the transceiver will not initiate the start-up sequence but is capable of responding to the appropriate activation tone. When the timer in the receive reset state has timed out (40 ms), the transceiver enters the full reset state. All timers surrounding the reset states are included in the DSLIC and have been set as per the ANSI- T1.601-1988:
- Failure to complete a start-up sequence timer is set at 15 seconds.
- Loss of received signal timer is set at 480 ms as is the loss of synchronization.
- The receive reset state timer is set to 40 ms.
- A fourth timer (not specified in ANSI T1.601-1988) has been included which will restrict the time to 520 ms for a deactivation sequence. The DSLIC will enter a deactivated state on the assertion of a deactivation request (setting the Start/ Stop bit to 0 in Control Register 1, and the subsequent loss of the received signal). Once the deactivation process has been completed, the request for activation can follow a warm start process as defined in ANSI T1.601-1988. Loop Performance The MT8910-1 operates on a digital subscriber line (DSL) which is a two wire twisted pair metallic medium typically used for transmission between the central office (LT) and the customer premise equipment (more commonly referred to as "Basic Access Interface on the Network side of the NT"). The MT8910-1 is production tested for error free performance for 2.5 sec (20,000 ST-BUS) frames over a 4.6km (15 kft) 26 AWG simulated loop (equivalent to 40dB attenuation @ 40 kHz). ST-BUS Interface The ST-BUS is a synchronous time division multiplexed serial bussing scheme with data streams operating at 2048 kbit/s configured as 32, 64 kbit/s channels (refer to Figure 7). Synchronization of the data transfer is provided from a frame pulse which identifies the frame boundaries and repeats at an 8 KHz rate. Figure 7 shows how the frame pulse (F0b defines the ST-BUS frame boundaries. All data is clocked into the device on the rising edge of the 4096 kHz clock (C4b ) three quarters of the way into the bit cell, while data is clocked out on the falling edge of the 4096 kHz clock at the start of the bit cell. The bits on the ST-BUS are numbered bit 7 to bit 0 as outlined in Figure 7. Information transferred from the system port to the line port, will maintain the integrity of the bit order. All timing signals, i.e., F0b , C4b and SFb , are bidirectional. The I/O configuration of these pins is controlled by the mode of operation (LT or NT). In the LT mode, these timing signals must be supplied from an external source and the MT8910-1 will in turn uses these timing signals to transfer information to and from the line port or the ST-BUS port. In the NT mode, timing is generated from an on board digital phase locked loop which extracts timing from the received data on the DSL and generates the system frame pulse (F0b ), the system 4096 kHz clock (C4b) and the system superframe pulse (SFb). The superframe timing signal (SFb) is an active low signal with a period of 12ms which is required to provide a reference for structuring the maintenance channel (M channel). In the LT mode, the SFb is an input which, when set low during the system frame pulse (F0b ), will set the phase of the transmit superframe. As an alternative, the SFb pin can be tied high and the device will automatically establish Figure 7 - ST-BUS Functional Timing F0b C4b ST-BUS Bit Cells CHANNEL 31 BIT 0 CHANNEL 0 BIT 7 CHANNEL 0 BIT 6 CHANNEL 0 BIT 5 CHANNEL 0 BIT 4 CHANNEL 0 BIT 3 CHANNEL 0 BIT 2
subsequent devices in the daisy chain configuration. having contention on the system bus.
- With MS0=1, the D-channel is found in timeslot
Table 1. Truth Table for Mode Select Pins Control Register as described following.
11 R e s e r v e d
to the B2-channel at the system interface. detection protocol used over the M-channel.
recognized if the transceiver is in a full reset state. is not in the active state will be ignored. supported on the DSLIC as outlined in Table 3. the transceiver is being used over long loops. Table 2. Control Register 1 high or low. Not used in NT mode.
4 BSWAP When this bit is set to 1, the location of the B1 channel on the ST-BUS is swapped with the
location of the B2 channel. This affects both directions of the ST-BUS. 3 CCRC Corrupt CRC. When set to 1, the 12 bit CRC transmitted on the line is corrupted. transparency of network is achieved (indicated by act=1). 1, 0 CRS1, CRS0 Control Register Select 1 and 0. Must be set to 0, 0 to address Control Register 1.
Table 3. Control Register 2 Table 4. Control Register 3 DS4 - DS1 Diagnostic Select Bits.
0001 B 1 S T i t o S T o L oopback 1
0010 B 2 S T i t o S T o L oopback 1
0011 B 1 + B 2 S T i t o S T o L oopback 1
0101 B 1 S T o t o S T i Loopback 2
0110 B 2 S T o t o S T i Loopback 2
0111 B 1 + B 2 S T o t o S T i Loopback 2
1001 A L L L out to Lin Loopback 1 3
card to exchange static data in the B- and D- channels. MSWAP can also be used in the NT mode. 1, 0 CRS1, CRS0 Control Register Select 1 and 0. Must be set to 0, 1 respectively to address Control Register 2. 1, 0 CRS1, CRS0 Control Register Select 1 and 0. Must be set to 1, 0 respectively to address Control Register 3.
access to the transmit M-bits as shown in T able 4. three control registers assuming a reset state. Table 5. Status Register 1 7,6 SRID1, SRID0 Status Register ID. Always reads 0,0 when Status Register 1 is output. 5,4,3 IS2, IS1, IS0 Internal State Indication. 2 RxSFIB Received superframe Indication. When low, indicates the beginning of the received superframe. This bit is low for one ST-BUS frame, then high for 95 ST-BUS frames. 1 RSV Reserved. Always read a 0.
0 CRCERR When “1”, the received CRC code did not match with a locally generated CRC code, indicating
boundary in both the LT and NT modes. updated once every superframe. QSNR should be greater than 15.7dB. the RPA bits is shown in Table 7. Table 6. Status Register 2 7,6 SRID1, SRID0 Status Register ID. Always reads 0, 1, respectively, when Status Register 2 is output. 0 NA Reserved. Always reads 0.
Table 7. Status Register 3 Table 8. Status Register 4 Table 9. Maintenance Channel Bit Assignment on ST-BUS Port 7,6 SRID1, SRID0 Status Register ID. Always reads 1, 0, respectively, when Status Register 3 is output. RPA4-RPA0 Receive Pulse Amplitude bits (see Note 1). cable attenuation for a 2B1Q pulse. termination and transformer (ADC Gain = 0). 0 RSV Reserved. Always reads 0. 7,6 SRID1, SRID0 Status Register ID. Always reads 1, 1, respectively, when Status Register 4 is output. structuring of the received M-bits.
Preliminary Information MT8910-1 9-19 Status Register 4 When SRID1=1 and SRID0=1, the contents of the Status Register 4 are being output in the C-channel allowing the system to monitor the received maintenance channel bits M1 to M6 as specified in T able 8. The received M-bits may carry the EOC message (with overhead) as specified in T1.601- 1988. Refer to the “Maintenance Channel“ section for further details. Maintenance Channel The MT8910-1 has provisions for transmitting and receiving a 4 kbit/s maintenance channel from the system port to the line port. The maintenance channel at the line port is structured into six columns of which M5 and M6 carry the results of a CRC calculation (refer to Table 9). All bits except these CRC bits are treated as a transparent channel to the MT8910-1. The 12 bit cyclical redundancy check is computed using the generator polynomial: x 12 ⊕ x11 ⊕ x3 ⊕ x2 ⊕ x ⊕ 1 (where ⊕ is modulo two summation) The CRC calculation covers all 2B + D-channels within a superframe as well as the M4 column within the maintenance channel. Access to the maintenance channel is granted through Control Register 3 (Tx M-Channel) and Status Register 4 (Rx M-Channel) and is structured on the ST-BUS port as shown in T able 9. The Tx M- bits for all DSL basic frames are written to Control Register 3 once every 1.5ms within the ST-BUS frames indicated in T able 9. If the user fails to update the contents of Control Register 3 within the allocated window, the M-bits will be substituted by ones until the information in Control Register 3 is updated. On the receive path, the Rx M-bits from each DSL basic frame are available in Status Register 4 within the ST-BUS frames indicated in T able 9. The Rx M-bits will be updated every DSL basic frame (or 1.5 ms). The M-bits are structured according to the transmit and receive superframe boundary signals output on the ST-BUS. The transmit superframe boundary is defined relative to the input or output SFb signal. (In LT mode, the transmit superframe boundary can also be defined in the frame following the TxSFB bit being set to zero.) The ST-BUS frame in which the SFb signal is active is defined as transmit frame 0. The superframe boundary in the receive path is defined relative to the RxSFIB bit found in Status Register 1. The ST-BUS frame with RxSFIB=0 is defined as the receive frame 0. The functional timing diagram for the phase of the SFb and RxSFIB signals for both the LT and NT modes is shown in Figure 10. In applications which do not utilize the maintenance channel, 2B+D data at the NT and the LT should be all set to 0 or 1 until activation occurs at the LT . Since the NT trains up before the LT , the activation at the LT can be detected at the NT by the reception of random data. Only then the NT can transmit normal 2B+D data. Figure 10 - Functional Timing for Superframe Signals ISW 12x(2B + D) M SW 12x(2B + D) M SW 12x(2B + D) ISW 12x(2B + D) M SW 12x(2B + D) M ISW 12x(2B + D) M SW 12x(2B + D) M SW 12x(2B + D) ISW 12x(2B + D) M SW 12x(2B + D) M LT Mode NT Mode Tx Line Signal Rx Line Sigmal SFb pin RxSFIB bit Rx Line Signal Tx Line Signal SFb pin RxSFIB bit 7 ST-BUS Frames
10.24 MHz Clock Interface
- This is typically used in LT mode. To meet the
capacitor connected to its output and the ground. signal fed to the internal blocks of the MT8910-1. providing an input signal (TSTin) to all output drivers.
- The TSTout pin will carry the output of the XOR
Table 10. I/O Structure Test Vectors
Preliminary Information MT8910-1 9-21 Figure 11 - Typical Connections for LT Mode (Single Port) OSC1 OSC2 C4b F0b SFb DSTi DSTo MS0 MS1 NT/LT TSTin TSTen CDSTi MRST VSS AVSS VDD AVDD Lout+ Lin+ Lin- Lout- VBias VRef CDSTo IC TSTout F0od 74HC04
10.24 MHz Clock
4.096 MHz Clock
1µF 0.1µF 0.1µF 1:1.3 1.5µF 1.0µF1.0µF TO LINE FEED SUPPLY TO NEXT DSLIC IN CHAIN 1µF MT8910-1 M H PLT *Duty cycle: 45% to 55% MRST , OSC1, C4b , F0b and SFb. TST out=0 if all input signals carry an even number of ones and TSTout=1 if all input signals carry an odd number of ones. The I/O structure test also allows the verification of the connection between the digital output pins and the printed circuit board. After running the initialization sequence, the I/O structure output test can be enabled by setting the TSTen to a logic high with the mode select pins MS0, MS1 and NT/LT set to 1, 1, 0 respectively. This causes all digital outputs to be driven from the I/O structure test input (TSTin) pin1. The outputs affected include the DSTo, CDSTo, F0od and TSTout These same outputs can also be placed into a high impedance state to allow the bed-of-nails tester or some other in-circuit tester to drive a known signal or pattern on any circuitry that may be connected to the output pins of the MT8910-1. The high impedance state is enabled by running the initialization pattern described above then setting TSTen to a logic one with the mode select pins MS0, MS1 and NT/LT set to 1, 0, 0 respectively. Note 1: Allow a propagation delay of approximately 800ns from digital input to XOR output or TSTin to any digital output. The typical connection diagrams are shown in Figures 11 and 12. In Figure 11, the MT8910-1 receives all its timing from the system including the C4b , F0b and a frequency-locked 10.24 MHz master clock. In Figure 12, the MT8910-1 is configured in the NT mode which implies that all timing signals including the F0b, C4b and SFb are being sourced from the MT8910-1. These timing signal are generated from an internal DPLL which divides a
10.24 MHz reference frequency down to a baseband
160 kHz. A comparison is performed on the reference signal with the received line signal to determine if the timing signals on the MT8910-1 have to be corrected. The MT8910-1 is interfaced to the transmission line through the Passive Line Termination network (PLT) and transformer. The PLT provides the two to four wire conversion and additional frequency compensation for the received signal. The whole circuit is DC isolated from the line by the low inductance transformer.
MT8910-1 Preliminary Information 9-22 Figure 12 - Typical Connections for NT Mode (Single Port)
10.24 MHz
1.5µF M H PLT V DD 0.1µF 1µF 0.1µF 1µF 1.0µF1.0µF VDD AVDD Lout+ Lin+ Lin- Lout- VBias VRef CDSTo IC TSTout F0od OSC1 OSC2 C4b F0b SFb DSTi DSTo MS0 MS1 NT/LT TSTin TSTen CDSTi MRST VSS AVSS MT8910-1 Passive Line Termination Network (PLT) The termination network is an all passive circuit which allows the MT8910-1 to interface to the DSL line through a line pulse transformer. The passive line termination consists of three blocks which includes a hybrid network, a compensator circuit and a line pulse transformer (refer to Figures 13 and 14). The hybrid network is a 2 to 4 wire converter which provides limited precancellation of near end echo. The hybrid specified in Figure 13 was optimized for the specified transformer and a 10 ohm series protection resistor (Rp). The compensator circuit, in conjunction with the transformer, acts as a high pass filter which is designed to increase the cut-off frequency in the receiver path. This has the effect of reducing the low frequency content in the received line signal which in turn reduces the effects of ISI and near end echo thereby improving transceiver performance. The low inductance transformer allows for the possibility of passing a sealing current and/or phantom feed supply through the secondary winding without saturating the magnetic core. The transformer specified in Figure 14 has been designed to carry typically 50 mA of DC current. Transformer Specification All subscriber equipment which is to be connected to a digital subscriber line, must deliver an output pulse which satisfies both the pulse template and the pulse PSD as specified earlier. The output drive characteristics of the MT8910-1 requires a transformer with a turns ratio of 1:1.3 having the electrical characteristics specified in Figure 14. For supporting initial design activities, Mitel Semiconductor has made available the MB6024 Magnetic Kit which contains the transformer shown in Fig. 14.
Preliminary Information MT8910-1 9-23 Figure 13 - Passive Line Termination (PLT) Figure 14 - Transformer Specification Lout+ Lin+ Lin- Lout- 680 pF 3.3 nF R s = 30.2 Ω R b1 1.6 KΩ R b2 1 KΩ
130 KΩ 20 KΩ
68.2 KΩ 7.8 KΩ 680 pF 3.3 nF Note 1: All resistors have a tolerance of ±1% unless indicated otherwise. All capacitors have a tolerance of ±10%. Note 2: May be incorporated on to a ceramic substrate. R b2 1 KΩ R b1 1.6 KΩ XFM+ XFM- 7 mH 1:1.3 5.5 mH 5.5 mH 1.5 µF 10 Ω ±10% 10 Ω ±10% Power Feed/Extract R s = 30.2 Ω NOTES: ➀ Open Circuit Secondary ② Open Circuit Primary ➂ With pins 1 and 11 shorted together ➃ Filtran Part Number TPW 4671 ➃ TURNS RATIO RESISTANCE INDUCTANCE Leakage Inductance (Sec. Short Circuit) < 75µH @ 40 kHz. LONGT. BAL. 1:1.3 R 1 = 5-8 3.7 Ω R 2 = 2-12 6.8 Ω LP = 5-8 7 mH LS = 2-12 11 mH 0 - 4 kHz 4-160 kHz min 63 dB min 58 dB
MT8910-1 Preliminary Information 9-24 Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Note 1: Except for V DD , AVDD , VSS , AVSS , Lout+ and Lout-. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Note 1: To obtain optimum line performance, noise level on supply must be less than 25 mVpp. Absolute Maximum Ratings* Parameters Symbol Min Max Units 1 Supply Voltage V DD -0.3 7.0 V 2 Voltage on any I/O pin V I/O -0.3 V DD +0.3 V
3 Current on any I/O pin I I/O 20 mA
4 Storage Temperature T ST -55 125 °C
5 Package Power Dissipation P D 1000 mW
Recommended Operating Conditions - Voltages are with respect to ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions 1 Supply Voltage V DD 4.75 5.00 5.25 V (see Note 1) 2 Analog Supply Voltage AV DD 4.75 5.00 5.25 V Relative to AV SS (Note 1)
3 Input Low Voltage (except OSC1,
MRST , MS0, MS1, NT/LT VIL 0.4 for 400mV noise margin
4 Input High Voltage (except OSC1,
MRST , MS0, MS1, NT/LT VIH 2.4 V for 400mV noise margin
5 Input Low Voltage for OSC1/2,
MRST , MS0, MS1, NT/LT V IL 1.0 V
6 Input High Voltage for OSC1/2,
MRST , MS0, MS1, NT/LT VIH 4.0 V
7 Operating Temperature T A 07 0 °C
Characteristics Sym Min Typ ‡ Max Units Test Conditions I N P U T S Input High Voltage (except OSC1, MRST , MS0, MS1, NT/LT VIH 2.0 V
2 Input Low Voltage (except OSC1,
MRST , MS0, MS1, NT/LT VIL 0.8 V
3 Input High Voltage for OSC1/2,
MRST , MS0, MS1, NT/LT VIH 3.0 V
4 Input Low Voltage for OSC1/2,
MRST , MS0, MS1, NT/LT V IL 2.0 V
5 Input Leakage Current (except
OSC1) IIL 10 µA V IN = VSS to VDD
6 Input Current for OSC1 I IC 50 100 µA V IN = VSS to VDD
7 Input Impedance (L in- to Lin+)Z in 250 k Ω @ DC
Preliminary Information MT8910-1 9-25 ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. (1) except OSC2 Note 1) This is a specification on the maximum parallel capacitance to AC ground, connected directly to the pins. Higher capacitance is acceptable when placed in series with resistor networks such as the line termination impedance. 2) Not production tested. Figure 15 - External Clock Timing in LT Mode † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Notes: 1) External clock tolerance of ±5 ppm in LT mode or ±50 ppm in NT mode is required. 2) Absolute jitter on OSC2 must be less than 2.0ns RMS in order to maximize performance. 3) In LT mode the C4b and OSC2 clocks must be externally frequency locked (i.e., fOSC2 = 2.5 x fC4b ). The relative phase between the clocks is not critical. Characteristics Sym Min Typ ‡ Max Units Test Conditions O U T P U T S VBias Voltage V Bias 0.5AVDD V Relative to AVSS C L=1 µF minimum to AVSS 9V Ref Voltage V Ref -1.9 V Relative to V Bias C L= 1µF minimum to AVSS
10 V Bias and/or VRef load V BL 1M Ω (see Note 2)
11 Output High Voltage (1) VOH 2.4 V I OH =10mA 12 Output Low Voltage (1) VOL 0.4 V I OL = 5.0mA 13 OSC2 Output High Voltage V OH 3.5 V I OH =10µA 14 OSC2 Output Low Voltage V OL 1.5 V I OL =10µA
15 Differential Output Voltage
(Lout+ to Lout-)V out 6.4 V pp R L=40Ω
16 Output Impedance
(Lout+, Lout-)Z out 0.5 Ω Measured by sourcing and sinking 10 mA. Line Driver active.
17 Output Capacitance
out+, Lout-)C o 50 pF (see Note 1)
18 High Impedance Leakage I OZ 10 µA
19 Supply Current I DD
unloaded. Low Power Mode Characteristics Sym Min Typ ‡ Max Units Test Conditions 1 OSC2 Clock Frequency 1/t MCF 10.24 MHz (see Notes 1, 2 & 3)
2 OSC2 Clock Duty Cycle t OCH /
45 50 55 %
3 OSC2 Clock Transition Time t OCT 10 ns
4C 4 b Jitter (wrt OSC2) t JC -15 +15 ns (see Note 3) C4b OSC2 VIH VIL VIH VIL tJC tJC tOCH tOCT tOCT (See Note 3)tMCF
MT8910-1 Preliminary Information 9-26 Figure 16 - ST-BUS Timing LT Mode † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Note 1) These timing parameters are mode independent (NT or LT). 2) T ested @ 5V , 25°C only. Characteristics Sym Min Typ ‡ Max Units Test Conditions 1F 0 b Input Pulse Width t FPW 244 ns
2 Frame Pulse (F0b ) Setup Time t FPS 50 ns (see Note 2)
3 Frame Pulse (F0b ) Hold Time t FPH 50 ns (see Note 2)
4C 4 b Input Clock Period t P4i 244 ns 5C 4 b Pulse Width High or Low t C4W 122 ns
6 Superframe Setup Time t SFS 50 ns (see Note 2)
7 Superframe Hold Time t SFH 50 ns (see Note 2)
8F 0 o d Delay t DFD 60 ns 150 pF Load (see Notes 1 & 2) 9F 0 o d Pulse Width t DFW 244 ns 150 pF Load (see Note 1)
10 Serial Input Setup Time t SIS 30 ns (see Notes 1 & 2)
11 Serial Input Hold Time t SIH 50 ns (see Notes 1 & 2)
12 Serial Output Delay Act to Act
t DAA tDZA tDAZ 120 120 120 ns 150 pF Load (see Notes 1 & 2) 150 pF Load (see Notes 1 & 2) 150 pF Load (see Notes 1 & 2) VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VOH VOL F0b C4b SFb F0od DSTi/ CDSTi DSTo/ CDSTo tFPS tFPW tFPH tP4i tC4W tSFS tSFH tC4W tDFD tDFD tSIS tSIH tDZA tDAA tDAZ tDFW BIT 0, CHANNEL 31 BIT 7, CHANNEL 0
Preliminary Information MT8910-1 9-27 Figure 17 - ST-BUS Timing NT Mode † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Notes 1) The C4b pulse width low will vary by ±48ns during a phase-correction cycle. 2) These timing parameters are mode independent (NT or LT). 3) Tested at 5.0V, 25°C only. Characteristics Sym Min Typ ‡ Max Units Test Conditions 1F 0 b Output Pulse Width t FPW 1 cycles C L=150 pF, C4b cycles 2F 0 b Output Delay t CFD 60 ns 150 pF (see Note 3) 3C 4 b Output Clock Period t P4o 244 ns 150 pF 4C 4 b Pulse Width High t C4H 88 ns 150 pF 5C 4 b Pulse Width Low t C4L 137 ns 150 pF (see Note 1) 6C 4 b Transition Time t C4T 15 ns 150 pF 7S F b Output Delay t SFD 60 ns C L=150 pF (see Note 3) 8S F b Output Pulse Width t SFW 1 cycles C L=150 pF, C4b cycles 9F 0 o d Delay t DFD 60 ns C L=150 pF (see Notes 2 & 3)
10 F0od Pulse Width t DFW 1 cycles C L=150 pF, C4b cycles (see
Note 2)
11 Serial Input Setup Time t SIS 30 ns C L=150 pF (see Note 2)
12 Serial Input Hold Time t SIH 50 ns C L=150 pF (see Note 2)
13 Serial Output Delay Act to Act
150 pF load (see Notes 2 & 3) 150 pF load (see Notes 2 & 3) 150 pF load (see Notes 2 & 3) VOH VOL VOH VOL VOH VOL VOH VOL VIH VIL VOH VOL F0b C4b SFb F0od DSTi/ CDSTi DSTo/ CDSTo BIT 0, CHANNEL 31 BIT 7, CHANNEL 0 tFPW tCFD tCFD tC4H tSFD tC4L tC4T tDFD tDFD tSIS tSIH tDZA tDAA tDAZ tP4o tSFW tDFW
MT8910-1 Preliminary Information 9-28 NOTES: