MT88L70

MT88L70 ZARLINK | Alldatasheet

Document overview

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Technical content

Features

• 2.7 - 3.6 volt operation
• Complete DTMF receiver
• Low power consumption
• Internal gain setting amplifier
• Adjustable guard time
• Central office quality
• Power-down mode
• Inhibit mode
• Functionally compatible with Zarlink’s MT8870D

Applications

• Paging systems
• Repeater systems/mobile radio
• Credit card systems
• Remote control
• Personal computers
• Telephone answering machine

Description

The MT88L70 is a complete 3 Volt, DTMF receiver integrating both the bandsplit filter and digital decoder functions. The filter section uses switched capacitor techniques for high and low group filters; the decoder uses digital counting techniques to detect and decode all 16 DTMF tone-pairs into a 4-bit code. External component count is minimized by on chip provision of a differential input amplifier, clock oscillator and latched three-state bus interface. August 2005

Ordering Information

MT88L70AE 18 Pin PDIP Tubes MT88L70AS 18 Pin SOIC Tubes MT88L70AN 20 Pin SSOP Tubes MT88L70ASR 18 Pin SOIC Tape & Reel MT88L70ANR 20 Pin SSOP Tape & Reel MT88L70AE1 18 Pin PDIP* Tubes MT88L70AN1 20 Pin SSOP* Tubes MT88L70ANR1 20 Pin SSOP* Tape & Reel MT88L70AS1 18 Pin SOIC* Tubes MT88L70ASR1 18 Pin SOIC* Tape & Reel * Pb Free Matte Tin -40°C to +85 °C MT88L70

3 Volt Integrated DTMF Receiver

Figure 1 - Functional Block Diagram PWDN IN + IN - GS OSC1 OSC2 St/GT ESt STD TOE VDD VSS VRef INH Bias Circuit Dial Tone Filter High Group Filter Low Group Filter Digital Detection Algorithm Code Converter and Latch St GT Steering Logic Chip Power Chip Bias VRef Buffer Zero Crossing Detectors to all Chip Clocks

Zarlink Semiconductor Inc. Figure 2 - Pin Connections Pin Description Pin # Name Description 18 20 11 I N + Non-Inverting Op-Amp (Input). 22 I N - Inverting Op-Amp (Input). 33 G S Gain Select. Gives access to output of front end differential amplifier for connection of feedback resistor. 44 V Ref Reference Voltage (Output). Nominally VDD/2 is used to bias inputs at mid-rail (see Figure 5 and Figure 6). 55 I N H Inhibit (Input). Logic high inhibits the detection of tones representing characters A, B, C and D. This pin input is internally pulled down. 6 6 PWDN Power Down (Input). Active high. Powers down the device and inhibits the oscillator. This pin input is internally pulled down. 78O S C 1 Clock (Input). 89O S C 2 Clock (Output). A 3.579545 MHz crystal connected between pins OSC1 and OSC2 completes the internal oscillator circuit. 91 0 V SS Ground (Input). 0 V typical. 10 11 TOE Three State Output Enable (Input). Logic high enables the outputs Q1-Q4. This pin is pulled up internally. 11- 12- Q1-Q4 Three State Data (Output). When enabled by TOE, provide the code corresponding to the last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high impedance. 15 17 StD Delayed Steering (Output).Presents a logic high when a received tone-pair has been registered and the output latch updated; returns to logic low when the voltage on St/GT falls below V TSt. 16 18 ESt Early Steering (Output). Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low. 9 10 IN+ IN- GS VRef INH PWDN OSC1 OSC2 VSS VDD St/GT ESt StD TOE

18 PIN PDIP/SOIC

20 PIN SSOP

Zarlink Semiconductor Inc. Functional Description The MT88L70 monolithic DTMF receiver offers small size , low power consumption and high performance, with 3 volt operation. Its architecture consists of a bandsplit filter section, which separates the high and low group tones, followed by a digital counting section which verifies the frequency and duration of the received tones before passing the corresponding code to the output bus. Filter Section Separation of the low-group and high group tones is achiev ed by applying the DTMF signal to the inputs of two sixth-order switched capacitor bandpa ss filters, the bandwidths of which correspond to the low and high group frequencies. The filter section also incorporates notches at 350 and 440 Hz for exceptional dial tone rejection. Each filter output is followed by a single order switched capacitor filter section which smooths the signals prior to limiting. Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the incoming DTMF signals. Decoder Section Following the filter section is a decoder employing digita l counting techniques to determine the frequencies of the incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm protects against tone simulation by extraneous signals su ch as voice while providing tolerance to small frequency deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the detector recognizes the presence of two valid tones (this is referred to as the “signal condition” in some industry specifications) the “Early Steering” (ESt) output will go to an active state. Any subs equent loss of signal condition will cause ESt to assume an inactive state (see “Steering Circuit”). Steering Circuit Before registration of a decoded tone pair, the receiver che cks for a valid signal duration (referred to as character recognition condition). This check is performed by an extern al RC time constant driven by ESt. A logic high on ESt causes vc (see Figure 3) to rise as the capacitor discharges . Provided signal condition is maintained (ESt remains high) for the validation period (t GTP), vc reaches the threshold (V TSt) of the steering logic to register the tone pair, latching its corresponding 4-bit code (see Table 1) into the output latch. At this point the GT output is activated and drives vc to VDD. GT continues to drive high as long as ESt remains high. Finally, after a short delay to allow the output latch to settle, the delayed steering output flag (StD) goes high, signalling that a received tone pair has been registered. The contents of t he output latch are made available on the 4-bi t output bus by raising the three state control input (TOE) to a logic high. The st eering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (dropout) too short to be considered a valid pause. This facility, together with the capability of selecting 17 19 St/GT Steering Input/Guard time (Output) Bidirectional. A voltage greater than VTSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St. 18 20 V DD Positive power supply (Input). +3 V typical. 7, 16 NC No Connection. Pin Description Pin # Name Description 18 20

Zarlink Semiconductor Inc. the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements. Table 1 - Functional Decode Table L=LOGIC LOW, H=LOGIC HIGH, Z=HIGH IMPEDANCE X = DON‘T CARE Guard Time Adjustment In many situations not requiring select ion of tone duration and interdigital pa use, the simple steering circuit shown in Figure 3 is applicable. Component values are chosen according to the formula: tREC=tDP+tGTP tID=tDA+tGTA The value of tDP is a device parameter (see Figure 7) and t REC is the minimum signal duration to be recognized by the receiver. A value for C of 0.1 µF is recommended for most application s, leaving R to be selected by the designer. Digit TOE INH ESt Q 4 Q3 Q2 Q1 A N Y LXHZZZZ

1 HX H0001

2 HX H0010

3 HX H0011

4 HX H0100

5 HX H0101

6 HX H0110

7 HX H0111

8 HX H1000

9 HX H1001

0 HX H1010

• HX H1011 # HX H1100 A HLH1101 B HLH1110 C HLH1111 D HLH0000 AH H L undetected, the output code will remain the same as the previous detected code BH H L CH H L DH H L

Zarlink Semiconductor Inc. A single-ended input configuration is show n in Figure 6. For applications with differential signal inputs the circuit shown in Figure 5 may be used. Figure 6 - Single-Ended Input Configuration IN+ IN- GS V Ref INH PDWN OSC1 OSC2 V SS VDD St/GT ESt StD TOE DTMF Input C VDD X-tal MT88L70 NOTES: R1, R2 = 100 kΩ ±1% R3 = 300 kΩ ±1% C1,C2 = 100 nF ±5% X-tal = 3.579545 MHz ±0.1%

Zarlink Semiconductor Inc. † Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Derate above 75 °C at 16 mW / °C. All leads soldered to board. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. Absolute Maximum Ratings† Parameter Symbol Min. Max. Units

1 DC Power Supply Voltage V DD 7V

2 Voltage on any pin V I VSS-0.3 V DD+0.3 V

3 Current at any pin (other than supply) I I 10 mA

4 Storage temperature T STG -65 +150 °C

5 Package power dissipation P D 500 mW

Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated. Parameter Sym. Min. Typ. ‡ Max. Units Test Conditions 1 DC Power Supply Voltage V DD 2.7 3.0 3.6 V

2 Operating Temperature T O -40 +85 °C

3 Crystal/Clock Frequency fc 3.579545 MHz 4 Crystal/Clock Freq.Tolerance ∆fc ±0.1 % VDD = 3.0 V+ 20%/-10%, VSS = 0 V, -40°C ≤ TO ≤ +85°C, unless otherwise stated. Characteristics Sym. Min. Typ. ‡ Max. Units Test Conditions 1 S U P P L Y Standby supply current I DDQ 11 0 µA PWDN=V DD 2 Operating supply current I DD 2.0 5.5 mA 3 Power consumption P O 6m W f c=3.579545 MHz I N P U T S High level input V IH 2.1 V V DD = 3.0 V 5 Low level input voltage V IL 0.9 V V DD = 3.0 V 6 Input leakage current I IH/IIL 0.05 5 µAV IN = VSS or VDD

7 Pull up (source) current I SO 41 5 µA TOE (pin 10) = 0,

VDD = 3.0 V

8 Pull down (sink) current I SI 15 40 µA INH = V DD, PWDN =

VDD, VDD = 3.0 V

9 Input impedance (IN+, IN-) R IN 10 M Ω @ 1 kHz

10 Steering threshold voltage V TSt 0.465VDD V

Zarlink Semiconductor Inc. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. O U T P U T S Low level output voltage V OL VSS+0.03 V No load 12 High level output voltage V OH VDD-0.03 V No load 13 Output low (sink) current I OL 1.5 8 mA V OUT = 0.4 V

14 Output high (source)

IOH 1.0 3.0 mA V OUT = 3.6 V, VDD = 3.6 V 15 V Ref output voltage V Ref 0.512VDD V No load

16 V Ref output resistance R OR 1k Ω

Operating Characteristics - VDD = 3.0 V+20%/-10%, VSS = 0 V, -40°C ≤ TO ≤ +85°C, unless otherwise stated. Gain Setting Amplifier Characteristics Sym. Min. Typ. ‡ Max. Units Test Conditions

1 Input leakage current I IN 100 nA V SS ≤ VIN ≤ VDD

2 Input resistance R IN 10 M Ω

3 Input offset voltage V OS 25 mV

4 Power supply rejection PSRR 50 dB 1 kHz

5 Common mode rejection CMRR 40 dB V

SS + 0.75 V ≤ VIN ≤ VDD-0.75 biased at VRef =1.5 V

6 DC open loop voltage gain A VOL 32 dB

7 Unity gain bandwidth f C 0.30 MHz 8 Output voltage swing V O 2.2 V pp Load ≥ 100 kΩ to VSS @ GS

9 Maximum capacitive load (GS) C L 100 pF

10 Resistive load (GS) R L 50 k Ω

11 Common mode range V CM 1.5 V pp No Load Characteristics Sym. Min. Typ. ‡ Max. Units Test Conditions

Zarlink Semiconductor Inc. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. *NOTES 1. dBm= decibels above or below a reference power of 1 mW into a 600 ohm load. 2. Digit sequence consists of all DTMF tones. 3. Tone duration= 40 ms, tone pause= 40 ms. 4. Signal condition consists of nominal DTMF frequencies. 5. Both tones in composite signal have an equal amplitude. 6. Tone pair is deviated by ±1.5%± 2H z . 7. Bandwidth limited (3 kHz) Gaussian noise. 8. The precise dial tone frequencies are (350 Hz and 440 Hz) ± 2%. 9. For an error rate of better than 1 in 10,000. 10. Referenced to lowest level frequency component in DTMF signal. 11. Referenced to the minimum valid accept level. 12. Guaranteed by design and characterization. Characteristics Sym Min. Typ ‡ Max Units Notes*

1 Valid input signal levels

(each tone of composite signal) -34 15.4 -4.0 489 dBm mVRMS 1,2,3,5,6,9 Min @ V DD=3.6 V Max @ VDD=2.7 V

2 Negative twist accept 8 dB 2,3,6,9,12

3 Positive twist accept 8 dB 2,3,6,9,12

4 Frequency deviation accept ±1.5% ± 2 Hz 2,3,5,9 5 Frequency deviation reject ±3.5% 2,3,5,9

6 Third zone tolerance -16 dB 2,3,4,5,9,10

7 Noise tolerance -12 dB 2,3,4,5,7,9,10

8 Dial zone tolerance +22 dB 2,3,4,5,8,9,11

Zarlink Semiconductor Inc. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. *NOTES: 1. Used for guard-time calculation purposes only and tested at -4 dBm. 2. These, user adjustable parameters, are not device specifications. The adjustable settings of these minimums and maximums are recommendations based upon network requirements. 3. With valid tone present at input, t PU equals time from PDWN goin g low until ESt going high. Characteristics Sym. Min. Typ. ‡ Max. Units Conditions T I M I N G Tone present detect time t DP 51 1 1 4 m s N o t e 1 2 Tone absent detect time t DA 0 . 548 . 5 m s N o t e 1

3 Tone duration accept t REC 40 ms Note 2

4 Tone duration reject t REC 20 ms Note 2

5 Interdigit pause accept t ID 40 ms Note 2

6 Interdigit pause reject t DO 20 ms Note 2

O U T P U T S Propagation delay (St to Q) t PQ 11 µsT O E = V DD

8 Propagation delay (St to StD) t PStD 20 µs TOE=VDD

9 Output data set up (Q to StD) t QStD 5.0 µs TOE=VDD

10 Propagation delay (TOE to Q ENABLE) t PTE 50 ns load of 10 k Ω,

11 Propagation delay (TOE to Q DISABLE) t PTD 130 ns load of 10 k Ω,

D W N Power-up time t PU 30 ms Note 3

13 Power-down time t PD 20 ms

C L O C K Crystal/clock frequency f C 3.5759 3.5795 3.5831 MHz 15 Clock input rise time t LHCL 110 ns Ext. clock 16 Clock input fall time t HLCL 110 ns Ext. clock 17 Clock input duty cycle DC CL 40 50 60 % Ext. clock

18 Capacitive load (OSC2) C LO 15 pF

Zarlink Semiconductor Inc. Figure 7 - Timing Diagram EXPLANATION OF EVENTS A) TONE BURSTS DETECTED, TONE DURATION INVALID, OUTPUTS NOT UPDATED. B) TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS. C) END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMAIN LATCHED UNTIL NEXT VALID TONE. D) OUTPUTS SWITCHED TO HIGH IMPEDANCE STATE. E) TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS (CURRENTLY HIGH IMPEDANCE). F) ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSEN T DURATION INVALID, OUTPUTS REMAIN LATCHED. G) END OF TONE #n+1 DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMAIN LATCHED UNTIL NEXT VALID TONE. EXPLANATION OF SYMBOLS V in DTMF COMPOSITE INPUT SIGNAL. ESt EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES. St/GT STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT. Q1-Q4 4-BIT DECODED TONE OUTPUT. StD DELAYED STEERING OUTPUT. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. TOE TONE OUTPUT ENABLE (INPUT). A LOW LEVEL SHIFTS Q 1-Q4 TO ITS HIGH IMPEDANCE STATE. tREC MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID. tREC MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION. tID MINIMUM TIME BETWEEN VALID DTMF SIGNALS. tDO MAXIMUM ALLOWABLE DROP OUT DURING VALID DTMF SIGNAL. tDP TIME TO DETECT THE PRESENCE OF VALID DTMF SIGNALS. tDA TIME TO DETECT THE ABSENCE OF VALID DTMF SIGNALS. tGTP GUARD TIME, TONE PRESENT. tGTA GUARD TIME, TONE ABSENT. Vin ESt St/GT Q1-Q4 StD TOE EVENTS AB C D EF G tREC tREC tID tDO TONE #n TONE #n + 1 TONE #n + 1 tDP tDA tGTP tGTA tPQ tQStD tPSrD tPTD tPTE # n # (n + 1) HIGH IMPEDANCE DECODED TONE # (n-1) VTSt

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