MT88E41

MT88E41 ZARLINK | Alldatasheet

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SEMICMF.019 1 MT88E41 ExtendedVoltageCallingNumber IdentificationCircuit (ECNIC) Data Sheet

Features

• 1200 baud BELL 202 and CCITT V.23 Frequency Shift Keying (FSK) demodulation
• Compatible with Bellcore GR-30-CORE and SR- TSV-002476
• High input sensitivity: -36dBm minimum FSK Detection Level
• Simple serial 3-wire data interface eliminating the need for a UART
• Power down mode
• Internal gain adjustable amplifier
• Carrier detect status output
• Uses 3.579545 MHz crystal
• 2.7 - 5.5V operation
• Low power CMOS technology

Applications

• Calling Number Delivery (CND), Calling Name Delivery (CNAM) and Calling Identity on Call Waiting (CIDCW) features of Bellcore CLASS SM service
• Feature phones
• Phone sets, adjunct boxes
• FAX machines
• Telephone answering machines
• Database query systems
• Battery powered applications

Description

The MT88E41 Extended Voltage Calling Number Identification Circuit (ECNIC) is a CMOS integrated circuit providing an interface to various calling line information delivery services that utilize 1200 baud BELL 202 or CCITT V.23 FSK voiceband data transmission schemes. The ECNIC receives and demodulates the signal and outputs data into a simple 3-wire serial interface. Typically, the FSK modulated data containing information on the calling line is sent before alerting the called party or during the silent interval between the first and second ring using either CCITT V.23 recommendations or Bell 202 specifications. The ECNIC accepts and demodulates both CCITT V.23 and BELL 202 signals. Along with serial data and clock, the ECNIC provides a data ready signal to indicate the reception of every 8-bit character sent from the Central DS5717 Issue 3 February 1998

Ordering Information

MT88E41AE 16 Pin Plastic DIP MT88E41AS 16 Pin SOIC MT88E41AN 20 Pin SSOP -40 °C to +85 °C Figure 1 - Functional Block Diagram CLASSSM is a service mark of Bellcore GS IN- IN+ CAP VRef DATA DR DCLK CD PWDN OSC1 OSC2 VSS VDD IC1 IC2 Receive Bandpass Filter Bias Generator FSK Demodulator Data and Timing Carrier Detector Clock Generator Recovery to other circuits CMOS

SEMICMF.0192 Office. The received data can be processed externally by a microcontroller, stored in memory, or displayed as is, depending on the application. Figure 2 - Pin Connections Pin Description Table Pin # Name Description 16 20 1 1 IN+ Non-inverting Op-Amp (Input). 2 2 IN- Inverting Op-Amp (Input). 3 3 GS Gain Select (Output). Gives access to op-amp output for connection of feedback resistor. 4 4 VRef Voltage Reference (Output). Nominally VDD/2. This is used to bias the op-amp inputs. 5 5 CAP Capacitor. Connect a 0.1µF capacitor to VSS. 6 7 OSC1 Oscillator (Input). Crystal connection. This pin can be driven directly from an external clocking source. 7 9 OSC2 Oscillator (Output). Crystal connection. When OSC1 is driven by an external clock, this pin should be left open. 8 10 VSS Power supply ground. 9 11 DCLK Data Clock (Output). Outputs a clock burst of 8 low going pulses at 1202.8Hz (3.5795MHz divided by 2976). Every clock burst is initiated by the DATA stop bit start bit sequence. When the input DATA is 1202.8 baud, the positive edge of each DCLK pulse coincides with the middle of the data bits output at the DATA pin. No DCLK pulses are generated during the start or stop bits. Typically, DCLK is used to clock the eight data bits from the 10 bit data word into a serial-to-parallel converter. 10 12 DATA Data (Output). Serial data output corresponding to the FSK input and switching at the input baud rate. Mark frequency at the input corresponds to a logic high, while space frequency corresponds to a logic low at the DATA output. With no FSK input, DATA is at logic high. This output stays high until CD has become active. 11 13 DR Data Ready (Open Drain Output). This output goes low after the last DCLK pulse of each word. This can be used to identify the data (8-bit word) boundary on the serial output stream. Typically, DR is used to latch the eight data bits from the serial-to-parallel converter into a microcontroller. 12 14 CD Carrier Detect (Open Drain Output). A logic low indicates that a carrier has been present for a specified time on the line. A time hysteresis is provided to allow for momentary discontinuity of carrier. IN+ IN- GS VRef CAP OSC1 OSC2 VSS VDD IC2 IC1 PWDN CD DR DATA DCLK

16 PIN PLASTIC DIP/SOIC

20 PIN SSOP

3SEMICMF.019 13 15 PWDN Power Down (Input). Active high, Schmitt Trigger input. Powers down the device including the input op-amp and the oscillator. 14 16 IC1 Internal Connection 1. Connect to VSS. 15 19 IC2 Internal Connection 2. Internally connected, leave open circuit. 16 20 VDD Positive power supply voltage. 6, 8, 17, 18 NC No Connection. Pin Description Table (continued) Pin # Name Description 16 20

SEMICMF.0194

1.0 Functional Description

The MT88E41 Extended Voltage Calling Number Identification Circuit (ECNIC) is a device compatible with the Bellcore proposal (GR-30-CORE) on generic requirements for transmitting asynchronous voiceband data to Customer Premises Equipment (CPE) from a serving Stored Program Controlled Switching System (SPCS) or a Central Office (CO). This data transmission technique is applicable in a variety of services like Calling Number Delivery (CND), Calling Name Delivery (CNAM) or Calling Identity Delivery on Call Waiting (CIDCW) as specified in Custom Local Area Signalling Service (CLASSSM) calling information delivery features by Bellcore. With CND, CNAM and CIDCW service, the called subscriber has the capability to display or to store the information on the calling party which is sent by the CO and received by the ECNIC. In the CND service, information about a calling party is embedded in the silent interval between the first and second ring. During this period, the ECNIC receives and demodulates the 1200 baud FSK signal (compatible with Bell-202 specification) and outputs data into a 3-wire serial interface. In the CIDCW service, information about a second calling party is sent to the subscriber, (while the subscriber is engaged in another call). During this period, the ECNIC receives and demodulates the FSK signal as in the CND case. The ECNIC is designed to provide the data transmission interface required for the above service at the called subscriber location either in the on-hook case as in CND, or the off-hook case, as in CIDCW. The functional block diagram of the ECNIC is shown in Figure 1. Note however, for CIDCW applications, a separate CAS (CPE Alerting Signal) detector is required. Figure 3 - Differential Input Configuration C1 R1 C2 R4 R3 R2 IN+ IN- GS VRef MT88E41DIFFERENTIAL INPUT AMPLIFIER C1 = C2 = 10 nF R1 = R4 = R5 = 100 kΩ R2 = 60kΩ , R3 = 37.5 kΩ VOLTAGE GAIN (AVdiff) = R5/R1 INPUT IMPEDANCE (ZINdiff) = 2 R12 + (1/ω C)2

5SEMICMF.019 Figure 4 - Single-Ended Input Configuration In Europe, Caller ID and CIDCW services are being proposed. These schemes may be different from their North American counterparts. In most cases, 1200 baud CCITT V.23 FSK is used instead of Bell 202. Because the ECNIC can also demodulate 1200 baud CCITT V.23 with the same performance, it is suitable for these applications. Although the main application of the ECNIC is to support CND and CIDCW service, it may also be used in any application where 1200 baud Bell 202 and/or CCITT V.23 FSK data reception is required.

1.1 Input Configuration

The input arrangement of the MT88E41 provides an operational amplifier, as well as a bias source (VRef) which is used to bias the inputs at VDD/2. Provision is made for connection of a feedback resistor to the op-amp output (GS) for adjustment of gain. In a single-ended configuration, the input pins are connected as shown in Figure 4. Figure 3 shows the necessary connections for a differential input configuration.

1.2 User Interface

The ECNIC provides a powerful 3-pin interface which can reduce the external hardware and software requirements. The ECNIC receives the FSK signal, demodulates it, and outputs the extracted data to the DATA pin. For each received stop bit start bit sequence, the ECNIC outputs a fixed frequency clock string of 8 pulses at the DCLK pin. Each clock rising edge corresponds to the centre of each DATA bit cell (providing the incoming baud rate matches the DCLK rate). DCLK is not generated for the stop and start bits. Consequently, DCLK will clock only valid data into a peripheral device such as a serial to parallel shift register or a micro-controller. The ECNIC also outputs an end of word pulse (data ready) at the DR pin. The data ready signal indicates the reception of every 10-bit word sent from the Central Office. This output is typically used to interrupt a micro-controller. The three outputs together, eliminate the need for a UART (Universal Asynchronous Receiver Transmitter) or the high software overhead of performing the UART function (asynchronous serial data reception). Note that the 3-pin interface may also output data generated by voice since these frequencies are in the input frequency detection band of the device. The user may choose to ignore these outputs when FSK data is not expected, or force the ECNIC into its powerdown mode.

1.3 Power Down Mode

For applications requiring reduced power consumption, the ECNIC can be forced into power down when it is not needed to receive FSK data. This is done by pulling the PWDN pin high. In powerdown mode, the crystal oscillator, op-amp and internal circuitry are all disabled and the ECNIC will not react to the input signal. DATA and DCLK are at logic high, and DR and CD are at high impedance or at logic high when pulled up with resistors.The ECNIC can be awakened for reception of the FSK signal by pulling the PWDN pin to ground (see Figure 9). C RIN IN+ IN- GS VRef MT88E41 VOLTAGE GAIN (AV) = RF / RIN RF

SEMICMF.0196

1.4 Carrier Detect

The presence of the FSK signal is indicated by a logic low at the carrier detect (CD) output. This output has built in hysteresis to prevent toggling when the received signal is shortly interrupted. Note that the CD output is also activated by voice since these frequencies are in the input frequency detection band of the device. The user may choose to ignore this output when FSK data is not expected, or force the ECNIC into its powerdown mode. Figure 5 - Common Crystal Connection

1.5 Crystal Oscillator

The ECNIC uses a crystal oscillator as the master timing source for filters and the FSK demodulator. The crystal specification is as follows: Frequency: 3.579545 MHz Frequency tolerance: ±0.1%(-40°C+85°C) Resonance mode: Parallel Load capacitance: 18 pF Maximum series resistance: 150 ohms Maximum drive level (mW): 2 mW e.g. CTS MP036S A number of MT88E41 devices can be connected as shown in Figure 5 such that only one crystal is required. The Alternatively, the OSC1 inputs on all devices can be driven from a CMOS buffer (dc coupled) with the OSC2 outputs left unconnected.

1.6 VRef and CAP Inputs

VRef is the output of a low impedance voltage source equal to V DD/2 and is used to bias the input op-amp. A 0.1 µF capacitor is required between CAP and VSS to suppress noise on VRef. OSC1OSC2 OSC1OSC2 OSC1OSC2

3.579545 MHz

7SEMICMF.019

2.0 Applications

The circuit shown in Figure 6 illustrates the use of the MT88E41 device in a typical FSK receiver system. Bellcore Special Report SR-TSV-002476 specifies that the FSK receiver should be able to receive FSK signal levels as follows: Received Signal Level at 1200Hz: -32dBm to -12dBm Received Signal Level at 2200Hz: -36dBm to -12dBm This condition can be attained by choosing suitable values of R1 and R2. The MT88E41 configured in a unity gain mode as shown in Fig. 6 meets the above level requirements. For applications requiring detection of lower FSK signal level, the input op amp may be configured to provide adequate gain. Figure 6 - Application Circuit (Single-Ended Input) VDD C2 X-tal MT88E41 IN + IN - GS VRef CAP OSC1 OSC2 VSS VDD IC2 IC1 PWDN CD DR DATA DCLK R3 R4 To Controller Notes: R1, R2 = 100 kΩ 1% R3, R4 = 100 kΩ 10% C1, C2, C3 = 0.1µF 20% X-tal = 3.579545 MHz

SEMICMF.0198 *Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. † DC Electrical Characteristics are over recommended operating conditions unless otherwise stated. * Typical figures are at 25°C and are for design aid only. Absolute Maximum Ratings* - Voltages are with respect to VSS unless otherwise stated. Parameter Symbol Min Max Units 1 DC Power Supply Voltage VDD to VSS VDD -0.3 6 V 2 Voltage on any pin VP -0.3 VDD+0.3 V

3 Current at any pin (except VDD and VSS) I I/O ±10 mA

4 Storage Temperature TST -65 +150 °C

5 Package Power Dissipation PD 500 mW

Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated Characteristics Sym Min Typ Max Units Test Conditions 1 DC Power Supply Voltage VDD 2.7 5.5 V 2 Clock Frequency fOSC 3.579545 MHz 3 Tolerance on Clock Frequency Δ fc ±0.1 %

4 Operating Temperature -40 +85 °C

Characteristics Sym Min Typ* Max Units Test Conditions 1 S U P P L Y Standby Supply Current VDD=2.7V VDD=5.5V IDDQ µA µA PWDN=VDD

2 Operating Supply Current

VDD=2.7V VDD=5.5V IDD mA mA PWDN=VSS

3 DATA

VOH VDD-0.4 0.4 V V IOL=2.5mA IOH=0.8mA 4 DR CD Sink Current IOL 2.5 mA VOL=0.4V PWDN Schmitt Input High Threshold Schmitt Input Low Threshold VT+ VT- 0.48*VDD 0.28*VDD 0.68*VDD 0.48*VDD V V 6 Schmitt Hysterisis VHYS 0.2 V

7 Input Current IIN 10 µA VSS ≤ VIN ≤ VDD

Output Voltage VRef 0.5VDD - 0.05 0.5VDD + 0.05 V No Load

9 Output Resistance RRef 2 kΩ

9SEMICMF.019 † Electrical characteristics are over recommended operating conditions, unless otherwise stated. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. † AC Electrical Characteristics are over recommended operating conditions, unless otherwise stated. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Electrical Characteristics† - Gain Setting Amplifier Characteristics Sym Min Typ‡ Max Units Test Conditions

1 Input Leakage Current IIN 1 µA VSS ≤ VIN ≤ VDD

2 Input Resistance Rin 5 MΩ

3 Input Offset Voltage VOS 25 mV

4 Power Supply Rejection Ratio PSRR 30 40 dB 1kHz ripple on VDD

5 Common Mode Rejection CMRR 30 40 dB VCMmin ≤ VIN ≤ VCMmax

6 DC Open Loop Voltage Gain AVOL 30 32 dB

7 Unity Gain Bandwidth fC .2 0.3 MHz 8 Output Voltage Swing VO 0.5 VDD-0.5 Vpp Load ≥ 50kΩ

9 Maximum Capacitive Load (GS) CL 100 pF

10 Maximum Resistive Load (GS) RL 50 kΩ

11 Common Mode Range Voltage VCM 1.0 VDD-1.0 V Characteristics Sym Min Typ‡ Max Units Notes*

1 Input Detection Level -36

12.3 275 dBm mV 1, 2, 3 1, 2, 3

2 Input Baud Rate 1188 1200 1212 baud 7

3 Input Frequency Detection

Bell 202 1 (Mark) Bell 202 0 (Space) CCITT V.23 1 (Mark) CCITT V.23 0 (Space) 1188 2178 1280.5 2068.5 1200 2200 1300 2100 1212 2222 1319.5 2131.5 Hz Hz Hz Hz

4 Input Noise Tolerance 20 log( SNR 20 dB 2, 3, 4, 5

SEMICMF.01910 † AC Electrical Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C and are for design aid only, not guaranteed and not subject to production testing. *Notes: 1. dBm=decibels above or below a reference power of 1mW into 600 Ω . 2. Using unity gain test circuit shown in Figure 6. 3. Mark and Space frequencies have the same amplitude. 4. Band limited random noise (200-3200Hz). 5. Referenced to the minimum input detection level. 6. FSK input data at 1200 ±12 baud. 7. OSC1 at 3.579545 MHz ±0.2%. 8. 10k to V SS, 50pF to V SS.9. 10k to V DD, 50pF to V SS. 10. Function of signal condition. 11. The device will stop functioning within this time, but more time may be required to reach I DDQ. 12. For a repeating mark space sequence, the data stream will typically have equal 1 and 0 bit durations. Characteristics Sym Min Typ‡ Max Units Notes*

1 PWDN

Power-up time tPU 35 50 ms

2 Power-down time tPD 100 1000 µs 11

Input FSK to CD low delay tIAL 25 ms

4 Input FSK to CD high delay tIAH 8 ms

5 Hysteresis 8 ms

6 DATA Rate 1188 1200 1212 bps 6,12

7 Input FSK to DATA delay tIDD 1 5 ms

9 Fall time tF 200 ns 8

10 DATA to DCLK delay tDCD 6 416 µs 6, 7, 10

11 DCLK to DATA delay tCDD 6 416 µs 6, 7, 10

Frequency 1200 1202.8 1205 Hz 7

13 High time tCH 415 416 417 µs 7

14 Low time tCL 415 416 417 µs 7

15 DCLK

DCLK to DR delay tCRD 415 416 417 µs 7 DR Rise time tRR 10 µs 9

17 Fall time tFF 200 ns 9

18 Low time tRL 415 416 417 µs 7

SEMICMF.01912 Figure 9 - Input and Output Timing (Bellcore CND Service) First Ringing Input FSK Data Second Ringing 2 sec channel seizure Mark state checksum TIP/RING PWDN OSC2 CD * DATA DCLK DR * High (Input Idle) * with external pull-up resistor tPU 500ms (min) tIAL 200ms (min) tPD tIAH High (Input Idle)

13SEMICMF.019 Figure 10 - Serial Data Interface Timing TIP/RING DATA DCLK DR * stop start stop start stop start stop start b0 b1 b2 b3 b4 b5 b6 b7b7 1 0 b0 b1 b2 b3 b4 b5 b6 b71 0 b0 b1 b21 0 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 stop start stop start tIDD tCRD * with external pull-up resistor

SEMICMF.01914

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