MT88E39

MT88E39 ZARLINK | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 16

Technical content

Features

• 1200 baud Bell 202 and CCITT V.23 Frequency Shift Keying (FSK) demodulation
• Compatible with Bellcore GR-30-CORE, SR-TSV- 002476, TIA/EIA-716 and ETSI 300 778-1
• High input sensitivity
• Dual mode 3-wire data interface (Serial FSK data stream or MT88E43 compatible 1 byte buffer)
• Internal gain adjustable amplifier
• Carrier detect status output
• Uses 3.579545 MHz crystal or ceramic resonator
• 3 to 5 V ±10% supply voltage
• Low power CMOS with power down mode
• Direct pin to pin replacement of MT8841 and MT88E41

Applications

• Global (North America, Japan, Europe) FSK based CID (Calling Identity Delivery) / CLIP (Calling Line Identity Presentation)
• Feature phones, adjunct boxes
• F A X m a c h i n e s
• Telephone answering machines
• Computer Telephony Integration (CTI)
• Battery powered applications

Description

The MT88E39 Calling Number Identification Circuit (CNIC1.1) is a CMOS integrated circuit which provides an interface to calling line information delivery services that utilize 1200 baud Bell 202 or CCITT V.23 FSK data transmission schemes. The MT88E39 receives and demodulates the FSK signal and outputs the data into a simple dual mode 3-wire serial interface which eliminates the need for an UART. The MT88E39 is Bellcore, ETSI and NTT compatible and can operate in 3 V and 5 V applications. It is a pin to pin replacement of the MT8841 and MT88E41 by operating in the MT88E41 FSK interface mode (mode 0) when placed in a MT88E41 socket. New designs may also choose the MT88E43 compatible interface (mode 1) where the microcontroller reads the FSK byte from a 1 byte buffer. November 2004

Ordering Information

MT88E39AS 16 Pin SOIC Tubes MT88E39ASR 16 Pin SOIC Tape & Reel MT88E39AS1 16 Pin SOIC* Tubes MT88E39ASR1 16 Pin SOIC* Tape & Reel *Pb Free Matte Tin -40°C to +85 °C MT88E39 Calling Number Identification Circuit (CNIC1.1) Data Sheet Figure 1 - Functional Block Diagram GS IN- IN+ CAP VRef DATA DR DCLK CD PWDN OSC1 OSC2 MODE IC Receive Bandpass Filter Bias Generator FSK Demodulator Data and Timing Carrier Detector Clock Generator Recovery to other circuits

Zarlink Semiconductor Inc. Figure 2 - Pin Connections Pin Description Pin # Name Description 1I N + Non-inverting Op-Amp (Input). 2I N - Inverting Op-Amp (Input). 3G S Gain Select (Output). Gives access to op-amp output for connection of feedback resistor. 4V Ref Voltage Reference (Output). Nominally VDD/2. This is used to bias the op-amp inputs. 5C A P Capacitor. Connect a 0.1 µF capacitor to VSS. 6O S C 1 Oscillator (Input). Crystal connection. This pin can be driven directly from an external clocking source. 7O S C 2 Oscillator (Output). Crystal connection. When OSC1 is driven by an external clock, this pin should be left open. 8V SS Power supply ground. 9 DCLK 3-wire FSK Interface: Data Clock (CMOS Output/Schmitt Input). In mode 0 (MT88E41 compatible mode - when the MODE pin is logic low) this is a CMOS output which denotes the nominal mid-point of a FSK data bit. In mode 1 (when the MODE pin is logic high) this is a Schmitt trigger input used to shift the FSK data byte out to the DATA pin. 10 DATA 3-wire FSK Interface: Data (CMOS Output). In mode 0 (MT88E41 compatible mode - when the MODE pin is logic low) the FSK serial bit stream is output to DATA as demodulated. Mark frequency corresponds to logical 1. Space frequency corresponds to logical 0. In mode 1 (when the MODE pin is logic high) the start and stop bits are stripped off and only the data byte is stored in a 1 byte buffer. At the end of each word signalled by the DR pin, the microcontroller should shift the byte out to DATA pin by applying 8 read pulses at the DCLK pin. 11 DR 3-wire FSK Interface: Data Ready (Open Drain/CMOS Output). Active low. In mode 0 (MT88E41 compatible mode - when the MODE pin is logic low) this is an open drain output. In mode 1 (when the MODE pin is logic high) this is a CMOS output. This pin denotes the end of a word. Typically, DR is used to interrupt the microcontroller. It is normally hi-Z or high (modes 0 and 1 respectively) and goes low for half a bit time at the end of a word. But in mode 1 if DCLK begins during DR low, the first rising edge of the DCLK input will return DR to high. This feature allows an interrupt requested by DR to be cleared upon reading the first DATA bit. IN+ IN- GS VRef CAP OSC1 OSC2 VSS VDD IC** MODE* PWDN CD DR DATA DCLK * Was IC1 in MT88E41 ** Was IC2 in MT88E41

16 PIN SOIC

Zarlink Semiconductor Inc. Functional Description The MT88E39 is a FSK demodulator compatible with FSK based Caller ID services around the world, such as in North America, France, Germany, and Japan. Caller ID is the generic term for a group of services offered by telephone operating companies whereby information about the calling party is delivered to the subscriber. In the FSK based methods, the information is modulated in eith er Bell 202 (in North America) or CCITT V.23 (in Europe) FSK format and transmitted at 1200 baud from the serving end office to the subscriber’s terminal. In North America, Caller ID uses the voiceband data tran smission interface defined in the Bellcore document GR- 30-CORE. The terminal or CPE (Customer Premises E quipment) requirements are defined in Bellcore document SR-TSV-002476. Typical serv ices are CND (Calling Numb er Delivery), CNAM (Ca lling Name Delivery), VMWI (Visual Message Waiting Indicator) and CIDCW (Calling Identity Delivery on Call Waiting). In on-hook Caller ID, such as CND and CNAM, the information is typically transmitted from the end office before the subscriber picks up the phone. There are various met hods such as between the first and second rings (North America), between an abbreviated ring and the first true ring (Japan, France and Germany). On-hook Caller ID can also occur without ringing for services such as VMWI. The MT88E39 is suitable for these forms of alerting. In off-hook Caller ID, such as CIDCW, information about a new calling party is sent to the subscriber who is already engaged in a call. Bellcore’s method uses a special dual tone known as CAS (CPE Alerting Signal) which should be detected by the CPE. After the CPE has acknowledged with a DTMF digit, the end office will send the FSK data. The MT88E39 is suitable for receiving the FSK data but a separate CAS detector is required. The MT88E39 provides an interface to the Caller ID physical layer. It bandpass filters and demodulates the 1200 baud FSK signal. It also provides a convenient interfac e to extract the demodulated FSK data. Although the main application of the MT88E39 is Caller ID, it can also be used wherever 1200 baud Bell 202 and/or CCITT V.23 FSK reception is required. 3 to 5V operation The MT88E39 can operate from 5.5 V down to 2.7 V, but the FSK reject level will change with Vd d. In a battery powered CPE, the FSK a ccept level will become lower as the batterie s are run down. If the CPE is designed for 4.5 V, the accept level will be lowered w hen the batteries drain to 3 V. In North America there is a requirement for rejecting FSK signals which are below 3 mVrms when dat a is not preceded by ringing, such as VMWI (Visual 12 CD Carrier Detect (Open Drain/CMOS Output). Active low. In mode 0 (MT88E41 compatible mode - when the MODE pin is logic low) this is an open drain output. In mode 1 (when the MODE pin is logic high) this is a CMOS output. A logic low indicates that a carrier has been present for a specified time on the line. A time hysteresis is provided to allow for momentary discontinuity of carrier. The demodulated FSK data is inhibited until the carrier has been detected. 13 PWDN Power Down (Schmitt Input). Active high. Powers down the device including the input op- amp and the oscillator. Must be low for operation. 14 MODE Mode select (Input). This pin selects the 3-wire FSK interface mode. To select mode 0 (MT88E41 compatible mode) this pin should be logic low. To select mode 1 this pin should be logic high. Because this pin is already connected to Vss in ’E41 applications, the MT88E39 can replace the ’E41 without any circuit or software change. 15 IC Internal Connection. Internal connection. Leave open circuit. In MT88E41, this was IC2 which was also left open in the application circuit. 16 V DD Positive power supply voltage. Pin Description Pin # Name Description

Zarlink Semiconductor Inc. Mode 0 This mode is selected when the MODE pin is low. It is the MT88E41 compatible mode where the FSK data stream is output as demodulated. Since the MODE pin was IC1 in MT88E41 and connected to Vss, the MT88E39 will work in mode 0 when placed in a MT88E41 socket. In this mode, the MT88E39 receives the FSK signal, dem odulates it, and outputs the data directly to the DATA pin (see Figure 11). For each received stop and start bit sequence, the MT88E39 outputs a fixed frequency clock string of 8 pulses at the DCLK pin. Each DCLK rising edge occurs in the nominal centre of a data bit. DCLK is not generated for the stop and start bits. Consequently, DCLK will clock only valid data into a peripheral device such as a serial to parallel shift register or a microcontroller. The MT88E39 also outputs an end of word pulse (Data Ready) on the DR pin, which indicates the reception of every 10-bit word (counting the start and stop bits) sent from the end office. DR can be used to interrupt a microcontroller or cause a serial to parallel converter to parallel load its data into a microcontroller. The mode 0 DATA pin can also be connected to a personal computer’s serial communication port after converting from CMOS to RS-232 voltage levels. Mode 1 This mode is selected when the MODE pin is high. In this mode, the microcontroller supplies read pulses at the DCLK pin (which is now an input) to shift the 8-bit data words out of the MT88E39, onto the DATA pin. The MT88E39 asserts DR to denote the word boundary and indicate to the microprocessor that a new word has become available (see Figure 12). Internal to the MT88E39, the demodulated data bits are sampled and stored. The start and stop bits are stripped off. After the 8th bit, the data byte is parallel loaded into an 8 bit shift register and DR goes low. The shift register’s contents are shifted out to the DATA pin on the supplied DCLK’s rising edge in the order they were received. If DCLK begins while DR is low, DR will return to high upon the first DCLK. This feat ure allows the associated interrupt to be cleared by the first read pulse. Otherwise DR is low for half a nominal bit time (1/2400 sec). After the last bit has been read, additional DCLKs are ignored. Note that in both modes, the 3-pin interface may also output data generated by speech or other voiceband signals. The user may choose to ignore these outputs when FSK data is not expected, or force the MT88E39 into its power down mode. Power Down Mode For applications requiring reduced power consumption, the MT88E39 can be forced into power down when it is not needed. This is done by pulling the PWDN pin high. In power down mode, the oscillator, op-amp and internal circuitry are all disabled and the MT88E39 will not react to the input signal. DR and CD are at high impedance or at logic high (modes 0 and 1 respectively). In mode 0, DATA and DCLK are at logic high. The MT88E39 can be awakened for reception of the FSK signal by pulling the PWDN pin low. Carrier Detect The carrier detector provides an indica tion of the presence of a signal in the FSK frequency band. It detects the presence of a signal of sufficient ampl itude at the output of the FSK bandpass filter. The signal is qualified by a digital algorithm before the CD output is set low to indicate carrier detection. A 10ms hysteresis is provided to allow for momentary signal drop out once CD has been activated. CD is released when there is no activity at the FSK bandpass filter output for 10 ms. When CD is inactive (high), the raw output of the demodulator is ignored by the data timing recovery circuit (see Figure 1). In mode 0, the DATA pin is forced high. No DCLK or DR signal is generated. In mode 1, the internal shift register is not updated and no DR is generated. If DCLK is clocked (in mode 1), DATA is undefined. Note that signals such as CAS, speech and DTMF tones also lie in the FSK frequency band and the carrier detector may be activated by these signals. They will be demodulated and presented as data. To avoid false data, the PWDN pin should be used to disable the FSK demodulator when no FSK signal is expected.

Zarlink Semiconductor Inc. Ringing, on the other hand, does not pose a problem as it is ignored by the carrier detector. Crystal Oscillator The MT88E39 uses either a 3.579545 MHz ceramic resonator or crystal oscillator as the master timing source. The crystal specification is as follows: Frequency: 3.579545 MHz Frequency tolerance: ±0.2%(-40°C+85°C) Resonance mode : Parallel Load capacitance: 18 pF Maximum series resistance : 150 ohms Maximum drive level (mW): 2m W e.g., CTS MP036S Figure 5 - Common Crystal Connection For 5 V applications any number of MT88E39 devices can be connected as shown in Figure 5 such that only one crystal is required. The connection between OSC2 and OSC1 can be DC coupled as shown, or the OSC1 input on all devices can be driven from a CMOS buffer (dc coupled) with the OSC2 outputs left unconnected. VRef and CAP Inputs VRef is the output of a low impedance voltage source equal to VDD/2 and is used to bias the input op-amp. A 0.1 µF capacitor is required between CAP and VSS to suppress noise on VRef. Table 1 shows the Bellcore and ETSI FSK signal characteristics. The application circuit in Figure 6 will meet these requirements. For 5 V designs the input op-amp should be set to unity gain to meet the Bellcore requirements and -2.5 dB gain for ETSI requirements. As supply voltage (VDD) is decreased, the FSK detect threshold will be lowered. Therefore for designs operating at other than 5 V nominal voltage, to meet the FSK reject level requirement the gain of the op-amp should be reduced accordingly. For 3 V designs the gain settings for Bellcore and ETSI should be -3 dB and -5.5 dB respectively. For applications requiring detection of lower FSK signal level, the i nput op-amp may be configured to provide adequate gain. However, too much gain will cause noise tolerance to fail the TIA requirements because the FSK signal will be clipped at GS when the single tone noise is added. OSC1 OSC2 OSC1 OSC2 OSC1 OSC2

3.579545 MHz

(For 5 V application only)

Zarlink Semiconductor Inc. Figure 6 - Application Circuit IN+ IN- GS VRef OSC1 OSC2 VSS VDD IC MODE PWDN CD DATA DCLK MT88E39 CAP DR Vdd = To microcontroller = From microcontroller 100 nFTIP RING Vdd Vdd R10 464 K

200 K330 nF

10% 5% 1N5231B10% Xtal To microcontroller (Ring Detect) Vdd R8*1 R9*1 20% 20% D8 (FSK interface mode 0 selected) 250 V 50 V Note: *1 R8 and R9 not required when FSK interface mode 1 is selected. Unless stated otherwise, resistors are 1%, 0.1 Watt; capacitors are 5%, 6.3 V D1, D2, D3, D4 = diodes, 1N4003 or 1N4148 or equivalent D5, D6, D7, D8 = bridge rectifier diodes, 1N914 Xtal = 3.579545 MHz, +/-0.2% R8 = R9 = 100 K, 20% R10 = 12K1, 1W5, 5%, Fusible resistor R2 = R4 = 34 K For 1000 Vrms, 60 Hz isolation from Tip to Earth and Ring to Earth: R1 = R3 = 430 K, 0.5 W, 5%, 475 V minimum. e.g., IRC Type GS-3 C1 = C2 = 2 n2, 1332 V minimum If the 1000Vrms is met by other means, then this circuit has to meet FCC part 68 Type B Ringing: R1 = R3 = 432 K, 0.1 W, 1%, 56 V minimum C1 = C2 = 2n2, 212V minimum Example of component values for Vdd = 5 V +/- 10% For Bellcore applications, set input gain = 0 dB: For ETSI applications, set input gain = -2.5 dB: R5 = 53K6 R5 = 53K6 R6 = 60K4 R6 = 63K4 R7 = 464K R7 = 348K Example of component values for Vdd = 3 V +/- 10% For Bellcore applications, set input gain = -3 dB: For ETSI applications, set input gain = -5.5 dB: R5 = 44K2 R5 = 44K2 R6 = 51K1 R6 = 53K6 R7 = 332K R7 = 249K

Zarlink Semiconductor Inc. Note: *1: Recommended by TIA/EIA-716. Bellcore has agreed to the values an d will incorporate them into its future standards. *2: ETS 300 778-1 (On-hook) Sep 97, ETS 300 778-2 (Off-hook) Jan 97. *3: dBm = Decibels above or below a reference power of 1 mW into 600 ohms. 0 dBm = 0.7746 Vrms. *4: dBV = Decibels above or below a reference voltage of 1 Vrms. 0 dBV = 1 Vrms. *5: On-hook signal range. The Off-hook signal levels are inside this range: -30.78 to -7.78 dBm. Figure 7 - Application Circuit (multiple interrupt source) Parameter North America: Bellcore *1 Europe: ETSI *2 Mark (logical 1) frequency 1200 Hz +/- 1% 1300 Hz +/- 1.5% Space (logical 0) frequency 2200 Hz +/- 1% 2100 Hz +/- 1.5% Received signal level -36.20 to -4.23 dBm *3 (12 to 476 mVrms) -33.78 to -5.78 dBm Reject signal level -48.23 dBm (3 mVrms) (VMWI only) -47.78 dBm (-50 dBV) Transmission rate 1200 baud +/- 1% 1200 baud +/- 1% Twist -6 to +10 dB -6 to +6 dB Signal to noise ratio Single tone (f): -18 dB (f<=60 Hz) +25 dB (200<f<3200 Hz) +6 dB (f>=3200 Hz) >= 25 db (300 to 3400 Hz) MT88E39 FSK input gain for Vdd = 5 V +/-10% 0d B - 2 . 5d B Table 1 - FSK signal characteristics specified by some standard bodies Interrupt Source 1 Interrupt Source 2 MT88E39 Vdd Vdd *R2 can be omitted if mode 1 is selected R2 * Vdd INT (input) Microcontroller Input Port Bit R1 can be opened and D1 shorted if the microcontroller does not read the INT1 pin. INT1 (open drain) INT2 (CMOS) DR (Mode 0: Open Drain) (Mode 1: CMOS

Zarlink Semiconductor Inc. * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. † DC Electrical Characteristics are over recommended operating conditions unless otherwise stated. * Typical figures are at 25 °C and are for design aid only. Note 1: PWDN = Vdd. FSK input = 0 mVrms. Digital inputs at either Vdd or Vss. No current drawn from output pins. Note 2: PWDN = Vss. FSK input = 0 mVrms. With no current drawn from Vref, OSC2 and all digital pins. Absolute Maximum Ratings* - Voltages are with respect to VSS unless otherwise stated. Parameter Symbol Min. Max. Units 1 DC Power Supply Voltage V DD to VSS VDD -0.3 6 V 2 Voltage on any pin V P -0.3 V DD+0.3 V

3 Current at any pin (except V DD and VSS)I I/O ±10 mA

4 Storage Temperature T ST -65 +150 °C

5 Package Power Dissipation P D 500 mW

Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics Sym. Min. Typ. Max. Units Test Conditions 1 DC Power Supply Voltage V DD 2.7 5.5 V 2 Clock Frequency f OSC 3.579545 MHz 3 Tolerance on Clock Frequency ∆fc ±0.2 %

4 Operating Temperature -40 +85 °C

Characteristics Sym. Min. Typ.* Max. Units Test Conditions 1 S U P P L Y Standby Supply Current I DDQ 0.1 15 µA Notes* 1

2 Operating Supply Current

VDD = 3.0 V, 25oC VDD = 5.0 V, 25oC IDD 1.2 1.9 2.0 3.0 mA mA Notes* 2

3 DR,

CD, DATA, DCLK Sink Current I OL 2.5 mA V OL = 0.1 VDD

4 Source current

DCLK (in mode 0) DR, CD (in mode 1) IOH 0.8 mA V OH = 0.9 VDD

5 DR, CD Output hi-Z current

(in mode 0) IOZ 10 µAV OZ=VSS to VDD

6 PWDN,

(in mode Schmitt Input High Threshold Schmitt Input Low Threshold VT+ VT- 0.48*VDD 0.28*VDD 0.68*VDD 0.48*VDD V V 7 Schmitt Hysteresis V HYS 0.2 V

8 MODE CMOS Input High Voltage

0.7*VDD VSS VDD 0.3*VDD V

9 PWDN,

DCLK, MODE Input Current I IN 10 µAV SS ≤ VIN ≤ VDD VRef Output Voltage V Ref 0.5*VDD - 0.1 0.5*V DD + 0.1 V No Load

11 Output Resistance R Ref 2k Ω

Zarlink Semiconductor Inc. † Electrical characteristics are over recommended operating conditions, unless otherwise stated. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. † AC Electrical Characteristics are over recommended operating conditions, unless otherwise stated. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. Notes*: 1. dBm = Decibels above or below a reference power of 1 mW into 600 Ω. 0 dBm = 0.7746 Vrms. 2. dBV = Decibels above or below a reference voltage of 1 Vrms. 0 dBV = 1 Vrms. 3. Input op-amp configured to 0 dB gain at Vdd = 5 V+/-10%, -3 dB at Vdd = 3 V+/-10%. 4. Mark and Space frequencies have the same amplitude. 5. Band limited random noise (200-3400 Hz). Present when FSK signal present. 6. OSC1 at 3.579545 MHz ±0.2%. Electrical Characteristics† - Gain Setting Amplifier Characteristics Sym. Min. Typ. ‡ Max. Units Test Conditions

1 Input Leakage Current I IN 1 µAV SS ≤ VIN ≤ VDD

2 Input Resistance R in 5M Ω

3 Input Offset Voltage V OS 25 mV

4 Power Supply Rejection Ratio PSRR 30 dB 1 kHz ripple on V DD

5 Common Mode Rejection CMRR 30 dB V CMmin ≤ VIN ≤ VCMmax

6 DC Open Loop Voltage Gain A VOL 40 dB

7 Unity Gain Bandwidth f C 0.2 MHz 8 Output Voltage Swing V O 0.5 VDD-0.7 V Load ≥ 100 kΩ

9 Capacitive Load (GS) C L 50 pF

10 Resistive Load (GS) R L 100 k Ω

11 Common Mode Voltage Range V CM 1.0 VDD-1.0 V Characteristics Sym. Min. Typ. ‡ Max. Units Notes* 1 Input Detection Level -37.78 -40 -1.78 631 dBm dBV mVrms 1, 2, 3, 4

2 Input Baud Rate 1188 1200 1212 baud 6

3 Input Frequency Detection

Bell 202 1 (Mark) Bell 202 0 (Space) CCITT V.23 1 (Mark) CCITT V.23 0 (Space) 1188 2178 1280.5 2068.5 1200 2200 1300 2100 1212 2222 1319.5 2131.5 Hz Hz Hz Hz

4 Input Noise Tolerance 20 log SNR 20 dB 3, 4, 5

5T w i s t =20 log -6 10 dBVMark VSpace

Zarlink Semiconductor Inc. † AC Electrical Characteristics are over recommende d operating conditions unless otherwise stated. ‡ Typical figures are at 25 °C and are for design aid only, not guaranteed and not subject to production testing. Notes*: 1. The device will stop functioning within this time , but more time may be required to reach I DDQ. † AC Electrical Characteristics are over recommende d operating conditions unless otherwise stated. ‡ Typical figures are at 25 °C and are for design aid only, not guaranteed and not subject to production testing. Notes*: 1. FSK input data at 1200 ±12 baud. 2. OSC1 at 3.579545 MHz ±0.2%. 3. 10 k to V SS, 50pF to V SS. 4. 10 k to V DD, 50pF to V SS. 5. Function of signal condition. 6. For a repeating mark space seq uence, the data stream will typically have equal 1 and 0 bit durations. Characteristics Sym. Min. Typ. ‡ Max. Units Notes*

1 PWDN

2 Power-down time t PD 100 1000 µs1

Input FSK to CD low delay t IAL 25 ms

4 Input FSK to CD high delay t IAH 10 ms

5H y s t e r e s i s 1 0 m s

1 DATA Rate 1188 1200 1212 bps 1, 6

2 Input FSK to DATA delay t IDD 15 m s

4 Fall time t F 200 ns 3

5 DATA to DCLK delay t DCD 64 1 6 µs 1, 2, 5, 6

6 DCLK to DATA delay t CDD 64 1 6 µs 1, 2, 5, 6

Frequency 1200.4 1202.8 1205.2 Hz 2

8 High time t CH 415 416 417 µs2

9 Low time t CL 415 416 417 µs2

10 DCLK

DCLK to DR delay t CRD 415 416 417 µs2 DR Rise time t RR 10 µs4

12 Fall time t FF 200 ns 4

13 Low time t RL 415 416 417 µs2

Zarlink Semiconductor Inc. Figure 12 - Serial Data Interface Timing (Mode 1) DCLK clears DR stop start stop0 1 23 4 5 677 word N word N+1 0 1 2 3 4 5 67 word N word N-1 1/fDCLK1 tRL tDDH tDDS Demodulated DR (Data Ready) DCLK (Data Clock)* DATA Output Data (Internal Signal) DCLK does not clear DR, so DR is low for maximum time (1/2 bit time) CMOS Output Schmitt Input The DCLK input must be low before and after DR falling edge*

www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a licence under the Philips I 2C Patent rights to use these components in and I 2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE For more information about all Zarlink products visit our Web Site at