MT8889C MITEL | Alldatasheet
Document overview
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Technical content
Features
- Central office quality DTMF transmitter/ receiver
- Low power consumption
- High speed adaptive micro interface
- Adjustable guard time
- Automatic tone burst mode
- Call progress tone detection to -30dBm
Applications
- Credit card systems
- Paging systems
- Repeater systems/mobile radio
- Interconnect dialers
- Personal computers
Description
The MT8889C is a monolithic DTMF transceiver with call progress filter. It is fabricated in CMOS technology offering low power consumption and high reliability. The receiver section is based upon the industry standard MT8870 DTMF receiver while the transmitter utilizes a switched capacitor D/A converter for low distortion, high accuracy DTMF signalling. Internal counters provide a burst mode such that tone bursts can be transmitted with precise timing. A call progress filter can be selected allowing a microprocessor to analyze call progress tones. The MT8889C utilizes an adaptive micro interface, which allows the device to be connected to a number of popular microcontrollers with minimal external logic. The MT8889C-1 is functionally identical to the MT8889C except the receiver is enhanced to accept lower level signals, and also has a specified low signal rejection level.
Ordering Information
MT8889CE/CE-1 20 Pin Plastic DIP MT8889CC/CC-1 20 Pin Ceramic DIP MT8889CS/CS-1 20 Pin SOIC MT8889CN/CN-1 24 Pin SSOP -40°C to +85°C Figure 1 - Functional Block Diagram TONE IN+ IN- GS OSC1 OSC2 VDD VRef V SS ESt St/GT IRQ/CP DS/RD CS R/W /WR RS0 ∑ D/A Converters Row and Column Counters Transmit Data Register Data Bus Buffer Tone Burst Gating Cct. Oscillator Circuit Bias Circuit Control Logic Digital Algorithm and Code Converter Control Logic Steering Logic Status Register Control Register A Control Register B Receive Data Register Interrupt Logic I/O ControlLow Group Filter High Group Filter Dial Tone Filter ISSUE 2 May 1995 MT8889C/MT8889C-1 Integrated DTMF Transceiver with Adaptive Micro Interface
Figure 2 - Pin Connections Pin Description Pin # Name Description20 24 11 I N + Non-inverting op-amp input. 22 I N - Inverting op-amp input. 33 G S Gain Select. Gives access to output of front end differential amplifier for connection of feedback resistor. 44 V Ref Reference Voltage output (VDD /2). 55 V SS Ground (0V). 66 O S C 1 Oscillator input. This pin can also be driven directly by an external clock. 77 O S C 2 Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes the internal oscillator circuit. Leave open circuit when OSC1 is driven externally. 8 10 TONE Output from internal DTMF transmitter. 91 1 R / W (WR ) (Motorola) Read/Write or (Intel) Write microprocessor input. TTL compatible. 10 12 CS Chip Select input. This signal must be qualified externally by either address strobe (AS), valid memory address (VMA) or address latch enable (ALE) signal, see Figure 12. 11 13 RS0 Register Select input. Refer to Table 3 for bit interpretation. TTL compatible. 12 14 DS (RD ) (Motorola) Data Strobe or (Intel) Read microprocessor input. Activity on this input is only required when the device is being accessed. TTL compatible. 13 15 IRQ /CP Interrupt Request/Call Progress (open drain) output. In interrupt mode, this output goes low when a valid DTMF tone burst has been transmitted or received. In call progress mode, this pin will output a rectangular signal representative of the input signal applied at the input op-amp. The input signal must be within the bandwidth limits of the call progress filter, see Figure 8. 14- 18- D0-D3 Microprocessor data bus. High impedance when CS = 1 or DS =0 (Motorola) or RD = 1 (Intel). TTL compatible. 18 22 ESt Early Steering output. Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low. 19 23 St/GT Steering Input/Guard Time output (bidirectional). A voltage greater than VTSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than V TSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St. 20 24 V DD Positive power supply (5V typ.). 8,9 16, NC No Connection. 10 11 IN+ IN- GS VRef VSS OSC1 OSC2 TONE R/W /WR CS VDD St/GT ESt IRQ /CP DS/RD RS0 NC 12 13 IN+ IN- GS VRef VSS OSC1 OSC2 NC TONE R/W /WR CS VDD St/GT ESt NC NC IRQ /CP DS/RD RS0
24 PIN SSOP20 PIN CERDIP/PLASTIC DIP/SOIC
Figure 9 - Description of Timing Events EXPLANATION OF EVENTS A) TONE BURSTS DETECTED, TONE DURATION INVALID, RX DATA REGISTER NOT UPDATED. B) TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER. C) END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER RETAINED UNTIL NEXT VALID TONE PAIR. D) TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER. E) ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, DATA REMAINS UNCHANGED. F) END OF TONE #n+1 DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER RETAINED UNTIL NEXT VALID TONE PAIR. EXPLANATION OF SYMBOLS V in DTMF COMPOSITE INPUT SIGNAL. ESt EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES. St/GT STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT. RX 0-RX 3 4-BIT DECODED DATA IN RECEIVE DATA REGISTER b3 DELAYED STEERING. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. ACTIVE LOW FOR THE DURATION OF A VALID DTMF SIGNAL. b2 INDICATES THAT VALID DATA IS IN THE RECEIVE DATA REGISTER. THE BIT IS CLEARED AFTER THE STATUS REGISTER IS READ. IRQ/CP INTERRUPT IS ACTIVE INDICATING THAT NEW DATA IS IN THE RX DATA REGISTER. THE INTERRUPT IS CLEARED AFTER THE STATUS REGISTER IS READ. tREC MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID. tREC MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION. tID MINIMUM TIME BETWEEN VALID SEQUENTIAL DTMF SIGNALS. tDO MAXIMUM ALLOWABLE DROPOUT DURING VALID DTMF SIGNAL. tDP TIME TO DETECT VALID FREQUENCIES PRESENT. tDA TIME TO DETECT VALID FREQUENCIES ABSENT. tGTP GUARD TIME, TONE PRESENT. tGTA GUARD TIME, TONE ABSENT. DTMF Generator The DTMF transmitter employed in the MT8889C/ MT8889C-1 is capable of generating all sixteen standard DTMF tone pairs with low distortion and high accuracy. All frequencies are derived from an external 3.579545 MHz crystal. The sinusoidal waveforms for the individual tones are digitally synthesized using row and column programmable dividers and switched capacitor D/A converters. The row and column tones are mixed and filtered providing a DTMF signal with low total harmonic distortion and high accuracy. To specify a DTMF signal, data conforming to the encoding format shown in T able 1 must be written to the transmit Data Register. Note that this is the same as the receiver output code. The individual tones which are generated (f LOW and fHIGH ) are referred to as Low Group and High Group tones. As seen from the table, the low group frequencies are 697, 770, 852 and 941 Hz. The high group frequencies are 1209, 1336, 1477 and 1633 Hz. Typically, the high group to low group amplitude ratio (twist) is 2 dB to com- pensate for high group attenuation on long loops. The period of each tone consists of 32 equal time segments. The period of a tone is controlled by varying the length of these time segments. During write operations to the Transmit Data Register the 4 bit data on the bus is latched and converted to 2 of 8 coding for use by the programmable divider circuitry. This code is used to specify a time segment length, which will ultimately determine the frequency of the tone. When the divider reaches the appropriate count, as determined by the input code, a reset pulse is issued and the counter starts again. The number of time segments is fixed at 32, however, by varying the segment length as described above the frequency can also be varied. The divider output clocks another counter, which addresses the sinewave lookup ROM. The lookup table contains codes which are used by the switched capacitor D/A converter to obtain discrete and highly accurate DC voltage levels. Two identical circuits are employed to produce row and column tones, which are then mixed using a low noise summing amplifier. The oscillator described needs no “start-up” time as in other DTMF generators since the crystal oscillator is running continuously thus providing a high degree of tone burst accuracy. A bandwidth limiting filter is incorporated and serves to attenuate distortion products above 8 kHz. It can be seen from Figure 6 that the distortion products are very low in amplitude.
symmetric bursts/pauses of predetermined duration. indicating that the transmitter is ready for more data. and disabling the transmitter. Control Register B description for details. Table 2. Actual Frequencies Versus Standard fundamental frequency expressed as a percentage.
The Fourier components of the tone output correspond to V2f.... Vnf as measured on the output waveform. The total harmonic distortion for a dual tone can be calculated using Equation 2. VL and VH correspond to the low group amplitude and high group amplitude, respectively and V2 IMD is the sum of all the intermodulation components. The internal switched-capacitor filter following the D/A converter keeps distortion products down to a very low level as shown in Figure 10. Equation 2. THD (%) For a Dual Tone DTMF Clock Circuit The internal clock circuit is completed with the addition of a standard television colour burst crystal. The crystal specification is as follows: Frequency: 3.579545 MHz Frequency Tolerance: ±0.1% Resonance Mode: Parallel Load Capacitance: 18pF Maximum Series Resistance:150 ohms Maximum Drive Level: 2mW e.g. CTS Knights MP036S Toyocom TQC-203-A-9S A number of MT8889C/MT8889C-1 devices can be connected as shown in Figure 11 such that only one crystal is required. Alternatively, the OSC1 inputs on all devices can be driven from a TTL buffer with the OSC2 outputs left unconnected. Figure 11 - Common Crystal Connection Microprocessor Interface The MT8889C/MT8889C-1 design incorporates an adaptive interface, which allows it to be connected to L + V2 H 2L + V2 3L + .... V2 nL + V2 2H + 3H + .. V2 nH + V2 IMD THD (%) = 100 MT8889C/ OSC1 OSC2 MT8889C/ OSC1 OSC2 MT8889C/ OSC1 OSC2
3.579545 MHz
MT8889C-1 MT8889C-1 MT8889C-1 various kinds of microprocessors. Key functions of this interface include the following:
- Continuous activity on DS/RD is not necessary to update the internal status registers.
- senses whether input timing is that of an Intel or Motorola controller by monitoring the DS (RD ), R/W (WR ) and CS inputs.
- generates equivalent CS signal for internal operation for all processors.
- differentiates between multiplexed and non- multiplexed microprocessor buses. Address and data are latched in accordingly.
- compatible with Motorola and Intel processors. Figure 17 shows the timing diagram for Motorola microprocessors with separate address and data buses. Members of this microprocessor family include 2 MHz versions of the MC6800, MC6802 and MC6809. For the MC6809, the chip select (CS ) input signal is formed by NANDing the (E+Q) clocks and address decode output. For the MC6800 and MC6802, CS is formed by NANDing VMA and address decode output. On the falling edge of CS, the internal logic senses the state of data strobe (DS). When DS is low, Motorola processor operation is selected. Figure 18 shows the timing diagram for the Motorola MC68HC11 (1 MHz) microcontroller. The chip select (CS ) input is formed by NANDing address strobe (AS) and address decode output. Again, the MT8889C/MT8889C-1 examines the state of DS on the falling edge of CS to determine if the micro has a Motorola bus (when DS is low). Additionally, the Texas Instruments TMS370CX5X is qualified to have a Motorola interface. Figure 12(a) summarizes connection of these Motorola processors to the MT8889C/MT8889C-1 DTMF transceiver. Figures 19 and 20 are the timing diagrams for the Intel 8031/8051 (12 MHz) and 8085 (5 MHz) micro- controllers with multiplexed address and data buses. The MT8889C/MT8889C-1 latches in the state of RD on the falling edge of CS. When RD is high, Intel processor operation is selected. By NANDing the address latch enable (ALE) output with the high-byte address (P2) decode output, CS can be generated. Figure 12(b) summarizes the connection of these Intel processors to the MT8889C/MT8889C-1 transceiver. NOTE: The adaptive micro interface relies on high- to-low transition on CS to recognize the microcontroller interface and this pin must not be tied permanently low.
Table 6. Control Register A Description Table 7. Control Register B Description off. This bit controls all transmit tone functions. specified in the AC Electrical Characteristics for Call Progress. Note: DTMF signals cannot be detected when CP mode is selected. write cycle will be directed to control register A. Burst Mode Select. A logic high de-activates burst mode; a logic low enables burst mode. durations are extended from a typical duration of 51 msec to 102 msec. TOUT bit (control register A, b0). STEERING bit of the status register (see Figure 7, signal b3).
Table 8. Status Register Description (b1) or bit two (b2) is set. read or when in non-burst mode. the absence of a DTMF signal.
- Microprocessor based systems can inject undesirable noise into the supply rails.
connected close to the device and ground loops should be avoided.
Figure 15 - Application Notes TEST POINT MMD6150 (or equivalent)
5.0 VDC
2.4 kΩ 24 kΩ130 pF MMD7000 (or equivalent) TEST POINT 3 kΩ 100 pF Test load for IRQ/CP pinTest load for D0-D3 pins INITIALIZATION PROCEDURE A software reset must be included at the beginning of all programs to initialize the control registers after power up. The initialization procedure should be implemented 100ms after power up. Description: Motorola Intel Data RS0 R/W WR RD b3 b2 b1 b0 1) Read Status Register 1 1 1 0 X X X X 2) Write to Control Register 1 0 0 1 0 0 0 0 3) Write to Control Register 1 0 0 1 0 0 0 0 4) Write to Control Register 1 0 0 1 1 0 0 0 5) Write to Control Register 1 0 0 1 0 0 0 0 6) Read Status Register 1 1 1 0 X X X X TYPICAL CONTROL SEQUENCE FOR BURST MODE APPLICATIONS Transmit DTMF tones of 50 ms burst/50 ms pause and Receive DTMF Tones. Sequence: RS0 R/W WR RD b3 b2 b1 b0 1) Write to Control Register A 1 0 0 1 1 1 0 1 (tone out, DTMF , IRQ, Select Control Register B) 2) Write to Control Register B 1 0 0 1 0 0 0 0 (burst mode) 3) Write to Transmit Data Register 0 0 0 1 0 1 1 1 (send a digit 7) 4) Wait for an Interrupt or Poll Status Register 5) Read the Status Register 1 1 1 0 X X X X -if bit 1 is set, the Tx is ready for the next tone, in which case ... Write to Transmit Register 0 0 0 1 0 1 0 1 (send a digit 5) -if bit 2 is set, a DTMF tone has been received, in which case .... Read the Receive Data Register 0 1 1 0 X X X X -if both bits are set ... Read the Receive Data Register 0 1 1 0 X X X X Write to Transmit Data Register 0 0 0 1 0 1 0 1 NOTE: IN THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SET UNTIL 100 ms ( ±2 ms) AFTER THE DATA IS WRITTEN TO THE TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO 200 ms (± 4 ms)
- Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. ‡ Typical figures are at 25 °C and for design aid only: not guaranteed and not subject to production testing. † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25 °C, VDD =5V and for design aid only: not guaranteed and not subject to production testing. * See “Notes” following AC Electrical Characteristics Tables. Absolute Maximum Ratings* Parameter Symbol Min Max Units
1 Power supply voltage VDD -VSS VDD 6V
2 Voltage on any pin V I VSS -0.3 V DD +0.3 V
3 Current at any pin (Except VDD and VSS )1 0 m A
4 Storage temperature T ST -65 +150 °C
5 Package power dissipation P D 1000 mW
Recommended Operating Conditions - Voltages are with respect to ground (VSS ) unless otherwise stated. Parameter Sym Min Typ ‡ Max Units Test Conditions 1 Positive power supply V DD 4.75 5.00 5.25 V
2 Operating temperature T O -40 +85 °C
3 Crystal clock frequency f CLK 3.575965 3.579545 3.583124 MHz Characteristics Sym Min Typ ‡ Max Units Test Conditions 1 S U P Operating supply voltage V DD 4.75 5.0 5.25 V 2 Operating supply current I DD 7.0 11 mA 3 Power consumption P C 57.8 mW 4 I N P U T S High level input voltage (OSC1) VIHO 3.5 V Note 9*
5 Low level input voltage
(OSC1) VILO 1.5 V Note 9* 6 Steering threshold voltage V TSt 2.2 2.3 2.5 V V DD =5V O U T P U T S Low level output voltage (OSC2) V OLO 0.1 V No load Note 9*
8 High level output voltage
(OSC2) V OHO 4.9 V No load Note 9*
9 Output leakage current
(IRQ) I OZ 11 0 µAV OH =2.4 V 10 V Ref output voltage V Ref 2.4 2.5 2.6 V No load, V DD =5V 11 V Ref output resistance R OR 1.3 k Ω 12 D i g i t a l Low level input voltage V IL 0.8 V 13 High level input voltage V IH 2.0 V
14 Input leakage current I IZ 10 µAV IN=V SS to VDD
15 Data
Source current I OH -1.4 -6.6 mA V OH =2.4V 16 Sink current I OL 2.0 4.0 mA V OL =0.4V
17 ESt
Source current I OH -0.5 -3.0 mA V OH =4.6V 18 Sink current I OL 24 m A V OL =0.4V
19 IRQ /
Sink current I OL 41 6 m A V OL =0.4V
‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing. † Characteristics are over recommended temperature and at VDD =5V, using the test circuit shown in Figure 13. † Characteristics are over recommended operating conditions (unless otherwise stated) using the test circuit shown in Figure 13. † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C, VDD = 5V, and for design aid only: not guaranteed and not subject to production testing. * *See “Notes” following AC Electrical Characteristics Tables.
Electrical Characteristics
Gain Setting Amplifier - Voltages are with respect to ground (VSS ) unless otherwise stated, VSS = 0V , VDD =5V, TO =25°C. Characteristics Sym Min Typ ‡ Max Units Test Conditions
1 Input leakage current I IN ±100 nA V SS ≤ VIN ≤ VDD
2 Input resistance R IN 10 M Ω
3 Input offset voltage V OS 25 mV
4 Power supply rejection PSRR 60 dB 1 kHz
5 Common mode rejection CMRR 60 dB 0.75 ≤ V IN ≤ 4.25V
6 DC open loop voltage gain A VOL 65 dB
7 Unity gain bandwidth BW 1.5 MHz
8 Output voltage swing V
O 4.5 V pp R L ≥ 100 kΩ to VSS
9 Allowable capacitive load (GS) C L 100 pF
10 Allowable resistive load (GS) R L 50 k Ω
11 Common mode range V CM 3.0 V pp No Load Characteristics Sym Min Typ Max Units Notes* R X Valid input signal levels (each tone of composite signal) 21.8 869 mV RMS 1,2,3,5,6
2 Input Signal Level Reject -37 dBm 1,2,3,5,6
10.9 mV RMS 1,2,3,5,6 Characteristics Sym Min Typ ‡ Max Units Notes* 1 R X Valid input signal levels (each tone of composite signal) 27.5 869 mV RMS 1,2,3,5,6 Characteristics Sym Min Typ ‡ Max Units Notes* R X Positive twist accept 8 dB 2,3,6,9
2 Negative twist accept 8 dB 2,3,6,9
3 Freq. deviation accept ±1.5%± 2Hz 2,3,5 4 Freq. deviation reject ±3.5% 2,3,5
5 Third tone tolerance -16 dB 2,3,4, 5,9,10
6 Noise tolerance -12 dB 2,3,4,5,7,9,10
7 Dial tone tolerance 22 dB 2,3,4,5,8,9
† Characteristics are over recommended operating conditions unless otherwise stated ‡ Typical figures are at 25°C, VDD =5V, and for design aid only: not guaranteed and not subject to production testing † Characteristics are over recommended operating conditions unless otherwise stated ‡ Typical figures are at 25°C, VDD =5V, and for design aid only: not guaranteed and not subject to production testing † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing. Characteristics Sym Min Typ ‡ Max Units Conditions
1 Accept Bandwidth f A 310 500 Hz @ -25 dBm,
2 Lower freq. (REJECT) f LR 290 Hz @ -25 dBm 3 Upper freq. (REJECT) f HR 540 Hz @ -25 dBm
4 Call progress tone detect level (total
power) -30 dBm values are user selectable as per Figures 5, 6 and 7. Characteristics Sym Min Typ ‡ Max Units Conditions
1 Minimum tone accept duration t REC 40 ms
2 Maximum tone reject duration t REC 20 ms
3 Minimum interdigit pause duration t ID 40 ms
4 Maximum tone drop-out duration t OD 20 ms
Characteristics Sym Min Typ ‡ Max Units Conditions 1 T O N E I N Tone present detect time t DP 3 11 14 ms Note 11 2 Tone absent detect time t DA 0.5 4 8.5 ms Note 11
3 Delay St to b3 t PStb3 13 µs See Figure 7
4 Delay St to RX 0-RX3 tPStRX 8 µs See Figure 7
T O N E O U T Tone burst duration t BST 50 52 ms DTMF mode
6 Tone pause duration t PS 50 52 ms DTMF mode
7 Tone burst duration (extended) t BSTE 100 104 ms Call Progress mode
8 Tone pause duration (extended) t PSE 100 104 ms Call Progress mode
9 High group output level V HOUT -6.1 -2.1 dBm R L=10kΩ 10 Low group output level V LOUT -8.1 -4.1 dBm R L=10kΩ
11 Pre-emphasis dB P 023 d B R L=10kΩ
12 Output distortion (Single Tone) THD -35 dB 25 kHz Bandwidth
L=10kΩ 14 Frequency deviation f D ±0.7 ±1.5 % f C =3.579545 MHz
15 Output load resistance R LT 10 50 k Ω
X T A L Crystal/clock frequency f C 3.5759 3.5795 3.5831 MHz 17 Clock input rise and fall time t CLRF 110 ns Ext. clock 18 Clock input duty cycle DC CL 40 50 60 % Ext. clock
19 Capacitive load (OSC2) C LO 30 pF
† Characteristics are over recommended operating conditions unless otherwise stated ‡ Typical figures are at 25°C, VDD =5V, and for design aid only: not guaranteed and not subject to production testing NOTES: 1) dBm=decibels above or below a reference power of 1 mW into a 600 ohm load. 2) Digit sequence consists of all 16 DTMF tones. 3) T one duration=40 ms. T one pause=40 ms. 4) Nominal DTMF frequencies are used. 5) Both tones in the composite signal have an equal amplitude. 6) The tone pair is deviated by ± 1.5 %±2 Hz. 7) Bandwidth limited (3 kHz) Gaussian noise. 8) The precise dial tone frequencies are 350 and 440 Hz (±2 %). 9) Guaranteed by design and characterization. Not subject to production testing. 10) Referenced to the lowest amplitude tone in the DTMF signal. 11) For guard time calculation purposes. Figure 16 - DS/RD/WR Clock Pulse Characteristics Sym Min Typ ‡ Max Units Conditions 1D S / R D/WR clock frequency f CYC 4.0 MHz Figure 16 2D S / R D/WR cycle period t CYC 250 ns Figure 16 3D S / R D/WR low pulse width tCL 150 ns Figure 16 4D S / R D/WR high pulse width t CH 100 ns Figure 16 5D S / R D/WR rise and fall time t R,tF 20 ns Figure 16 6R / W setup time t RWS 23 ns Figures 17 & 18 7R / W hold time t RWH 20 ns Figures 17 & 18