MT8885AE

MT8885 MITEL | Alldatasheet

Document overview

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Technical content

Features

• External power down pin
• Central office quality DTMF transmitter/ receiver
• Low power consumption
• High speed adaptive micro interface
• Adjustable guard time
• Automatic tone burst mode
• Call progress tone detection to -30dBm
• DTMF transmitter/receiver power down via register control

Applications

• Credit card systems
• Paging systems
• Repeater systems/mobile radio
• Interconnect dialers
• Personal computers

Description

The MT8885 is a monolithic DTMF transceiver with call progress filter. It is fabricated in CMOS technology offering low power consumption and high reliability. The receiver section is based upon the industry standard MT8870 DTMF receiver while the transmitter utilizes a switched capacitor D/A converter for low distortion, high accuracy DTMF signalling. Internal counters provide a burst mode such that tone bursts can be transmitted with precise timing. A call progress filter can be selected allowing a microprocessor to analyze call progress tones. The MT8885 utilizes an adaptive micro interface, which allows the device to be connected to a number of popular microcontrollers with minimal external logic. The MT8885 provides enhanced power down features. The transmitter and receiver may independently be powered down via register control. A full chip power down pin provides simple power and control capability. Figure 1 - Functional Block Diagram TONE IN+ IN- GS OSC1 OSC2 VDD VRef V SS ESt St/GT IRQ/CP DS/RD CS R/W /WR RS0 ∑ D/A Converters Row and Column Counters Transmit Data Register Data Bus Buffer Tone Burst Gating Cct. Oscillator Circuit Bias Circuit Control Logic Digital Algorithm and Code Converter Control Logic Steering Logic Status Register Control Register A Control Register B Receive Data Register Interrupt Logic I/O ControlLow Group Filter High Group Filter Dial Tone Filter PWDN ISSUE 1 May 1995 MT8885 Integrated DTMF Transceiver with Power Down & Adaptive Micro Interface

Ordering Information

MT8885AE 24 Pin Plastic DIP MT8885AN 24 Pin SSOP MT8885AP 28 Pin PLCC -40°C to +85°C Advance Information

MT8885 Advance Information 4-52 Figure 2 - Pin Connections Pin Description Pin # Name Description24 28 11 I N + Non-inverting op-amp input. 22 I N - Inverting op-amp input. 34 G S Gain Select. Gives access to output of front end differential amplifier for connection of feedback resistor. 46 V Ref Reference Voltage output (VDD /2). 57 V SS Ground (0V). 68 O S C 1 Oscillator input. This pin can also be driven directly by an external clock. 79 O S C 2 Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes the internal oscillator circuit. Leave open circuit when OSC1 is driven externally. 10 12 TONE Output from internal DTMF transmitter. 11 13 R/W (WR ) (Motorola) Read/Write or (Intel) Write microprocessor input. CMOS compatible. 12 14 CS Chip Select input. This signal must be qualified externally by either address strobe (AS), valid memory address (VMA) or address latch enable (ALE) signal, see Figure 12. 13 15 RS0 Register Select input. Refer to Table 3 for bit interpretation. CMOS compatible. 14 17 DS (RD ) (Motorola) Data Strobe or (Intel) Read microprocessor input. Activity on this input is only required when the device is being accessed. CMOS compatible. 15 18 IRQ /CP Interrupt Request/Call Progress (open drain) output. In interrupt mode, this output goes low when a valid DTMF tone burst has been transmitted or received. In call progress mode, this pin will output a rectangular signal representative of the input signal applied at the input op-amp. The input signal must be within the bandwidth limits of the call progress filter, see Figure 8. 16 19 PWDN Power Down (input). Active High. Powers down the device and inhibits the oscillator. IRQ and TONE output are high impedance. Data bus is held in tri-state. This pin is internally pulled down. 14- 18- D0-D3 Microprocessor data bus. High impedance when CS = 1 or DS =0 (Motorola) or RD = 1 (Intel). TTL compatible. 18 22 ESt Early Steering output. Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low. 19 23 St/GT Steering Input/Guard Time output (bidirectional). A voltage greater than V TSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St. 20 24 V DD Positive power supply (5V typ.). NC 12 13 IN+ IN- GS VRef VSS OSC1 OSC2 NC TONE R/W /WR CS VDD St/GT ESt NC PWDN IRQ /CP DS/RD RS0

24 PIN DIP/SSOP

28 PIN PLCC

Table 1. Functional Encode/Decode Table continues to drive high as long as ESt remains high. delayed steering flag is active.

Advance Information MT8885 4-57 Figure 10 - Spectrum Plot Scaling Information 10 dB/Div Start Frequency = 0 Hz Stop Frequency = 3400 Hz Marker Frequency = 697 Hz and 1209 Hz The period of each tone consists of 32 equal time segments. The period of a tone is controlled by varying the length of these time segments. During write operations to the Transmit Data Register the 4 bit data on the bus is latched and converted to 2 of 8 coding for use by the programmable divider circuitry. This code is used to specify a time segment length, which will ultimately determine the frequency of the tone. When the divider reaches the appropriate count, as determined by the input code, a reset pulse is issued and the counter starts again. The number of time segments is fixed at 32, however, by varying the segment length as described above the frequency can also be varied. The divider output clocks another counter, which addresses the sinewave lookup ROM. The lookup table contains codes which are used by the switched capacitor D/A converter to obtain discrete and highly accurate DC voltage levels. Two identical circuits are employed to produce row and column tones, which are then mixed using a low noise summing amplifier. The oscillator described needs no “start-up” time as in other DTMF generators since the crystal oscillator is running continuously thus providing a high degree of tone burst accuracy. A bandwidth limiting filter is incorporated and serves to attenuate distortion products above 8 kHz. It can be seen from Figure 6 that the distortion products are very low in amplitude. Burst Mode In certain telephony applications it is required that DTMF signals being generated are of a specific duration determined either by the particular application or by any one of the exchange transmitter specifications currently existing. Standard DTMF signal timing can be accomplished by making use of the Burst Mode. The transmitter is capable of issuing symmetric bursts/pauses of predetermined duration. This burst/pause duration is 51 ms±1 ms which is a standard interval for autodialer and central office applications. After the burst/pause has been issued, the appropriate bit is set in the Status Register indicating that the transmitter is ready for more data. The timing described above is available when DTMF mode has been selected. However, when CP mode (Call Progress mode) is selected, the burst/pause duration is doubled to 102 ms ±2 ms. Note that when CP mode and Burst mode have been selected, DTMF tones may be transmitted only and not received. In applications where a non-standard burst/pause time is desirable, a software timing loop or external timer can be used to provide the timing pulses when the burst mode is disabled by enabling and disabling the transmitter. Single Tone Generation A single tone mode is available whereby individual tones from the low group or high group can be generated. This mode can be used for DTMF test equipment applications, acknowledgment tone generation and distortion measurements. Refer to Control Register B description for details.

Table 2. Actual Frequencies Versus Standard bursts with minimal error in frequency (see Table 2). harmonic components and intermodulation products. OSC2 outputs left unconnected.

• Continuous activity on DS/RD is not necessary to update the internal status registers.
• senses whether input timing is that of an Intel or Motorola controller by monitoring the DS (RD ), R/W (WR ) and CS inputs.
• generates equivalent CS signal for internal operation for all processors.
• differentiates between multiplexed and non- multiplexed microprocessor buses. Address and data are latched in accordingly.
• compatible with Motorola and Intel processors. Figure 16 shows the timing diagram for Motorola microprocessors with separate address and data buses. Members of this microprocessor family include 2 MHz versions of the MC6800, MC6802 and MC6809. For the MC6809, the chip select (CS ) input signal is formed by NANDing the (E+Q) clocks and address decode output. For the MC6800 and MC6802, CS is formed by NANDing VMA and address decode output. On the falling edge of CS, the internal logic senses the state of data strobe MT8885 OSC1 OSC2 MT8885 OSC1 OSC2 MT8885 OSC1 OSC2

3.579545 MHz

Table 3. Internal Register Functions Table 4. CRA Bit Positions Table 5. CRB Bit Positions Table 6. Control Register A Description controls all transmit tone functions. specified in the AC Electrical Characteristics for Call Progress. Note: DTMF signals cannot be detected when CP mode is selected. write cycle will be directed to control register A.

Table 7. Control Register B Description Table 8. Status Register Description b0 BURST Burst Mode Select. A logic high de-activates burst mode; a logic low enables burst mode. durations are extended from a typical duration of 51 msec to 102 msec. TOUT bit (control register A, b0). circuits. A logic high deactivates and puts both receiver circuits into power down mode. (b1) or bit two (b2) is set. read or when in non-burst mode. the absence of a DTMF signal.

MT8885 Advance Information 4-62 Figure 13 - Application Circuit (Single-Ended Input) IN+ IN- GS VRef VSS OSC1 OSC2 TONE R/W /WR CS VDD St/GT ESt IRQ /CP DS/RD RS0 DTMF/CP INPUT DTMF OUTPUT C1 R1 X-tal R L VDD To µP or µC Notes: R1, R2 = 100 kΩ 1% R3 = 374 Ω 1% R4 = 3.3 kΩ 10% R L = 10 k Ω (min.) C1 = 100 nF 5% C2 = 100 nF 5% C3 = 100 nF 10%* X-tal = 3.579545 MHz * Microprocessor based systems can inject undesirable noise into the supply rails. The performance of the MT8885 can be optimized by keeping noise on the supply rails to a minimum. The decoupling capacitor (C3) should be connected close to the device and ground loops should be avoided. MT8885 PWDNNC NCNC

Advance Information MT8885 4-63 Figure 14 - Application Notes INITIALIZATION PROCEDURE A software reset must be included at the beginning of all programs to initialize the control registers after power up. Description: Motorola Intel Data RS0 R/W WR RD b3 b2 b1 b0 1) Read Status Register 1 1 1 0 X X X X 2) Write to Control Register 1 0 0 1 0 0 0 0 3) Write to Control Register 1 0 0 1 0 0 0 0 4) Write to Control Register 1 0 0 1 1 0 0 0 5) Write to Control Register 1 0 0 1 0 0 0 0 6) Read Status Register 1 1 1 0 X X X X TYPICAL CONTROL SEQUENCE FOR BURST MODE APPLICATIONS Transmit DTMF tones of 50 ms burst/50 ms pause and Receive DTMF Tones. Sequence: RS0 R/W WR RD b3 b2 b1 b0 1) Write to Control Register A 1 0 0 1 1 1 0 1 (tone out, DTMF , IRQ, Select Control Register B) 2) Write to Control Register B 1 0 0 1 0 0 0 0 (burst mode) 3) Write to Transmit Data Register 0 0 0 1 0 1 1 1 (send a digit 7) 4) Wait for an Interrupt or Poll Status Register 5) Read the Status Register 1 1 1 0 X X X X -if bit 1 is set, the Tx is ready for the next tone, in which case ... Write to Transmit Register 0 0 0 1 0 1 0 1 (send a digit 5) -if bit 2 is set, a DTMF tone has been received, in which case .... Read the Receive Data Register 0 1 1 0 X X X X -if both bits are set ... Read the Receive Data Register 0 1 1 0 X X X X Write to Transmit Data Register 0 0 0 1 0 1 0 1 NOTE: IN THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SET UNTIL 100 ms ( ±2 ms) AFTER THE DATA IS WRITTEN TO THE TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO 200 ms (± 4 ms)

MT8885 Advance Information 4-64 * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. ‡ Typical figures are at 25 °C and for design aid only: not guaranteed and not subject to production testing. † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25 °C, VDD =5V and for design aid only: not guaranteed and not subject to production testing. * See “Notes” following AC Electrical Characteristics Tables. Absolute Maximum Ratings* Parameter Symbol Min Max Units

1 Power supply voltage VDD -VSS VDD 6V

2 Voltage on any pin V I VSS -0.3 V DD +0.3 V

3 Current at any pin (Except VDD and VSS )1 0 m A

4 Storage temperature T ST -65 +150 °C

5 Package power dissipation P D 1000 mW

Recommended Operating Conditions - Voltages are with respect to ground (VSS ) unless otherwise stated. Parameter Sym Min Typ ‡ Max Units Test Conditions 1 Positive power supply V DD 4.75 5.00 5.25 V

2 Operating temperature T O -40 +85 °C

3 Crystal clock frequency f CLK 3.575965 3.579545 3.583124 MHz Characteristics Sym Min Typ ‡ Max Units Test Conditions 1 S U P Operating supply voltage V DD 4.75 5.0 5.25 V 2 Operating supply current I DD 7.0 11 mA

3 Standby supply current 25 µA PWDN= V DD

N P U T S High level input voltage (OSC1) VIHO 3.5 V Note 9*

5 Low level input voltage

(OSC1) VILO 1.5 V Note 9* 6 Steering threshold voltage V TSt 2.2 2.3 2.5 V V DD =5V O U T P U T S Low level output voltage (OSC2) V OLO 0.1 V No load Note 9*

8 High level output voltage

(OSC2) V OHO 4.9 V No load Note 9*

9 Output leakage current

(IRQ) I OZ 11 0 µAV OH =2.4 V 10 V Ref output voltage V Ref 2.4 2.5 2.6 V No load, V DD =5V 11 V Ref output resistance R OR 1.3 k Ω 12 D i g i t a l Low level input voltage V IL 0.8 V 13 High level input voltage V IH 2.0 V

14 Input leakage current I IZ 10 µAV IN=V SS to VDD

15 Data

Source current I OH -1.4 -6.6 mA V OH =2.4V 16 Sink current I OL 2.0 4.0 mA V OL =0.4V

17 ESt

Source current I OH -0.5 -3.0 mA V OH =4.6V 18 Sink current I OL 24 m A V OL =0.4V

19 IRQ /

Sink current I OL 41 6 m A V OL =0.4V

Advance Information MT8885 4-65 ‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing. † Characteristics are over recommended operating conditions (unless otherwise stated) using the test circuit shown in Figure 13. † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C, VDD = 5V, and for design aid only: not guaranteed and not subject to production testing. * *See “Notes” following AC Electrical Characteristics Tables.

Electrical Characteristics

Gain Setting Amplifier - Voltages are with respect to ground (VSS ) unless otherwise stated, VSS = 0V, VDD =5V, TO =25°C. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Input leakage current I IN ±100 nA V SS ≤ VIN ≤ VDD

2 Input resistance R IN 10 M Ω

3 Input offset voltage V OS 25 mV

4 Power supply rejection PSRR 60 dB 1 kHz

5 Common mode rejection CMRR 60 dB 0.75 ≤ V IN ≤ 4.25V

6 DC open loop voltage gain A VOL 65 dB

7 Unity gain bandwidth BW 1.5 MHz

8 Output voltage swing V

O 4.5 V pp R L ≥ 100 kΩ to VSS

9 Allowable capacitive load (GS) C L 100 pF

10 Allowable resistive load (GS) R L 50 k Ω

11 Common mode range V CM 3.0 V pp No Load Characteristics Sym Min Typ ‡ Max Units Notes* 1 R X Valid input signal levels (each tone of composite signal) 27.5 869 mV RMS 1,2,3,5,6 Characteristics Sym Min Typ ‡ Max Units Notes* R X Positive twist accept 8 dB 2,3,6,9

2 Negative twist accept 8 dB 2,3,6,9

3 Freq. deviation accept ±1.5%± 2Hz 2,3,5 4 Freq. deviation reject ±3.5% 2,3,5

5 Third tone tolerance -16 dB 2,3,4,5,9,10

6 Noise tolerance -12 dB 2,3,4,5,7,9,10

7 Dial tone tolerance 22 dB 2,3,4,5,8,9

MT8885 Advance Information 4-66 † Characteristics are over recommended operating conditions unless otherwise stated ‡ Typical figures are at 25°C, VDD =5V, and for design aid only: not guaranteed and not subject to production testing † Characteristics are over recommended operating conditions unless otherwise stated ‡ Typical figures are at 25°C, VDD =5V, and for design aid only: not guaranteed and not subject to production testing † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing. Characteristics Sym Min Typ ‡ Max Units Conditions

1 Accept Bandwidth f A 310 500 Hz @ -25 dBm,

2 Lower freq. (REJECT) f LR 290 Hz @ -25 dBm 3 Upper freq. (REJECT) f HR 540 Hz @ -25 dBm

4 Call progress tone detect level (total

power) -30 dBm values are user selectable as per Figures 5, 6 and 7. Characteristics Sym Min Typ ‡ Max Units Conditions

1 Minimum tone accept duration t REC 40 ms

2 Maximum tone reject duration t REC 20 ms

3 Minimum interdigit pause duration t ID 40 ms

4 Maximum tone drop-out duration t OD 20 ms

Characteristics Sym Min Typ ‡ Max Units Conditions 1 T O N E I N Tone present detect time t DP 3 11 14 ms Note 11 2 Tone absent detect time t DA 0.5 4 8.5 ms Note 11

3 Delay St to b3 t PStb3 13 µs See Figure 7

4 Delay St to RX 0-RX3 tPStRX 8 µs See Figure 7

T O N E O U T Tone burst duration t BST 50 52 ms DTMF mode

6 Tone pause duration t PS 50 52 ms DTMF mode

7 Tone burst duration (extended) t BSTE 100 104 ms Call Progress mode

8 Tone pause duration (extended) t PSE 100 104 ms Call Progress mode

9 High group output level V HOUT -6.1 -2.1 dBm R L=10kΩ 10 Low group output level V LOUT -8.1 -4.1 dBm R L=10kΩ

11 Pre-emphasis dBP 0 2 3 dB R L=10kΩ

12 Output distortion (Single Tone) THD -35 dB 25 kHz Bandwidth

L=10kΩ 14 Frequency deviation f D ±0.7 ±1.5 % f C =3.579545 MHz

15 Output load resistance R LT 10 50 k Ω

X T A L Crystal/clock frequency f C 3.5759 3.5795 3.5831 MHz 17 Clock input rise and fall time t CLRF 110 ns Ext. clock 18 Clock input duty cycle DC CL 40 50 60 % Ext. clock

19 Capacitive load (OSC2) C LO 30 pF

Advance Information MT8885 4-67 † Characteristics are over recommended operating conditions unless otherwise stated ‡ Typical figures are at 25°C, VDD =5V, and for design aid only: not guaranteed and not subject to production testing NOTES: 1) dBm=decibels above or below a reference power of 1 mW into a 600 ohm load. 2) Digit sequence consists of all 16 DTMF tones. 3) T one duration=40 ms. T one pause=40 ms. 4) Nominal DTMF frequencies are used. 5) Both tones in the composite signal have an equal amplitude. 6) The tone pair is deviated by ± 1.5 %±2 Hz. 7) Bandwidth limited (3 kHz) Gaussian noise. 8) The precise dial tone frequencies are 350 and 440 Hz (±2 %). 9) Guaranteed by design and characterization. Not subject to production testing. 10) Referenced to the lowest amplitude tone in the DTMF signal. 11) For guard time calculation purposes. Figure 15 - DS/RD/WR Clock Pulse Characteristics Sym Min Typ ‡ Max Units Conditions 1D S / R D/WR clock frequency f CYC 4.0 MHz Figure 15 2D S / R D/WR cycle period t CYC 250 ns Figure 15 3D S / R D/WR low pulse width t CL 150 ns Figure 15 4D S / R D/WR high pulse width t CH 100 ns Figure 15 5D S / R D/WR rise and fall time t R,tF 20 ns Figure 15 6R / W setup time t RWS 23 ns Figures 16 & 17 7R / W hold time t RWH 20 ns Figures 16 & 17

8 Address setup time (RS0) t AS 0 ns Figures 16 - 19

9 Address hold time (RS0) t AH 40 20 ns Figures 16 - 19

10 Data hold time (read) t DHR 22 ns Figures 16 - 19

11 DS/RD to valid data delay (read) tDDR 100 ns Figures 16 - 19

12 Data setup time (write) t DSW 45 ns Figures 16 - 19

13 Data hold time (write) t DHW 10 ns Figures 16 - 19

14 Chip select setup time t CSS 45 35 ns Figures 16 - 19

15 Chip select hold time t CSH 40 ns Figures 16 - 19

16 Input Capacitance (data bus) C IN 5p F

17 Output Capacitance (IRQ/CP) C OUT 5p F

MT8885 Advance Information 4-70 NOTES: