MT8880

MT8880C MITEL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 18

Technical content

Features

• Complete DTMF transmitter/receiver
• Central office quality
• Low power consumption
• Microprocessor port
• Adjustable guard time
• Automatic tone burst mode
• Call progress mode

Applications

• Credit card systems
• Paging systems
• Repeater systems/mobile radio
• Interconnect dialers
• Personal computers

Description

The MT8880C/C-1 is a monolithic DTMF transceiver with call progress filter. It is fabricated in Mitel’s ISO 2-CMOS technology, which provides low power dissipation and high reliability. The DTMF receiver is based upon the industry standard MT8870 monolithic DTMF receiver; the transmitter utilizes a switched capacitor D/A converter for low distortion, high accuracy DTMF signalling. Internal counters provide a burst mode such that tone bursts can be transmitted with precise timing. A call progress filter can be selected allowing a microprocessor to analyze call progress tones. A standard microprocessor bus is provided and is directly compatible with 6800 series microprocessors. The MT8880C-1 is functionally identical to the MT8880C except for the performance of the receiver section, which is enhanced to accept and reject lower signal levels.

Ordering Information

MT8880CE/CE-1 20 Pin Plastic DIP MT8880CC/CC-1 20 Pin Ceramic DIP MT8880CS/CS-1 20 Pin SOIC MT8880CN/CN-1 24 Pin SSOP MT8880CP/CP-1 28 Pin Plastic LCC -40°C to +85°C Figure 1 - Functional Block Diagram TONE IN+ IN- GS OSC1 OSC2 VDD V Ref VSS ESt St/GT IRQ/CP Φ 2 CS R/W RS0 ∑ D/A Converters Row and Column Counters Transmit Data Register Data Bus Buffer Tone Burst Gating Cct. Oscillator Circuit Bias Circuit Control Logic Digital Algorithm and Code Converter Control Logic Steering Logic Status Register Control Register A Control Register B Receive Data Register Interrupt Logic I/O ControlLow Group Filter High Group Filter Dial Tone Filter ISSUE 2 May 1995 ISO2-CMOS

MT8880C/MT8880C-1 ISO2-CMOS 4-34 Figure 2 - Pin Connections Pin Description Pin # Name Description20 24 28 1 1 1 IN+ Non-inverting op-amp input. 2 2 2 IN- Inverting op-amp input. 334 G S Gain Select. Gives access to output of front end differential amplifier for connection of feedback resistor. 446V Ref Reference Voltage output, nominally VDD /2 is used to bias inputs at mid-rail (see Fig. 13). 557V SS Ground input (0V). 6 6 8 OSC1 DTMF clock/oscillator input. 7 7 9 OSC2 Clock output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes the internal oscillator circuit. Leave open circuit when OSC1 is clock input. 81 0 1 2 T O N ETone output (DTMF or single tone). 91 1 1 3R / W Read/Write input. Controls the direction of data transfer to and from the MPU and the transceiver registers. TTL compatible. 10 12 14 CS Chip Select, TTL input (CS=0 to select the chip). 11 13 15 RS0 Register Select input. See register decode table. TTL compatible. 12 14 17 Φ 2 System Clock input. TTL compatible. N.B. Φ 2 clock input need not be active when the device is not being accessed. 13 15 18 IRQ / CP Interrupt Request to MPU (open drain output). Also, when call progress (CP) mode has been selected and interrupt enabled the IRQ/CP pin will output a rectangular wave signal representative of the input signal applied at the input op-amp. The input signal must be within the bandwidth limits of the call progress filter. See Figure 8. 14- 18- 19- D0-D3 Microprocessor Data Bus (TTL compatible). High impedance when CS = 1 or Φ 2 is low. 18 22 26 ESt Early Steering output. Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low. 19 23 27 St/GT Steering Input/Guard Time output (bidirectional). A voltage greater than VTSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St. 20 24 28 V DD Positive power supply input (+5V typical). 8,9 16, 3,5, 10, 11, 16, 23- NC No Connection. 10 11 IN+ IN- GS VRef VSS OSC1 OSC2 TONE R/W CS VDD St/GT ESt IRQ /CP Φ 2 RS0

20 PIN CERDIP/PLASTIC DIP/SOIC 28 PIN PLCC

/CP Φ 2 RS0

24 PIN SSOP

ISO2-CMOS MT8880C/MT8880C-1 4-39 Burst Mode In certain telephony applications it is required that DTMF signals being generated are of a specific duration determined either by the particular application or by any one of the exchange transmitter specifications currently existing. Standard DTMF signal timing can be accomplished by making use of the Burst Mode. The transmitter is capable of issuing symmetric bursts/pauses of predetermined duration. This burst/pause duration is 51 ms±1 ms which is a standard interval for autodialer and central office applications. After the burst/pause has been issued, the appropriate bit is set in the Status Register indicating that the transmitter is ready for more data. The timing described above is available when DTMF mode has been selected. However, when CP mode (Call Progress mode) is selected, a second burst/ pause time of 102 ms ±2 ms is available. This extended interval is useful when precise tone bursts of longer than 51 ms duration and 51 ms pause are desired. Note that when CP mode and Burst mode have been selected, DTMF tones may be transmitted only and not received. In applications where a non-standard burst/pause duration is required, burst mode must be disabled and the transmitter gated on and off by an external hardware or software timer. Single Tone Generation A single tone mode is available whereby individual tones from the low group or high group can be generated. This mode can be used for DTMF test equipment applications, acknowledgment tone generation and distortion measurements. Refer to Control Register B description for details. Distortion Calculations The MT8880C/C-1 is capable of producing precise tone bursts with minimal error in frequency (see T able 1). The internal summing amplifier is followed by a first-order lowpass switched capacitor filter to minimize harmonic components and intermodulation products. The total harmonic distortion for a single tone can be calculated using Equation 1, which is the ratio of the total power of all the extraneous frequencies to the power of the fundamental frequency expressed as a percentage. The Fourier components of the tone output correspond to V 2f.... Vnf as measured on the output waveform. The total harmonic distortion for a dual tone can be calculated Figure 11 - Description of Timing Events EXPLANATION OF EVENTS A) TONE BURSTS DETECTED, TONE DURATION INVALID, RX DATA REGISTER NOT UPDATED. B) TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER. C) END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER RETAINED UNTIL NEXT VALID TONE PAIR. D) TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER. E) ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, DATA REMAINS UNCHANGED. F) END OF TONE #n+1 DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER RETAINED UNTIL NEXT VALID TONE PAIR. EXPLANATION OF SYMBOLS V in DTMF COMPOSITE INPUT SIGNAL. ESt EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES. St/GT STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT. RX 0-RX 3 4-BIT DECODED DATA IN RECEIVE DATA REGISTER b3 DELAYED STEERING. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. ACTIVE LOW FOR THE DURATION OF A VALID DTMF SIGNAL. b2 INDICATES THAT VALID DATA IS IN THE RECEIVE DATA REGISTER. THE BIT IS CLEARED AFTER THE STATUS REGISTER IS READ. IRQ /CP INTERRUPT IS ACTIVE INDICATING THAT NEW DATA IS IN THE RX DATA REGISTER. THE INTERRUPT IS CLEARED AFTER THE STATUS REGISTER IS READ. tREC MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID. tREC MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION. tID MINIMUM TIME BETWEEN VALID SEQUENTIAL DTMF SIGNALS. tDO MAXIMUM ALLOWABLE DROPOUT DURING VALID DTMF SIGNAL. tDP TIME TO DETECT VALID FREQUENCIES PRESENT. tDA TIME TO DETECT VALID FREQUENCIES ABSENT. tGTP GUARD TIME, TONE PRESENT. tGTA GUARD TIME, TONE ABSENT.

Table 1. Actual Frequencies Versus Standard addition of a standard television colour burst crystal. OSC2 outputs left unconnected. associated with data transfer operations. as such requires a pull-up resistor (see Figure 13).

3.579545 MHz

Table 2. Internal Register Functions Table 3. CRA Bit Positions Table 4. CRB Bit Positions Table 5. Control Register A Description implemented in either the burst mode or non-burst mode. decoded when the CP mode of operation has been selected. Control Register are directed back to Control Register A.

Table 6. Control Register B Description Table 7. Status Register Description burst of a specific duration (see AC Characteristics). Subsequently, a pause of the same duration is induced. selected (CRA b1=0) before test mode can be implemented. ‘1’ will select column frequencies. read or when in non-burst mode.

ISO2-CMOS MT8880C/MT8880C-1 4-43 Figure 13 - Application Circuit (Single-Ended Input) Figure 14 - Test Circuit IN+ IN- GS VRef VSS OSC1 OSC2 TONE R/W CS VDD St/GT ESt IRQ /CP Φ 2 RS0 DTMF/CP INPUT DTMF OUTPUT C1 R1 X-tal C4 R L VDD To µP or µC Notes: R1, R2 = 100 kΩ 1% R3 = 374 Ω 1% R4 = 3.3 kΩ 10% R L = 10 k Ω (min.) C1 = 100 nF 5% C2 = 100 nF 5% C3 = 100 nF 10%* C4 = 10 nF 10% X-tal = 3.579545 MHz * Microprocessor based systems can inject undesirable noise into the supply rails. The performance of the MT8880 can be optimized by keeping noise on the supply rails to a minimum. The decoupling capacitor (C3) should be connected close to the device and ground loops should be avoided. MT8880C/C-1 TEST POINT MMD6150 (or equivalent)

5.0 VDC

2.4 kΩ 24 kΩ130 pF MMD7000 (or equivalent) TEST POINT 3 kΩ 70 pF Test load for IRQ/CP pinTest load for D0-D3 pins

MT8880C/MT8880C-1 ISO2-CMOS 4-44 Figure 15 - MT8880C/C-1 to 6802 Interface Figure 16 - Application Hints IRQ Address VMA R/W E Data Peripheral decode +5V 3.3k IRQ RS0 CS R/W Φ 2 Data

6802 MT8880C/C-1

EXAMPLE 1: A software reset must be included at the beginning of all programs to initialize the control registers after power up. The initialization procedure should be implemented 100ms after power up. Description Control Data CS RS0 R/W b3 b2 b1 b0 1) Read Status Register 0 1 1 X X X X 2) Write to Control Register 0 1 0 0 0 0 0 3) Write to Control Register 0 1 0 0 0 0 0 4) Write to Control Register 0 1 0 1 0 0 0 5) Write to Control Register 0 1 0 0 0 0 0 6) Read Status Register 0 1 1 X X X X EXAMPLE 2: Transmit DTMF tones of 50 ms burst/50 ms pause and Receive DTMF Tones 1) Write to Control Register A 0 1 0 1 1 0 1 (tone out, DTMF , IRQ, Select Control Register B) 2) Write to Control Register B 0 1 0 0 0 0 0 (burst mode) 3) Write to Transmit Data Register 0 0 0 0 1 1 1 (send a digit 7) 4) Read the Status Register 0 1 1 X X X X -if bit 1 is set, the Tx is ready for the next tone, in which case... Write to Transmit Register 0 0 0 0 1 0 1 (send a digit 5) -if bit 2 is set, a DTMF tone has been received, in which case.... Read the Receive Data Register 0 0 1 X X X X -if both bits are set... Read the Receive Data Register 0 0 1 X X X X Write to Transmit Data Register 0 0 0 0 1 0 1 NOTE: IN THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SET UNTIL 100 ms (±2 ms) AFTER THE DATA IS WRITTEN TO THE TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO 200 ms (± 4 ms) .

ISO2-CMOS MT8880C/MT8880C-1 4-45 * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. ‡ Typical figures are at 25 °C and for design aid only: not guaranteed and not subject to production testing. † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25 °C, VDD =5V and for design aid only: not guaranteed and not subject to production testing. Absolute Maximum Ratings* Parameter Symbol Min Max Units

1 Power supply voltage VDD -VSS VDD 6V

2 Voltage on any pin V I VSS -0.3 V DD +0.3 V

3 Current at any pin (Except VDD and VSS )1 0 m A

4 Storage temperature T ST -65 +150 °C

5 Package power dissipation P D 1000 mW

Recommended Operating Conditions - Voltages are with respect to ground (VSS ) unless otherwise stated. Parameter Sym Min Typ ‡ Max Units Test Conditions 1 Positive power supply V DD 4.75 5.00 5.25 V

2 Operating temperature T O -40 +85 °C

3 Crystal clock frequency f CLK 3.575965 3.579545 3.583124 MHz Characteristics Sym Min Typ ‡ Max Units Test Conditions 1 S U P Operating supply voltage V DD 4.75 5.0 5.25 V 2 Operating supply current I DD 7.0 11 mA 3 Power consumption P C 57.8 mW 4 I N P U T S High level input voltage (OSC1) VIHO 3.5 V

5 Low level input voltage

(OSC1) VILO 1.5 V 6 Steering threshold voltage V TSt 2.2 2.3 2.5 V V DD =5V O U T P U T S Low level output voltage (OSC2) V OLO 0.1 V No load

8 High level output voltage

(OSC2) V OHO 4.9 V No load VDD =5 V

9 Output leakage current

(IRQ) I OZ 11 0 µAV OH =2.4 V 10 V Ref output voltage V Ref 2.4 2.5 2.6 V No load, V DD =5V 11 V Ref output resistance R OR 1.3 k Ω 12 D i g i t a l Low level input voltage V IL 0.8 V 13 High level input voltage V IH 2.0 V

14 Input leakage current I IZ 10 µAV IN=V SS to VDD

15 Data

Source current I OH -1.4 -6.6 mA V OH =2.4V 16 Sink current I OL 2.0 4.0 mA V OL =0.4V

17 ESt

Source current I OH -0.5 -3.0 mA V OH =4.6V 18 Sink current I OL 24 m A V OL =0.4V

19 IRQ/

Sink current I OL 41 6 m A V OL =0.4V

MT8880C/MT8880C-1 ISO2-CMOS 4-46 ‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing. † Characteristics are over recommended temperature and at VDD =5V, using the test circuit shown in Figure 13. † Characteristics are over recommended operating conditions (unless otherwise stated) using the test circuit shown in Figure 13. † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C, VDD = 5V, and for design aid only: not guaranteed and not subject to production testing. * See “Notes” following AC Electrical Characteristics Tables.

Electrical Characteristics

Gain Setting Amplifier - Voltages are with respect to ground (VSS ) unless otherwise stated, VSS = 0 V, VDD =5V, TO =25°C. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Input leakage current I IN ±100 nA V SS ≤ VIN ≤ VDD

2 Input resistance R IN 10 M Ω

3 Input offset voltage V OS 25 mV

4 Power supply rejection PSRR 60 dB 1 kHz

5 Common mode rejection CMRR 60 dB 0.75V ≤ V IN ≤ 4.25V

6 DC open loop voltage gain A VOL 65 dB

7 Unity gain bandwidth BW 1.5 MHz

8 Output voltage swing V

O 4.5 V pp R L ≥ 100 kΩ to VSS

9 Allowable capacitive load (GS) C L 100 pF

10 Allowable resistive load (GS) R L 50 k Ω

11 Common mode range V CM 3.0 V pp No Load Characteristics Sym Min Typ Max Units Notes* R X Valid input signal levels (each tone of composite signal) 21.8 mV RMS 1,2,3,5,6,9 +1 dBm 1,2,3,5,6,9 869 mV RMS 1,2,3,5,6,9

2 Input Signal Level Reject -37 dBm 1,2,3,5,6,9

Characteristics Sym Min Typ ‡ Max Units Notes* 1 R X Valid Input signal levels (each tone of composite signal) +1 dBm 1,2,3,5,6,9 869 mV RMS 1,2,3,5,6,9 Characteristics Sym Min Typ ‡ Max Units Notes* R X Positive twist accept 8 dB 2,3,6,9

2 Negative twist accept 8 dB 2,3,6,9

3 Freq. deviation accept ±1.5%±2Hz 2,3,5,9 4 Freq. deviation reject ±3.5% 2,3,5

5 Third tone tolerance -16 dB 2,3,4,5,9,10

6 Noise tolerance -12 dB 2,3,4,5,7,9,10

7 Dial tone tolerance 22 dB 2,3,4,5,8,9,11

ISO2-CMOS MT8880C/MT8880C-1 4-47 † Characteristics are over recommended operating conditions unless otherwise stated ‡ Typical figures are at 25°C, VDD = 5V, and for design aid only: not guaranteed and not subject to production testing * See “Notes” AC Electrical Characteristics Tables Characteristics Sym Min Typ ‡ Max Units Notes* 1 Lower freq. (ACCEPT) f LA 320 Hz @ -25 dBm 2 Upper freq. (ACCEPT) f HA 510 Hz @ -25 dBm 3 Lower freq. (REJECT) f LR 290 Hz @ -25 dBm 4 Upper freq. (REJECT) f HR 540 Hz @ -25 dBm

5 Call progress tone detect level

(total power) -30 dBm Characteristics Sym Min Typ ‡ Max Units Conditions R X Tone present detect time t DP 3 1 11 4m s N o t e 1 2 2 Tone absent detect time t DA 0.5 4 8.5 ms Note 12

3 Tone duration accept t REC 40 ms User adjustable #

4 Tone duration reject t REC 20 ms User adjustable #

5 Interdigit pause accept t ID 40 ms User adjustable #

6 Interdigit pause reject t DO 20 ms User adjustable #

7 Delay St to b3 t PStb3 13 µs

8 Delay St to RX 0-RX3 tPStRX 8 µs

T X Tone burst duration t BST 50 52 ms DTMF mode

10 Tone pause duration t PS 50 52 ms DTMF mode

11 Tone burst duration (extended) t BSTE 100 104 ms Call Progress mode

12 Tone pause duration (extended) t PSE 100 104 ms Call Progress mode

T O N E O U T High group output level V HOUT -6.1 -2.1 dBm R L=10kΩ 14 Low group output level V LOUT -8.1 -4.1 dBm R L=10kΩ

15 Pre-emphasis dB P 23 d B R L=10kΩ

16 Output distortion (Single Tone) THD -35 dB 25 kHz Bandwidth

R L=10kΩ 17 Frequency deviation f D ±0.7 ±1.5 % f C =3.579545 MHz

18 Output load resistance R LT 10 50 k Ω

M P U I N T E R F A C E Φ 2 cycle period t CYC 250 ns 20 Φ 2 high pulse width t CH 115 ns 21 Φ 2 low pulse width t CL 110 ns 22 Φ 2 rise and fall time tR, tF 25 ns

23 Address, R/W hold time t AH,tRWH 26 ns

24 Address, R/W setup time (before Φ 2) tAS,tRWS 23 ns

25 Data hold time (read) t DHR 22 ns *

26 Φ 2 to valid data delay (read) t DDR 100 ns 200 pF load

27 Data setup time (write) t DSW 45 ns

MT8880C/MT8880C-1 ISO2-CMOS 4-48 † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing. * The data bus output buffers are no longer sourcing or sinking current by tDHR . # See Figure 6 regarding guard time adjustment. NOTES: 1) dBm=decibels above or below a reference power of 1 mW into a 600 ohm load. 2) Digit sequence consists of all 16 DTMF tones. 3) T one duration=40 ms. T one pause=40 ms. 4) Nominal DTMF frequencies are used. 5) Both tones in the composite signal have an equal amplitude. 6) The tone pair is deviated by ±1.5%±2 Hz. 7) Bandwidth limited (3 kHz) Gaussian noise. 8) The precise dial tone frequencies are 350 and 440 Hz (±2%). 9) For an error rate of less than 1 in 10,000. 10) Referenced to the lowest amplitude tone in the DTMF signal. 11) Referenced to the minimum valid accept level. 12) For guard time calculation purposes. Characteristics Sym Min Typ ‡ Max Units Notes*

28 Data hold time (write) t DHW 10 ns

29 Input Capacitance (data bus) C IN 5p F

30 Output Capacitance (IRQ /CP) C OUT 5p F

T M F C L K Crystal/clock frequency f C 3.5759 3.5795 3.5831 MHz 32 Clock input rise time t LHCL 110 ns Ext. clock 33 Clock input duty cycle t HLCL 110 ns Ext. clock 34 Clock input duty cycle DC CL 40 50 60 % Ext. clock

35 Capacitive load (OSC2) C LO 30 pF

MT8880C/MT8880C-1 ISO2-CMOS 4-50 NOTES: