MT8816 ZARLINK | Alldatasheet

Document overview

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Technical content

Features

  • Internal control latches and address decoder
  • Short set-up and hold times
  • Wide operating voltage: 4.5 V to 13.2 V
  • 12Vpp analog signal capability ON 65 Ω max. @ VDD = 12 V, 25°C
  • ∆RON ≤10 Ω @ VDD = 12 V, 25°C
  • Full CMOS switch for low distortion
  • Minimum feedthrough and crosstalk
  • Separate analog and digital reference supplies
  • Low power consumption ISO-CMOS technology

Applications

  • Key systems
  • PBX systems
  • Mobile radio
  • Test equipment/instrumentation
  • Analog/digital multiplexers
  • Audio/Video switching

Description

The Zarlink MT8816 is fabricated in Zarlink’s ISO- CMOS technology providing low power dissipation and high reliability. The device contains a 8 x 16 array of crosspoint switches along with a 7 to 128 line decoder and latch circuits. Any one of the 128 switches can be addressed by selecting the appropriate seven address bits. The selected switch can be turned on or off by applying a logical one or zero to the DATA input. V SS is the ground reference of the digital inputs. The range of the analog signal is from V DD to VEE. Chip Select (CS) allows the crosspoint array to be cascaded for matrix expansion. February 2005

Ordering Information

MT8816AE 40 Pin PDIP Tubes MT8816AP 44 Pin PLCC Tubes MT8816APR 44 Pin PLCC Tape & Reel MT8816AP1 44 Pin PLCC* Tubes MT8816APR1 44 Pin PLCC* Tape & Reel MT8816AE1 40 Pin PDIP* Tubes * Pb Free Matte Tin -40°C to +85 °C MT8816 ISO-CMOS 8 x 16 Analog Switch Array Data Sheet Figure 1 - Functional Block Diagram 7 to 128 Decoder Latches 8 x 16 Switch Array CS STROBE DATA RESET VDD VEE VSS Xi I/O (i=0-15) Yi I/O (i=0-7) 128128 AX0 AX1 AY0 AY1 AY2 AX2 AX3

Zarlink Semiconductor Inc. Figure 2 - Pin Connections Pin Description Pin # Name Description PDIP PLCC 11Y 3 Y3 Analog (Input/Output): this is connected to the Y3 column of the switch array. 22 A Y 2 Y2 Address Line (Input). 3 3 RESET Master RESET (Input): this is used to turn off all switches regardless of the condition of CS. Active High. 4,5 4,5 AX3,AX0 X3 and X0 Address Lines (Inputs). 6,7 7,8 X14, X15 X14 and X15 Analog (Inputs/Outputs): these are connected to the X14 and X15 rows of the switch array. 8-13 9-14 X6-X11 X6-X11 Analog (Inputs/Outputs): these are connected to the X6-X11 rows of the switch array. 14 6,15,16 NC No Connection 15 17 Y7 Y7 Analog (Input/Output): this is connected to the Y7 column of the switch array. 16 18 V SS Digital Ground Reference. 17 19 Y6 Y6 Analog (Input/Output): this is connected to the Y6 column of the switch array. 18 20 STROBE STROBE (Input): enables function selected by address and data. Address must be stable before STROBE goes high and DATA must be stable on the falling edge of the STROBE. Active High. 19 21 Y5 Y5 Analog (Input/Output): this is connected to the Y5 column of the switch array. 20 22 V EE Negative Power Supply. 21 23 Y4 Y4 Analog (Input/Output): this is connected to the Y4 column of the switch array. 22, 23 24,25 AX1,AX2 X1 and X2 Address Lines (Inputs).

40 PIN PLASTIC DIP 44 PIN PLCC

2318 19 20 21 22 24 25 26 27 28 17 29 NC X12 X13 NC CS DATA VDD AY2 RESET AX3 AX0 NC

Zarlink Semiconductor Inc. 24, 25 26,27 AY0,AY1 Y0 and Y1 Address Lines (Inputs). 26, 27 30,31 X13, X12 X13 and X12 Analog (Inputs/Outputs): these are connected to the X13 and X12 rows of the switch array. 28 - 33 32-37 X5-X0 X5-X0 Analog (Inputs/Outputs): these are connected to the X5-X0 rows of the switch array. 34 28,29, NC No Connection. 35 39 Y0 Y0 Analog (Input/Output): this is connected to the Y0 column of the switch array. 36 40 CS Chip Select (Input): this is used to select the device. Active High. 37 41 Y1 Y1 Analog (Input/Output): this is connected to the Y1 column of the switch array. 38 42 DATA DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off the selected switch. Active High. 39 43 Y2 Y2 Analog (Input/Output): this is connected to the Y2 column of the switch array. 40 44 V DD Positive Power Supply. Pin Description (continued) Pin # Name Description PDIP PLCC

Zarlink Semiconductor Inc. Functional Description The MT8816 is an analog switch matrix with an array size of 8 x 16. The switch array is arranged such that there are 8 columns by 16 rows. The columns are referred to as the Y inputs/outputs and the rows are the X inputs/outputs. The crosspoint analog switch array will interconnect any X I/O with any Y I/O when turned on and provide a high degree of isolation when turned off. The c ontrol memory consists of a 128 bit write only RAM in which the bits are selected by the address inputs (AY0-AY2 , AX0-AX3). Data is presented to the memory on the DATA input. Data is asynchronously written into memory whenever both the CS (Chip Select) and STROBE inputs are high and are latched on the falling edge of STROBE. A logical “1” written into a memory cell turns the corresponding crosspoint switch on and a logical “0” tu rns the crosspoint off. Only the crosspoint switches corresponding to the addressed memory location are altered when data is written into memory. The remaining switches retain their previous states. Any combinat ion of X and Y inputs/outputs can be interconnected by establishing appropriate patterns in the control memory. A logical “1” on the RESET input will asynchronously return all memory locations to logical “0” turning off all crosspoint switches regardless of whether CS is high or low. Two voltage reference pins (V SS and V EE) are provided for the MT8816 to enable switching of negative analog signals. The range for digital signals is from VDD to VSS while the range for analog signals is from VDD to VEE. VSS and VEE pins can be tied together if a single voltage reference is needed. Address Decode The seven address inputs along with the STROBE and CS (Chip Select) are logically ANDed to form an enable signal for the resettable transparent latches. The DATA input is buffered and is used as the input to all latches. To write to a location, RESET must be low and CS must go high while the address and data are set up. Then the STROBE input is set high and then low causing the data to be latched. The data can be changed while STROBE is high, however, the corresponding switch will turn on and off in accordance with the DATA input. DATA must be stable on the falling edge of STROBE in order for correct data to be written to the latch.

Zarlink Semiconductor Inc. * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. † DC Electrical Characteristics are over recommended temperature range. ‡ Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. Absolute Maximum Ratings*- Voltages are with respect to VEE unless otherwise stated. Parameter Symbol Min. Max. Units

1 Supply Voltage V DD

-0.3 -0.3 16.0 VDD+0.3 V V 2 Analog Input Voltage V INA -0.3 V DD+0.3 V 3 Digital Input Voltage V IN VSS-0.3 V DD+0.3 V

4 Current on any I/O Pin I ±15 mA

5 Storage Temperature T S -65 +150 °C

6 Package Power Dissipation PLASTIC DIP P D 0.6 W Recommended Operating Conditions - Voltages are with respect to VEE unless otherwise stated. Characteristics Sym. Min. Typ. Max. Units Test Conditions

1 Operating Temperature T O -40 25 85 °C

2 Supply Voltage V DD

4.5 VEE 13.2 VDD-4.5 V V

3 Analog Input Voltage V INA VEE VDD V

4 Digital Input Voltage V IN VSS VDD V

Characteristics Sym. Min. Typ. ‡ Max. Units Test Conditions

1 Quiescent Supply Current I DD 1 100 µA All digital inputs at V IN=VSS or

0.4 1.5 mA All digital inputs at V IN=2.4V + VSS; VSS=7.0 V 5 15 mA All digital inputs at V IN=3.4 V

2 Off-state Leakage Current

(See G.9 in Appendix) IOFF ±1 ±500 nA IV Xi - VYjI = VDD - VEE See Appendix, Fig. A.1 3 Input Logic “0” level V IL 0.8+VS S VV SS=7.5V; VEE=0 V 4 Input Logic “1” level V IH 2.0+VSS VV SS=6.5V; VEE=0 V 5 Input Logic “1” level V IH 3.3 V 6 Input Leakage (digital pins) I LEAK 0.1 10 µA All digital inputs at V IN = VSS or VDD

Zarlink Semiconductor Inc. † Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details. ‡ Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. Crosstalk measurements are for Plastic DIPS only, crosstalk values for PLCC packages are approximately 5 dB better. Characteristics Sym. 25 °C7 0 °C8 5 °C Units Test Conditions

1 On-state V DD=12V

Resistance V DD=10V VDD= 5V (See G.1, G.2, G.3 in Appendix) R ON 45 120 185 215 225 Ω Ω Ω VSS=VEE=0 V,VDC=VDD/2, IVXi-VYjI = 0.4 V See Appendix, Fig. A.2

2 Difference in on-state

(See G.4 in Appendix) ON 51 0 1 0 1 0 Ω VDD=12V, VSS=VEE=0, VDC=VDD/2, IVXi-VYjI = 0.4 V See Appendix, Fig. A.2 otherwise stated. Characteristics Sym. Min. Typ. ‡ Max. Units Test Conditions

1 Switch I/O Capacitance C S 20 pF f=1 MHz

2 Feedthrough Capacitance C F 0.2 pF f=1 MHz

3 Frequency Response

Channel “ON” 20LOG(VOUT/VXi)=-3 dB F3dB 45 MHz Switch is “ON”; V INA = 2Vpp sinewave; RL = 1 kΩ See Appendix, Fig. A.3

4 Total Harmonic Distortion

(See G.5, G.6 in Appendix) THD 0.01 % Switch is “ON”; V INA = 2Vpp sinewave f= 1 kHz; RL=1 kΩ

5 Feedthrough

Channel “OFF” Feed.=20LOG (VOUT/VXi) (See G.8 in Appendix) FDT -95 dB All Switches “OFF”; V INA= 2Vpp sinewave f= 1 kHz; RL= 1 kΩ. See Appendix, Fig. A.4

6 Crosstalk between any two

channels for switches Xi-Yi and Xj-Yj. Xtalk=20LOG (V Yj/VXi). (See G.7 in Appendix). Xtalk -45 dB V INA=2Vpp sinewave f= 10 MHz; RL = 75 Ω. -90 dB V INA=2Vpp sinewave f= 10 kHz; RL = 600 Ω. -85 dB V INA=2Vpp sinewave f= 10 kHz; RL = 1 kΩ. -80 dB V INA=2Vpp sinewave f= 1 kHz; RL = 10 kΩ. Refer to Appendix, Fig. A.5 for test circuit.

7 Propagation delay through

t PS 30 ns R L=1 kΩ; CL=50 pF

Zarlink Semiconductor Inc. † Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details. Digital Input rise time (tr) and fall time (tf) = 5 ns. ‡ Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. ¿ Refer to Appendix, Fig. A.7 for test circuit. otherwise stated. Characteristics Sym. Min. Typ. ‡ Max. Units Test Conditions

1 Control Input crosstalk to switch

(for CS, DATA, STROBE, Address) CX talk 30 mVpp V IN=3 V squarewave; RIN=1 kΩ, RL=10 kΩ. See Appendix, Fig. A.6

2 Digital Input Capacitance C DI 10 pF f=1 MHz

3 Switching Frequency F O 20 MHz

4 Setup Time DATA to STROBE t DS 10 ns R L= 1 kΩ, CL=50 pF ¿

5 Hold Time DATA to STROBE t DH 10 ns R L= 1 kΩ, CL=50 pF ¿

6 Setup Time Address to

tAS 10 ns R L= 1 kΩ, CL= 50pF ¿

7 Hold Time Address to STROBE t AH 10 ns R L= 1 kΩ, CL=50 pF ¿

8 Setup Time CS to STROBE t CSS 10 ns R L= 1 kΩ, CL=50 pF ¿

9 Hold Time CS to STROBE t CSH 10 ns R L= 1 kΩ, CL=50 pF ¿

10 STROBE Pulse Width t SPW 20 ns R L= 1 kΩ, CL=50 pF ¿

11 RESET Pulse Width t RPW 40 ns R L= 1 kΩ, CL=50 pF ¿

12 STROBE to Switch Status Delay t S 40 100 ns R L= 1 kΩ, CL=50 pF ¿

13 DATA to Switch Status Delay t D 50 100 ns R L= 1 kΩ, CL=50 pF ¿

14 RESET to Switch Status Delay t R 35 100 ns R L= 1 kΩ, CL=50 pF ¿

Zarlink Semiconductor Inc. Figure 3 - Control Memory Timing Diagram * See Appendix, Fig. A.7 for switching waveform tCSS tCSH tRPW tSPW tAS tAH tDH tD tS tR tR tDS 50% 50% 50% 50% 50%50%50% 50% 50% 50% 50% CS RESET STROBE ADDRESS DATA SWITCH* ON OFF

Zarlink Semiconductor Inc. Table 1 - Address Decode Truth Table * Switch connections are not in ascending order AX0 AX1 AX2 AX3 AY0 AY1 AY2 Connection* X0-Y0 X1-Y0 X2-Y0 X3-Y0 X4-Y0 X5-Y0 X12-Y0 X13-Y0 X6-Y0 X7-Y0 X8-Y0 X9-Y0 X10-Y0 X11-Y0 X14-Y0 X15-Y0 X0-Y1 ↓ ↓ X15-Y1 X0-Y2 ↓ ↓ X15-Y2 X0-Y3 ↓ ↓ X15-Y3 X0-Y4 ↓ ↓ X15-Y4 X0-Y5 ↓ ↓ X15-Y5 X0-Y6 ↓ ↓ X15-Y6 X0-Y7 ↓ ↓ X15-Y7

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