MT8812 MITEL | Alldatasheet

Document overview

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Technical content

Features

  • Internal control latches and address decoder
  • Short set-up and hold times
  • Wide operating voltage: 4.5V to 14.5V
  • 14Vpp analog signal capability
  • R ON 65Ω max. @ V DD =14V, 25°C
  • Δ R ON ≤10Ω @ V DD =14V , 25°C
  • Full CMOS switch for low distortion
  • Minimum feedthrough and crosstalk
  • Low power consumption ISO-CMOS technology

Applications

  • PBX systems
  • Mobile radio
  • Test equipment /instrumentation
  • Analog/digital multiplexers
  • Audio/Video switching

Description

The Mitel MT8812 is fabricated in MITEL’s ISO- CMOS technology providing low power dissipation and high reliability. The device contains a 8 x12 array of crosspoint switches along with a 7 to 96 line decoder and latch circuits. Any one of the 96 switches can be addressed by selecting the appropriate seven input bits. The selected switch can be turned on or off by applying a logical one or zero to the DATA input.

Ordering Information

MT8812AC 40 Pin Ceramic DIP MT8812AE 40 Pin Plastic DIP MT8812AP 44 Pin PLCC 0° to 70°C Figure 1 - Functional Block Diagram 7 to 96 Decoder Latches 8 x 12 Switch Array AX0 AX1 AY0 AY1 AY2 STROBE DATA RESET VDD VSS Xi I/O (i=0-11) Yi I/O (i=0-7) 9696 AX2 AX3 ISSUE 5 November 1988 ISO-CMOS

Figure 2 - Pin Connections * Plastic DIP and CERDIP only. Pin Description Pin #* Name Description 1Y 3 Y3 Analog (Input/Output): this is connected to the Y3 column of the switch array. 2A Y 2 Y2 Address Line (Input). 3R E S E T Master RESET (Input): this is used to turn off all switches. Active High. 4,5 AX3,AX0 X3 and X0 Address Lines (Inputs). 6,7 NC No Connection. 8-13 X6-X11 X6-X11 Analog (Inputs/Outputs): these are connected to the X6-X11 rows of the switch array. 14 NC No Connection. 15 Y7 Y7 Analog (Input/Output): this is connected to the Y7 column of the switch array. 16 NC No Connection. 17 Y6 Y6 Analog (Input/Output): this is connected to the Y6 column of the switch array. 18 STROBE STROBE (Input): enables function selected by address and data. Address must be stable before STROBE goes high and DATA must be stable on the falling edge of the STROBE. Active High. 19 Y5 Y5 Analog (Input/Output): this is connected to the Y5 column of the switch array. 20 V SS Ground Reference. 21 Y4 Y4 Analog (Input/Output): this is connected to the Y4 column of the switch array. 22, 23 AX1,AX2 X1 and X2 Address Lines (Inputs). 24, 25 AY0,AY1 Y0 and Y1 Address Lines (Inputs). 26, 27 NC No Connection. 28 - 33 X5-X0 X5-X0 Analog (Inputs/Outputs): these are connected to the X5-X0 rows of the switch array. 34 NC No Connection. 35 Y0 Y0 Analog (Input/Output): this is connected to the Y0 column of the switch array. 36 NC No Connection. 37 Y1 Y1 Analog (Input/Output): this is connected to the Y1 column of the switch array. 38 DATA DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off the selected switch. Active High. 39 Y2 Y2 Analog (Input/Output): this is connected to the Y2 column of the switch array. 40 V DD Positive Power Supply.

40 PIN CERDIP/PLASTIC DIP 44 PIN PLCC

2318 19 20 21 22 24 25 26 27 28 17 29 NC NC NC NC NC DATA VDD AY2 RESET AX3 AX0 NC

The MT8812 is an analog switch matrix with an array size of 8 x 12. The switch array is arranged such that there are 8 columns by 12 rows. The columns are referred to as the Y input/output lines and the rows are the X input/output lines. The crosspoint analog switch array will interconnect any X line with any Y line when turned on and provide a high degree of isolation when turned off. The control memory consists of a 96 bit write only RAM in which the bits are selected by the address input lines (AY0-AY2, AX0-AX3). Data is presented to the memory on the DATA input line. Data is asynchro-nously written into memory whenever the STROBE input is high and is latched on the falling edge of STROBE. A logical “1” written into a memory cell turns the corresponding crosspoint switch on and a logical “0” turns the crosspoint off. Only the crosspoint switches corresponding to the addressed memory location are altered when data is written into memory. The remaining switches retain their previous states. Any combination of X and Y lines can be interconnected by establishing appropriate patterns in the control memory. A logical “1” on the RESET input line will asynchronously return all memory locations to logical “0” turning off all crosspoint switches. Address Decode The seven address lines along with the STROBE input are logically ANDed to form an enable signal for the resettable transparent latches. The DATA input is buffered and is used as the input to all latches. To write to a location, RESET must be low while the address and data lines are set up. Then the STROBE input is set high and then low causing the data to be latched. The data can be changed while STROBE is high, however, the corresponding switch will turn on and off in accordance with the data. Data must be stable on the falling edge of STROBE in order for correct data to be written to the latch.

  • Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. † DC Electrical Characteristics are over recommended temperature range. ‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. Absolute Maximum Ratings*- Voltages are with respect to VSS unless otherwise stated. Parameter Symbol Min Max Units

1 Supply Voltage V DD

-0.3 -0.3 16.0 VDD +0.3 V V 2 Analog Input Voltage V INA -0.3 V DD +0.3 V 3 Digital Input Voltage V IN VSS -0.3 V DD +0.3 V

4 Current on any I/O Pin I ±15 mA

5 Storage Temperature T S -65 +150 °C

6 Package Power Dissipation PLASTIC DIP

0.6 1.0 W W Recommended Operating Conditions - Voltages are with respect to VSS unless otherwise stated. Characteristics Sym Min Typ Max Units Test Conditions

1 Operating Temperature T O 02 5 7 0 ° C

2 Supply Voltage V DD 4.5 14.5 V

3 Analog Input Voltage V INA VSS VDD V

4 Digital Input Voltage V IN VSS VDD V

Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Quiescent Supply Current I DD 11 0 0 µA All digital inputs at VIN=V SS or

7 15 mA All digital inputs at V IN=2.4V

2 Off-state Leakage Current

(See G.9 in Appendix) IOFF ±1 ±500 nA IV Xi - VYjI = VDD - VSS See Appendix, Fig. A.1 3 Input Logic “0” level V IL 0.8 V 4 Input Logic “1” level V IH 2.4 V 5 Input Leakage (digital pins) ILEAK 0.1 10 µA All digital inputs at VIN = VSS or VDD Characteristics Sym 25°C 60°C 70°C Units Test Conditions Typ Max Typ Max Typ Max

1 On-state V DD =14V

Resistance VDD =12V VDD =10V VDD = 5V (See G.1, G.2, G.3 in Appendix) R ON 45 145 220 110 260 Ω Ω Ω Ω V SS =0V,VDC =V DD /2, IVXi-VYjI = 0.4V See Appendix, Fig. A.2

2 Difference in on-state

(See G.4 in Appendix) Δ R ON 51 0 1 0 1 0 Ω VDD =14V, VSS =0, VDC =V DD /2, IVXi-VYjI = 0.4V See Appendix, Fig. A.2

† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details. ‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. Crosstalk measurements are for Plastic DIPS only, crosstalk values for PLCC packages are approximately 5dB better. † Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details. Digital Input rise time (tr) and fall time (tf) = 5ns. ‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. /G81 Refer to Appendix, Fig. A.7 for test circuit. I/O pins. Voltages are with respect to VDD =7V, VDC =0V, VSS =-7V, unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Switch I/O Capacitance C S 20 pF f=1 MHz

2 Feedthrough Capacitance C F 0.2 pF f=1 MHz

3 Frequency Response

Channel “ON” 20LOG(V OUT /VXi)=-3dB F3dB 45 MHz Switch is “ON”; V INA = 2Vpp sinewave; RL = 1kΩ See Appendix, Fig. A.3

4 Total Harmonic Distortion

(See G.5, G.6 in Appendix) THD 0.01 % Switch is “ON”; V INA = 2Vpp sinewave f= 1kHz; R L=1kΩ

5 Feedthrough

Channel “OFF” Feed.=20LOG (V OUT /VXi) (See G.8 in Appendix) FDT -95 dB All Switches “OFF”; V INA= 2Vpp sinewave f= 1kHz; R L= 1kΩ . See Appendix, Fig. A.4

6 Crosstalk between any two

channels for switches Xi-Yi and Xj-Yj. Xtalk=20LOG (VYj/VXi). (See G.7 in Appendix). Xtalk -45 dB V INA=2Vpp sinewave f= 10MHz; RL = 75Ω . -90 dB V INA=2Vpp sinewave f= 10kHz; RL = 600Ω . -85 dB V INA=2Vpp sinewave f= 10kHz; RL = 1kΩ . -80 dB V INA=2Vpp sinewave f= 1kHz; RL = 10kΩ . Refer to Appendix, Fig. A.5 for test circuit.

7 Propagation delay through

t PS 30 ns R L=1kΩ ; C L=50pF I/O pins. Voltages are with respect to VDD =7V, VDC =0V, VSS =-7V, unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Control Input crosstalk to switch

(for CS, DATA, STROBE, Address) CX talk 30 mVpp V IN=3V+V DC squarewave; R IN=1kΩ , RL=10kΩ . See Appendix, Fig. A.6

2 Digital Input Capacitance C DI 10 pF f=1MHz

3 Switching Frequency F O 20 MHz

4 Setup Time DATA to STROBE t DS 10 ns R L= 1kΩ , C L=50pF /G81

5 Hold Time DATA to STROBE t DH 10 ns R L= 1kΩ , C L=50pF /G81

6 Setup Time Address to STROBE t AS 10 ns R L= 1kΩ , C L=50pF /G81

7 Hold Time Address to STROBE t AH 10 ns R L= 1kΩ , C L=50pF /G81

8 STROBE Pulse Width t SPW 20 ns R L= 1kΩ , C L=50pF /G81

9 RESET Pulse Width t RPW 40 ns R L= 1kΩ , C L=50pF /G81

10 STROBE to Switch Status Delay t S 40 100 ns R L= 1kΩ , C L=50pF /G81

11 DATA to Switch Status Delay t D 50 100 ns R L= 1kΩ , C L=50pF /G81

12 RESET to Switch Status Delay t R 35 100 ns R L= 1kΩ , C L=50pF /G81

Table 1. Address Decode Truth Table ➀ This address has no effect on device status.