MT8806

MT8806 MITEL | Alldatasheet

Document overview

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Technical content

Features

• Internal control latches and address decoder
• Short set-up and hold times
• Wide operating voltage: 4.5V to 13.2V
• 12Vpp analog signal capability
• R ON 65Ω max. @ V DD =12V, 25°C
• Δ R ON ≤ 10Ω @ V DD =12V, 25°C
• Full CMOS switch for low distortion
• Minimum feedthrough and crosstalk
• Separate analog and digital reference supplies
• Low power consumption ISO-CMOS technology

Applications

• Key systems
• PBX systems
• Mobile radio
• Test equipment/instrumentation
• Analog/digital multiplexers
• Audio/Video switching

Description

The Mitel MT8806 is fabricated in MITEL’s ISO- CMOS technology providing low power dissipation and high reliability. The device contains a 8 x 4 array of crosspoint switches along with a 5 to 32 line decoder and latch circuits. Any one of the 32 switches can be addressed by selecting the appropriate five address bits. The selected switch can be turned on or off by applying a logical one or zero to the DATA input. V SS is the ground reference of the digital inputs. The range of the analog signal is from V DD to VEE . Chip Select (CS) allows the crosspoint array to be cascaded for matrix expansion.

Ordering Information

MT8806AC 24 Pin Ceramic DIP MT8806AE 24 Pin Plastic DIP MT8806AP 28 Pin PLCC -40° to 85°C Figure 1 - Functional Block Diagram 5 to 32 Decoder Latches 8 x 4 Switch Array AX0 AX1 AY0 AY1 AY2 CS STROBE DATA RESET VDD VEE VSS Xi I/O (i=0-3) Yi I/O (i=0-7) 3232 ISSUE 2 November 1988 MT8806 8 x 4 Analog Switch Array ISO-CMOS

Figure 2 - Pin Connections * Plastic DIP and CERDIP only Pin Description Pin #* Name Description 1-3 Y2-Y0 Y2-Y0 Analog (Inputs/Outputs): these are connected to the Y2-Y0 columns of the switch array. 4D A T A DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off the selected switch. Active High. 5X 0 X0 Analog (Input/Output): this is connected to the X0 row of the switch array. 6A X 0 X0 Address Line (Input). 7X 1 X1 Analog (Input/Output): this is connected to the X1 row of the switch array. 8A X 1 X1 Address Line (Input). 9X 2 X2 Analog (Input/Output): this is connected to the X2 row of the switch array. 10 CS Chip Select (Input): this is used to select the device. Active High. 11 X3 X3 Analog (Input/Output): this is connected to the X3 row of the switch array. 12 V SS Digital Ground Reference. 13 V EE Negative Power Supply. 14-16 AY0-AY2 Y0 -Y2 Address Lines (Inputs). 17 STROBE STROBE (Input): enables function selected by address and data. Address must be stable before STROBE goes high and DATA must be stable on the falling edge of the STROBE. Active High.

18 RESET Master RESET (Input): this is used to turn off all switches regardless of the condition of

CS. Active High. 19-23 Y7-Y3 Y7-Y3 Analog (Inputs/Outputs): these are connected to the Y7-Y3 columns of the switch array. 24 VDD Positive Power Supply. 12 13 DATA AX0 AX1 CS VSS VDD RESET STROBE AY2 AY1 AY0 VEE

28 PIN PLCC

24 PIN CERDIP/PLASTIC DIP

The MT8806 is an analog switch matrix with an array size of 8 x 4. The switch array is arranged such that there are 8 columns by 4 rows. The columns are referred to as the Y inputs/outputs and the rows are the X inputs/outputs. The crosspoint analog switch array will interconnect any X I/O with any Y I/O when turned on and provide a high degree of isolation when turned off. The control memory consists of a 32 bit write only RAM in which the bits are selected by the address inputs (AY0-AY2, AX0 & AX1). Data is presented to the memory on the DATA input. Data is asynchronously written into memory whenever both the CS (Chip Select) and the STROBE inputs are high and is latched on the falling edge of STROBE. A logical “1” written into a memory cell turns the corresponding crosspoint switch on and a logical “0” turns the crosspoint off. Only the crosspoint switches corresponding to the addressed memory location are altered when data is written into memory. The remaining switches retain their previous states. Any combination of X and Y inputs/ outputs can be interconnected by establishing appropriate patterns in the control memory. A logical “1” on the RESET input will asynchronously return all memory locations to logical “0” turning off all crosspoint switches regardless of whether CS is high or low. Two voltage reference pins (V SS and VEE ) are provided for the MT8806 to enable switching of negative analog signals. The range for digital signals is from V DD to VSS while the range for analog signals is from VDD to VEE . VSS and VEE pins can be tied together if a single voltage reference is needed. Address Decode The five address inputs along with the STROBE and CS (Chip Select) inputs are logically ANDed to form an enable signal for the resettable transparent latches. The DATA input is buffered and is used as the input to all latches. T o write to a location, RESET must be low and CS must go high while the address and data are set up. Then the STROBE input is set high and then low causing the data to be latched. The data can be changed while STROBE is high, however, the corresponding switch will turn on and off in accordance with the DATA input. DATA must be stable on the falling edge of STROBE in order for correct data to be written to the latch.

• Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. † DC Electrical Characteristics are over recommended temperature range. ‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. Absolute Maximum Ratings*- Voltages are with respect to VEE unless otherwise stated. Parameter Symbol Min Max Units

1 Supply Voltage V DD

-0.3 -0.3 15.0 VDD +0.3 V V 2 Analog Input Voltage V INA -0.3 V DD +0.3 V 3 Digital Input Voltage V IN VSS -0.3 V DD +0.3 V

4 Current on any I/O Pin I ±15 mA

5 Storage Temperature T S -65 +150 °C

6 Package Power Dissipation PLASTIC DIP

0.6 1.0 W W Recommended Operating Conditions - Voltages are with respect to VEE unless otherwise stated. Characteristics Sym Min Typ Max Units Test Conditions

1 Operating Temperature T O -40 25 85 °C

2 Supply Voltage V DD

4.5 VEE 13.2 VDD -4.5 V V

3 Analog Input Voltage V INA VEE VDD V

4 Digital Input Voltage V IN VSS VDD V

Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Quiescent Supply Current I DD 11 0 0 µA All digital inputs at VIN=V SS or

0.4 1.5 mA All digital inputs at V IN=2.4 + VSS ; VSS =7.0V 5 15 mA All digital inputs at V IN=3.4V

2 Off-state Leakage Current

(See G.9 in Appendix) IOFF ±1 ±500 nA IV Xi - VYjI = VDD - VEE See Appendix, Fig. A.1 3 Input Logic “0” level V IL 0.8+VS S VV SS =7.5V; VEE =0V 4 Input Logic “1” level V IH 2.0+VSS VV SS =6.5V; VEE =0V 5 Input Logic “1” level V IH 3.3 V 6 Input Leakage (digital pins) ILEAK 0.1 10 µA All digital inputs at VIN = VSS or VDD Characteristics Sym 25°C 70°C 85°C Units Test Conditions Typ Max Typ Max Typ Max

1 On-state V DD =12V

Resistance VDD =10V VDD = 5V (See G.1, G.2, G.3 in Appendix) R ON 45 120 185 215 225 Ω Ω Ω V SS =V EE =0V,VDC =V DD /2, IVXi-VYjI = 0.4V See Appendix, Fig. A.2

2 Difference in on-state

(See G.4 in Appendix) Δ R ON 51 0 1 0 1 0 Ω VDD =12V, VSS =V EE =0, VDC =V DD /2, IVXi-VYjI = 0.4V See Appendix, Fig. A.2

† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details. ‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. Crosstalk measurements are for Plastic DIPS only, crosstalk values for PLCC packages are approximately 5dB better. † Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details. Digital Input rise time (tr) and fall time (tf) = 5ns. ‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. /G81 Refer to Appendix, Fig. A.7 for test circuit. VEE =-7V, unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Switch I/O Capacitance C S 20 pF f=1 MHz

2 Feedthrough Capacitance C F 0.2 pF f=1 MHz

3 Frequency Response

Channel “ON” 20LOG(V OUT /VXi)=-3dB F3dB 45 MHz Switch is “ON”; V INA = 2Vpp sinewave; RL = 1kΩ See Appendix, Fig. A.3

4 Total Harmonic Distortion

(See G.5, G.6 in Appendix) THD 0.01 % Switch is “ON”; V INA = 2Vpp sinewave f= 1kHz; R L=1kΩ

5 Feedthrough

Channel “OFF” Feed.=20LOG (V OUT /VXi) (See G.8 in Appendix) FDT -95 dB All Switches “OFF”; V INA= 2Vpp sinewave; f= 1kHz; R L= 1kΩ . See Appendix, Fig. A.4

6 Crosstalk between any two

channels for switches Xi-Yi and Xj-Yj. Xtalk=20LOG (V Yj/VXi). (See G.7 in Appendix). Xtalk -45 dB V INA=2Vpp sinewave f= 10MHz; RL = 75Ω . -90 dB V INA=2Vpp sinewave f= 10kHz; RL = 600Ω . -85 dB V INA=2Vpp sinewave f= 10kHz; RL = 1kΩ . -80 dB V INA=2Vpp sinewave f= 1kHz; RL = 10kΩ . Refer to Appendix, Fig. A.5 for test circuit.

7 Propagation delay through

tPS 30 ns R L=1kΩ ; C L=50pF VEE =-7V, unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Control Input crosstalk to switch

(for CS, DATA, STROBE, Address) CX talk 30 mVpp V IN=3V squarewave; R IN=1kΩ , RL=10kΩ . See Appendix, Fig. A.6

2 Digital Input Capacitance C DI 10 pF f=1MHz

3 Switching Frequency F O 20 MHz

4 Setup Time DATA to STROBE t DS 10 ns R L= 1kΩ , C L=50pF /G81

5 Hold Time DATA to STROBE t DH 10 ns R L= 1kΩ , C L=50pF /G81

6 Setup Time Address to STROBE t AS 10 ns R L= 1kΩ , C L=50pF /G81

7 Hold Time Address to STROBE t AH 10 ns R L= 1kΩ , C L=50pF /G81

8 Setup Time CS to STROBE t CSS 10 ns R L= 1kΩ , C L=50pF /G81

9 Hold Time CS to STROBE t CSH 10 ns R L= 1kΩ , C L=50pF /G81

10 STROBE Pulse Width t SPW 20 ns R L= 1kΩ , C L=50pF /G81

11 RESET Pulse Width t RPW 40 ns R L= 1kΩ , C L=50pF /G81

12 STROBE to Switch Status Delay t S 40 100 ns R L= 1kΩ , C L=50pF /G81

13 DATA to Switch Status Delay t D 50 100 ns R L= 1kΩ , C L=50pF /G81

14 RESET to Switch Status Delay t R 35 100 ns R L= 1kΩ , C L=50pF /G81

Table 1. Address Decode Truth Table