MT8804A MITEL | Alldatasheet

Document overview

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Technical content

Features

  • Microprocessor compatible control inputs
  • On chip control memory and address decoding
  • Row addressing
  • Master reset
  • 32 crosspoint switches in 8 x 4 array
  • 5.0V to 15.0V operation
  • Low crosstalk between switches
  • Low on resistance: 90Ω (typ.) at 13V
  • Matched switch characteristics
  • Switches frequencies up to 40MHz

Applications

  • PABX and key sytems
  • Data acquisition systems
  • Test equipment/instrumentation
  • Analog/digital multiplexers

Description

The MT8804A is a CMOS/LSI 8 x 4 Analog Switch Array incorporating control memory (32 bits), deco- der and digital logic level converters. This circuit has digitally controlled analog switches having very low “ON“ resistance and very low “OFF” leakage current. Switches will operate with analog signals at frequencies to 40 MHz and up to 15.0Vp-p. A “HIGH“ on the Master Reset input switches all channels “OFF“ and clears the memory. This device is ideal for crosspoint switching applications.

Ordering Information

MT8804AC 24 Pin Ceramic DIP MT8804AE 24 Pin Plastic DIP MT8804AP 28 Pin PLCC -40° to 85°C Figure 1 - Functional Block Diagram 3 to 8 Decoder Latches 8 x 4 Switch Array 83 2 AE D0 D1 D2 D3 VDD VEE VSS MR Ji I/O (i=0-3) Li I/O (i=0-7) ISSUE 2 October 1989 MT8804A 8 x 4 Analog Switch Array CMOS

Figure 2 - Pin Connections * Plastic DIP and CERDIP only Pin Description Pin #* Name Description 1-3 L2-L0 L2-L0 Analog Lines (Inputs/Outputs): these are connected to the L2-L0 columns of the switch array. 4D 0 D0 Data (Input): Active High. 5J 0 J0 Analog Junctor (Input/Output): this is connected to the J0 row of the switch array. 6D I DI Data (Input). Active High. 7J 1 J1 Analog Junctor (Input/Output): this is connected to the J1 row of the switch array. 8D 2 D2 Data (Input): Active High. 9J 2 J2 Analog Junctor (Input/Output): this is connected to the J2 row of the switch array. 10 D3 D3 Data (Input): Active High. 11 J3 J3 Analog Junctor (Input/Output): this is connected to the J3 row of the switch array. 12 V SS Digital Ground Reference. 13 V EE Negative Power Supply. 14-16 A0-A2 A0-A2 Address Lines (Inputs). 17 AE Address Enable/Strobe (Input): enables function selected by address and data. Address must be stable before AE goes high and D0-D3 must be stable on the falling edge of the AE. Active High. 18 MR Master RESET (Input): this is used to turn off all switches. Active High. 19-23 L7-L3 L7-L3 Analog Lines (Inputs/Outputs): these are connected to the L7-L3 columns of the switch array. 24 V DD Positive Power Supply. 12 13 VSS VDD MR AE VEE

28 PIN PLCC

24 PIN CERDIP/PLASTIC DIP

  • Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. † DC Electrical Characteristics are at ambient temperature (25°C). ‡ Typical figures are for design aid only; not guaranteed and not subject to production testing. Absolute Maximum Ratings* - Voltages are with respect to VEE unless otherwise stated. Parameter Symbol Min Max Units

1 Supply Voltage V DD-VSS

-0.3 -0.3 -0.3 V V V

2 Analog Input Voltage V

INA VEE -0.3 V DD +0.3 V 3 Digital Input Voltage V IN VSS -0.3 V DD +0.3 V

4 Current on any Logic Pin I 10 mA

5 Storage Temperature T S -65 +150 °C

6 Package Power Dissipation PLASTIC DIP

0.6 1.2 W W Recommended Operating Conditions - Voltages are with respect to VEE unless otherwise stated. Characteristics Sym Min Typ Max Units Test Conditions

1 Operating Temperature TO -40 25 85 °C

2 Supply Voltage VDD -VSS

V V V

3 Analog Input Voltage VINA VEE V DD V

4 Digital Input Voltage VIN VSS V DD V

Characteristics Sym Min Typ ‡ Max Units Test Conditions 1 Quiescent Supply Current I DD 11 0 0 µAV DD =15V. All digital inputs at VIN=V SS or VDD

2 Off-state Leakage Current

(Any line to any junctor) IOFF ±0.1 ±500 nA V DD =13V, Switch is ‘Off’ IVJi - VLjI = VDD - VEE 3 Input Logic “0” level V IL 3.0 1.5 V V V DD =10V VDD =5V VINA=V DD through 1kΩ 4 Input Logic “1” level V IH 7.0 3.5 V V VDD =10V VDD =5V VINA=V DD through 1kΩ

5 Maximum current through

IMAX ±8.0 mA V DD =13V Characteristics Sym 25°C 70°C 85°C Units Test Conditions Min Typ Max Typ Typ

1 On-state V DD =13V

Resistance VDD =10V VDD = 5V R ON 60 90 105 290 108 160 650 105 120 320 110 125 325 Ω Ω Ω VSS =V EE =0V,VDC =V DD /2, IVJi - VLjI = 0.6V

2 Difference in on-state

VDD =13V VDD =10V ΔR ON 20 Ω Ω VSS =V EE =0V,VDC =V DD /2, IVJi - VLjI = 0.6V

† AC Electrical Characteristics are at ambient temperature (25°C). ‡ Typical figures are for design aid only; not guaranteed and not subject to production testing. † AC Electrical Characteristics are at ambient temperature (25°C). ‡ Typical figures are for design aid only; not guaranteed and not subject to production testing. Note 1 RL= 10kΩ , C L=50pF Note 2 RL= 1kΩ , CL=50pF Digital Input rise time (tr) and fall time (tf) = 5ns. I/O pins. Voltages are with respect to VDD =10V, VSS =V EE =0V unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Switch Line Capacitance C IS 5p F

2 Switch Junctor Capacitance C OS 20 pF

3 Feedthrough Capacitance C I 0.2 pF

4 Frequency Response

Channel “ON” 20LOG(VOUT / VINA) = -3dB F3dB 40 MHz Switch is “ON”; V DC =5V, VINA=5Vpp sinewave f= 1kHz; RL = 1kΩ

5 Total Harmonic Distortion

VDD =15V/VDC =7.5V VDD =10V/VDC =5V VDD =5V/VDC =2.5V THD 0.1 0.2 1.0 Switch is “ON”; V EE= VSS =0V VINA=5Vpp sinewave f= 1kHz; R L = 10kΩ

6 Feedthrough

Channel “OFF” Feed.=20LOG (V OUT / VINA) FDT -50 dB All Switches “OFF”; V INA= 5Vpp sinewave f= 1MHz; R L= 1kΩ . VDC =5V

7 Crosstalk between any two

channels for switches Li - Ji and Lj - Jj. Li - Ji is “ON“ Lj - Jj is “OFF“ Xtalk=20LOG (V Jj/VLi). Xtalk -40 -90 dB dB VINA=2Vpp sinewave f= 1.0MHz; RL = 600Ω . VINA=2Vpp sinewave f= 3.4kHz; RL = 600Ω . VDC = 5V

8 Propagation delay through

tPS 10 ns C L=50pF otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Digital Input Capacitance C DI 5p F V DD =10V

2 Setup Time D0-D3 to AE t DS 150

VDD =10V VDD =5V

3 Hold Time D0-D3 to AE t DH 120

VDD =10V VDD =5V

4 Setup Time Address to AE t AS 0

VDD =10V VDD =5V

5 Hold Time Address to AE t AH 120

VDD =10V VDD =5V

6 AE Pulse Width t AEW 100

VDD =10V VDD =5V

7 AE to Switch Status Delay t PAE 200

VDD =10V VDD =5V

8 DATA to Switch Status Delay t PLH

VDD =10V VDD =5V

9 MR to Switch Status Delay t MR

V DD =10V VDD =5V VDD =10V VDD =5V See Note 1 See Note 1 See Note 2

Figure 6 - Control Memory Timing Diagram Table 1 - Address Decode Truth Table NOTES: 0 - Low Logic Level 1 - High Logic Level X - Don’t Care Condition + - Indicates Connection Between Junctor and Addressed Line

  • - Indicates No Connection Between Junctor and Addressed Line Memory Reset MR Address Enable AE Address Addressed Line Input Data To Control Memory Junctors Connected To Addressed Line A2 A1 A0 D3 D2 D1 D0 J3 J2 J1 J0

1 X X X X ALL X X X X All Switches "OFF"

0 0 X X X NONE X X X X No Change of State tAEW tAS tDH tPLH /tPHL tPAE tMR tMRRtPLH /tPHL tDS tAH 50% 50% 50%50%50% 50% 50% 50% 50% MR AE ADDRESS D0-D3 SWITCH ON OFF