MT41J64M16

MT41J256M4 MDTIC | Alldatasheet

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PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D1 .fm - Rev. D 8/1/08 EN 1 ©2006 Micron Technology, Inc. All rights reserved. DDR3 SDRAM MT41J256M4 – 32 Meg x 4 x 8 Banks MT41J128M8 – 16 Meg x 8 x 8 Banks MT41J64M16 – 8 Meg x 16 x 8 Banks

• V DD = VDDQ = +1.5V ±0.075V  1.5V center-terminated push/pull I/O  Differential bidirectional data strobe 8 n-bit prefetch architecture  Differential clock inputs (CK, CK#) 8 i n t e r n a l b a n k s  Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals  CAS (READ) latency (CL): 5, 6, 7, 8, 9, 10, or 11  POSTED CAS ADDITIVE latency (AL): 0, CL - 1, CL - 2  CAS (WRITE) latency (CWL): 5, 6, 7, 8, based on tCK  Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])  Selectable BC4 or BL8 on-the-fly (OTF)  Self refresh mode C of 0oC to 95oC – 64ms, 8,192 cycle refresh at 0oC to 85oC – 32ms at 85oC to 95oC  Clock frequency range of 300–800 MHz  Self refresh temperature (SRT) A u t o m a t i c s e l f r e f r e s h ( A S R )  Write leveling M u l t i p u r p o s e r e g i s t e r  Output driver calibration Options Marking  Configuration – 256 Meg x 4 256M4 – 128 Meg x 8 128M8 – 64 Meg x 16 64M16  FBGA package (Pb-free) - x4, x8 – 78-ball FBGA (8mm x 11.5mm) Rev. F JP – 78-ball FBGA (9mm x 11.5mm) Rev. D HX – 86-ball FBGA (9mm x 15.5mm) Rev. B BY  FBGA package (Pb-free) - x16 – 96-ball FBGA (9mm x 15.5mm) Rev. B LA  Timing - cycle time – 1.25ns @ CL = 11 (DDR3-1600) -125 – 1.25ns @ CL = 10 (DDR3-1600) -125E – 1.25ns @ CL = 9 (DDR3-1600) -125F – 1.5ns @ CL = 10 (DDR3-1333) -15 – 1.5ns @ CL = 9 (DDR3-1333) -15E – 1.5ns @ CL = 8 (DDR3-1333) -15F – 1.87ns @ CL = 8 (DDR3-1066) -187 – 1.87ns @ CL = 7 (DDR3-1066) -187E – 2.5ns @ CL = 5 (DDR3-800) -25E  Revision :B/:D/:F Table 1: Key Timing Parameters Speed Grade Data Rate (MT/s) Target tRCD-tRP-CL tRCD (ns) tRP (ns) CL (ns) -125 1600 11-11-11 13.75 13.75 13.75 -125E 1600 10-10-10 12.5 12.5 12.5 -125F 1600 9-9-9 11.25 11.25 11.25 -15 1333 10-10-10 15 15 15 -15E 1333 9-9-9 13.5 13.5 13.5 -15F 1333 8-8-8 12 12 12 -187 1066 8-8-8 15 15 15 -187E 1066 7-7-7 13.1 13.1 13.1 -25 800 6-6-6 15 15 15 -25E 800 5-5-5 12.5 12.5 12.5

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D1 .fm - Rev. D 8/1/08 EN 2 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Figure 1: 1Gb DDR3 Part Numbers FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’ s Web site: www.micron.com. Table 2: Addressing Parameter 256 Meg x 4 128 Meg x 8 64 Meg x 16 Configuration 32 Meg x 4 x 8 banks 16 Meg x 8 x 8 banks 8 Meg x 16 x 8 banks Refresh count 8K 8K 8K Row addressing 16K (A[13:0]) 16K (A[13:0]) 8K (A[12:0]) Bank addressing 8 (BA[2:0]) 8 (BA[2:0]) 8 (BA[2:0]) Column addressing 2K (A[11, 9:0]) 1K (A[9:0]) 1K (A[9:0]) Package 78-ball 8mm x 11.5mm FBGA 78-ball 9mm x 11.5mm FBGA 86-ball 9mm x 15.5mm FBGA 96-ball 9mm x 15.5mm FBGA Mark JP HX BY LA Rev. F D B B Example Part Number: MT41J256M4BY-15:B Configuration

256 Meg x 4

128 Meg x 8

64 Meg x 16

tCK = 1.25ns, CL = 11 tCK = 1.25ns, CL = 10 tCK = 1.25ns, CL = 9 tCK = 1.5ns, CL = 10 tCK = 1.5ns, CL = 9 tCK = 1.5ns, CL = 8 tCK = 1.87ns, CL = 8 tCK = 1.87ns, CL = 7 tCK = 2.5ns, CL = 6 tCK = 2.5ns, CL = 5 -125 -125E -125F -15 -15E -15F -187 -187E -25 -25E ConfigurationMT41J Package Speed Revision Revision:B/:D/:F Temperature Commercial Industrial temperature None IT

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_TOC.fm - Rev. D 8/1/08 EN 3 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Table of Contents Table of Contents

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_TOC.fm - Rev. D 8/1/08 EN 4 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Table of Contents

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_LOT.fm - Rev. D 8/1/08 EN 8 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM List of Tables List of Tables

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_LOT.fm - Rev. D 8/1/08 EN 9 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM List of Tables Table 55: DDR3-800, DDR3-1066, DDR3-1333, and DDR3-1600 Derating Values for tIS/tIH – AC/DC-Based78 Table 59: DDR3-800, DDR3-1066, DDR3-1333, and DDR3-1600 Derating Values for tDS/tDH – AC/DC-Based85

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN 10 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM State Diagram State Diagram Figure 2: Simplified State Diagram SRX = Self refresh exit WRITE = WR, WRS4, WRS8 WRITE AP = WRAP, WRAPS4, WRAPS8 ZQCL = ZQ LONG CALIBRATION ZQCS = ZQ SHORT CALIBRATION Bank active ReadingWriting Activating Refreshing Self refresh Idle Active power- down ZQ calibration From any state Power applied Reset procedure Power on Initialization MRS, MPR, write leveling Precharge power- down Writing Reading Automatic sequence Command sequence Precharging READ READ READ READ AP READ AP READ AP PRE, PREA PRE, PREA PRE, PREA WRITE WRITE CKE L CKE L CKE L WRITE WRITE AP WRITE AP WRITE AP PDE PDE PDX PDX SRX SRE REF MRS ACT RESET ZQCL ZQCL/ZQCS ACT = ACTIVATE MPR = Multipurpose register MRS = Mode register set PDE = Power-down entry PDX = Power-down exit PRE = PRECHARGE PREA = PRECHARGE ALL READ = RD, RDS4, RDS8 READ AP = RDAP, RDAPS4, RDAPS8 REF = REFRESH RESET = START RESET PROCEDURE SRE = Self refresh entry

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN 11 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Functional Description Functional Description The DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock- cycle data transfers at the I/O pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble. Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE commands are used to select the bank and the starting column location for the burst access. DDR3 SDRAM use READ and WRITE BL8 and BC4. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM allows for concurrent operation, thereby providing high bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving, power-down mode. General Notes  The functionality and the timi ng specifications discussed in this data sheet are for the DLL enable mode of operation (normal operation).  Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ term is to be interpreted as any and all DQ collectively, unless specifically stated otherwise.  The terms “DQS” and “CK” found throughout the data sheet are to be interpreted as DQS, DQS# and CK, CK# respectively, unless specifically stated otherwise.  Complete functionality may be described throughout the entire document, and any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements.  Any specific requirement takes precedence over a general statement.  Any functionality not specifically stated herewithin is considered undefined, illegal, and not supported and can result in unknown operation.  Row addressing is denoted as A[ n:0](1Gb: n = 12 [x16]; 1Gb: n = 13 [x4, x8]).

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN 12 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Functional Block Diagrams Functional Block Diagrams DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally configured as an 8-bank DRAM. Figure 3: 256 Meg x 4 Functional Block Diagram Bank 5 Bank 6 Bank 7 Bank 4 Bank 7 Bank 4 Bank 5 Bank 6 Row- address MUX Control logic Column- address counter/ latch Mode registers Command decode A[13:0] BA[2:0] Address register17 256 (x32) 8,192 I/O gating DM mask logic Column decoder Bank 0 memory array (16,384 x 256 x 32) Bank 0 row- address latch and decoder 16,384 Sense amplifiers Bank control logic Bank 1 Bank 2 Bank 3 Refresh counter DQS, DQS# Columns 0, 1, and 2 Columns 0, 1, and 2 ZQCL, ZQCS To pull-up/pull-down networks READ drivers DQ[3:0] READ FIFO and data MUX Data Bank 1 Bank 2 Bank 3 DM DM CK, CK# DQS, DQS# ZQ CAL CS# ZQ RZQ CK, CK# RAS# WE# CAS# ODT CKE RESET# CK, CK# DLL DQ[3:0] (1 . . . 4) (1, 2) sw1 sw2 VDDQ/2 RTT_NOM RTT_WR sw1 sw2 VDDQ/2 RTT_NOM RTT_WR sw1 sw2 VDDQ/2 RTT_NOM RTT_WR OTF BC4 (burst chop) BC4 Column 2 (select upper or lower nibble for BC4) Data interface WRITE drivers and input logic ODT control VSSQ A12 OTF BC4

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN 14 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions Ball Assignments and Descriptions Figure 6: 78-Ball FBGA – x4, x8 Ball Assignments (Top View) Notes: 1. Ball descriptions listed in Table 3 on page 17 are listed as “x4, x8” if uni que; otherwise, x4 and x8 are the same. 2. A comma separates the configuration; a slash defines a selectable function. 3. Example D7 = NF, NF/TDQS#. NF applies to th e x4 configuration only. NF/TDQS# applies to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are defined in Table 3 on page 17). 1234 6 7895 VSS VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS VDD VSSQ DQ2 NF, DQ6 VDDQ VSS VDD CS# BA0 RESET# NC DQ0 DQS DQS# NF, DQ4 RAS# CAS# WE# BA2 A13 NF, NF/TDQS# DM, DM/TDQS DQ1 VDD NF, DQ7 CK CK# A10/AP NC A12/BC# A11 NC VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS VSS VSSQ DQ3 VSS NF, DQ5 VSS VDD ZQ VREFCA BA1 A B C D E F G H J K L M N

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN 15 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions Figure 7: 86-Ball FBGA – x4, x8 Ball Assignments (Top View) Notes: 1. Ball descriptions listed in Table 4 on page 19 are listed as “x4, x8” if uni que; otherwise, x4 and x8 are the same. 2. A comma separates the configuration; a slash defines a selectable function. 3. Example D7 = NF, NF/TDQS#. NF applies to th e x4 configuration only. NF/TDQS# applies to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are defined in Table 4 on page 19). 1234 6 7895 NC VSS VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS NC VDD VSSQ DQ2 NF, DQ6 VDDQ VSS VDD CS# BA0 RESET# NC NC DQ0 DQS DQS# NF, DQ4 RAS# CAS# WE# BA2 A13 NC NC NF, NF/TDQS# DM, DM/TDQS DQ1 VDD NF, DQ7 CK CK# A10/AP NC A12/BC# A11 NC NC NC VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS NC VSS VSSQ DQ3 VSS NF, DQ5 VSS VDD ZQ VREFCA BA1 A B C D E F G H J K L M N P R T U V W

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN 16 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions Figure 8: 96-Ball FBGA – x16 Ball Assignments (Top View) Notes: 1. Ball descriptions listed in Table 5 on page 21 are listed as “x4, x8” if uni que; otherwise, x4 and x8 are the same. 2. A comma separates the configuration; a slash defines a selectable function. 3. Example D7 = NF, NF/TDQS#. NF applies to th e x4 configuration only. NF/TDQS# applies to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are defined in Table 5 on page 21). 1234 6 7895 A B C D E F G H J K L M N P R T VDDQ VSSQ VDDQ VSSQ VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS DQ13 VDD DQ11 VDDQ VSSQ DQ2 DQ6 V DDQ VSS VDD CS# BA0 RESET# DQ15 VSS DQ9 UDM DQ0 LDQS LDQS# DQ4 RAS# CAS# WE# BA2 NC DQ12 UDQS# UDQS DQ8 LDM DQ1 VDD DQ7 CK CK# A10/AP NC A12/BC# A11 NC VDDQ DQ14 DQ10 V SSQ VSSQ DQ3 VSS DQ5 VSS VDD ZQ VREFCA BA1 VSS VSSQ VDDQ VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN 17 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions Ball Assignments Symbol Type Description K3, L7, L3, K2, L8, L2, M8, M2, N8, M3, H7, M7, K7, N3 A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10/AP , A11, A12/BC#, A13 Input Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/ WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to V REFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop, LOW = BC4 burst chop). See Table 62 on page 91. J2, K8, J3 BA0, BA1, BA2 Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VREFCA. F7, G7 CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#. G9 CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE power-down and SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA. H2 CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to VREFCA. B7 DM Input Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with the input data during a write access. Although the DM ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM is referenced to VREFDQ. DM has an optional use as TDQS on the x8. G1 ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to VREFCA. F3, G3, H3 RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered and are referenced to VREFCA.

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN 18 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions N2 RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDDQ and DC LOW ≤ 0.2 × VDDQ. RESET# assertion and desertion are asynchronous. B3, C7, C2, C8 DQ0, DQ1, DQ2, DQ3 I/O Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are referenced to VREFDQ. B3, C7, C2, C8, E3, E8, D2, E7 DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7 I/O Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are referenced to VREFDQ. C3, D3 DQS, DQS# I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data. B7, A7 TDQS, TDQS# Output Termination data strobe: Applies to the x8 configuration only. When TDQS is enabled, DM is disabled, and the TDQS and TDQS# balls provide termination resistance. A2, A9, D7, G2, G8, K1, K9, M1, M9 VDD Supply Power supply: 1.5V ±0.075V. B9, C1, E2, E9 V DDQ Supply DQ power supply: 1.5V ±0.075V. Isolated on the device for improved noise immunity. J8 V REFCA Supply Reference voltage for control, command, and address: VREFCA must be maintained at all times (including self refresh) for proper device operation. E1 V REFDQ Supply Reference voltage for data: VREFDQ must be maintained at all times (including self refresh) for proper device operation. A1, A8, B1, D8, F2, F8, J1, J9, L1, L9, N1, VSS Supply Ground. B2, B8, C9, D1, D9 V SSQ Supply DQ ground: Isolated on the device for improved noise immunity. H8 ZQ Reference External reference ball for output drive calibration: This ball is tied to an external 240Ω resistor (RZQ), which is tied to VSSQ. A3, J7, N7, F9, H1, F1, NC – No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). A7, D2, E3, E7, E8 NF – No function: When configured as a x4 device, these balls are NF. When configured as a x8 device, these balls are defined as TDQS#, DQ[7:4]. Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (continued) Ball Assignments Symbol Type Description

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN 19 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions Table 4: 86-Ball FBGA – x4, x8 Ball Descriptions Ball Assignments Symbol Type Description N3, P7, P3, N2, P8, P2, R8, R2, T8, R3, L7, R7, N7, A0, A1, A2, A3, A4, A5, A6, A7, A8, A9 A10/AP, A11, A12/BC#, A13 Input Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/ WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop, LOW = BC4 burst chop). See Table 62 on page 91. M2, N8, M3 BA0, BA1, BA2 Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VREFCA. J7, K7 CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#. K9 CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE power-down and SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA. L2 CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to VREFCA. E7 DM Input Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with the input data during a write access. Although the DM ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM is referenced to VREFDQ. DM has an optional use as TDQS on the x8. K1 ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to VREFCA. J3, K3, L3 RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered and are referenced to VREFCA.

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN 20 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions T2 RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDDQ and DC LOW ≤ 0.2 × VDDQ. RESET# assertion and desertion are asynchronous. E3, F7, F2, F8 DQ0, DQ1, DQ2, DQ3 I/O Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are referenced to VREFDQ. E3, F7, F2, F8, H3, H8, G2, H7 DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7 I/O Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are referenced to VREFDQ. F3, G3 DQS, DQS# I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data. E7, D7 TDQS, TDQS# Output Termination data strobe: Applies to the x8 configuration only. When TDQS is enabled, DM is disabled, and the TDQS and TDQS# balls provide termination resistance. D2, D9, G7, K2, K8, N1, N9, R1, R9 VDD Supply Power supply: 1.5V ±0.075V. E9, F1, H2, H9 V DDQ Supply DQ power supply: 1.5V ±0.075V. Isolated on the device for improved noise immunity. M8 V REFCA Supply Reference voltage for control, command, and address: VREFCA must be maintained at all times (including self refresh) for proper device operation. H1 V REFDQ Supply Reference voltage for data: VREFDQ must be maintained at all times (including self refresh) for proper device operation. D1, D8, E1, G8, J2, J8, M1, M9, P1, P9, T1, VSS Supply Ground. E2, E8, F9, G1, G9 V SSQ Supply DQ ground: Isolated on the device for improved noise immunity. L8 ZQ Reference External reference ball for output drive calibration: This ball is tied to an external 240Ω resistor (RZQ), which is tied to VSSQ. A1, A3, A7, A9, D3, J1, J9, L1, L9, M7, T7, W1, W3, W7, W9 NC – No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). D7, G2, H3, H7, H8 NF – No function: When configured as a x4 device, these balls are NF. When configured as a x8 device, these balls are defined as TDQS#, DQ[7:4]. Table 4: 86-Ball FBGA – x4, x8 Ball Descriptions (continued) Ball Assignments Symbol Type Description

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN 21 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions Table 5: 96-Ball FBGA – x16 Ball Descriptions Ball Assignments Symbol Type Description N3, P7, P3, N2, P8, P2, R8, R2, T8, R3, L7, R7, N7 A0, A1, A2, A3, A4, A5, A6, A7, A8, A9 A10/AP, A11, A12/BC# Input Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/ WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop, LOW = BC4 burst chop). See Table 62 on page 91. M2, N8, M3 BA0, BA1, BA2 Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VREFCA. J7, K7 CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#. K9 CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE power-down and SELF REFRESH operations (all banks idle),or active power-down (row active in any bank). CKE is synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to V REFCA. L2 CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to VREFCA. E7 LDM Input Input data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte input data is masked when LDM is sampled HIGH along with the input data during a write access. Although the LDM ball is input-only, the LDM loading is designed to match that of the DQ and DQS balls. LDM is referenced to V REFDQ. K1 ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS, LDQS#, UDQS, UDQS#, LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS, and NF/ TDQS# (when TDQS is enabled) for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to VREFCA. J3, K3, L3 RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered and are referenced to VREFCA.

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN 22 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions T2 RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDDQ and DC LOW ≤ 0.2 × VDDQ. RESET# assertion and desertion are asynchronous. D3 UDM Input Input data mask: UDM is an upper-byte, input mask signal for write data. Upper-byte input data is masked when UDM is sampled HIGH along with that input data during a WRITE access. Although the UDM ball is input-only, the UDM loading is designed to match that of the DQ and DQS balls. UDM is referenced to VREFDQ. E3, F7, F2, F8, H3, H8, G2, H7 DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7 I/O Data input/output: Lower byte of bidirectional data bus for the x16 configuration. DQ[7:0] are referenced to VREFDQ. D7, C3, C8, C2, A7, A2, B8, A3 DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, DQ15 I/O Data input/output: Upper byte of bidirectional data bus for the x16 configuration. DQ[15:8] are referenced to VREFDQ. F3, G3 LDQS, LDQS# I/O Lower byte data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data. C7, B7 UDQS, UDQS# I/O Upper byte data strobe: Output with read data. Edge-aligned with read data. Input with write data. DQS is center-aligned to write data. B2, D9, G7, K2, K8, N1, N9, R1, R9 VDD Supply Power supply: 1.5V ±0.075V. A1, A8, C1, C9, D2, E9, F1, H2, H9 VDDQ Supply DQ power supply: 1.5V ±0.075V. Isolated on the device for improved noise immunity. M8 V REFCA Supply Reference voltage for control, command, and address: VREFCA must be maintained at all times (including self refresh) for proper device operation. H1 V REFDQ Supply Reference voltage for data: VREFDQ must be maintained at all times (including self refresh) for proper device operation. A9, B3, E1, G8, J2, J8, M1, M9, P1, P9, T1, VSS Supply Ground. B1, B9, D1, D8, E2, E8, F9, G1, G9 VSSQ Supply DQ ground: Isolated on the device for improved noise immunity. L8 ZQ Reference External reference ball for output drive calibration: This ball is tied to an external 240Ω resistor (RZQ), which is tied to VSSQ. J1, J9, L1, L9, M7, T3, NC – No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). Table 5: 96-Ball FBGA – x16 Ball Descriptions (continued) Ball Assignments Symbol Type Description

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN 23 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions Package Dimensions Figure 9: 78-Ball FBGA – x4, x8; “JP” Notes: 1. All dimensions are in millimeters. Ball A1 ID 1.2 MAX0.8 TYP 0.8 ±0.1 Seating plane A 9.6 CTR

6.4 CTR

0.12 A 78X Ø0.45 11.5 ±0.15 Ball A1 ID

0.8 TYP

8 ±0.15

0.25 MIN

A B C D E F G H J K L M N Dimensions apply to solder balls post- reflow on Ø0.33 NSMD ball pads.

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN 24 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions Figure 10: 78-Ball FBGA – x4, x8; “HX” Notes: 1. All dimensions are in millimeters. Ball A1 ID Seating plane

0.12 A A

0.8 ±0.1

1.2 MAX

9 ±0.15 Ball A1 ID 9.6 CTR Solder ball material: SAC305. Dimensions apply to solder balls post- reflow on Ø0.33 NSMD ball pads. 78X Ø0.45 11.5 ±0.15 A B C D E F G H J K L M N

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN 25 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions Figure 11: 86-Ball FBGA – x4, x8 Notes: 1. All dimensions are in millimeters. Ball A1 ID Seating plane 0.8 ±0.1 Dimensions apply to solder balls post-reflow on Ø0.33 NSMD ball pads. 15.5 ±0.15

2.4 TYP

14.4 CTR

86X Ø0.45 9 ±0.15 A D E F G H J K L M N P R T W

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN 26 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions Figure 12: 96-Ball FBGA – x16 Notes: 1. All dimensions are in millimeters. Ball A1 ID Seating plane 0.8 ±0.1 Solder ball material: SAC305. Dimensions apply to solder balls post-reflow on Ø0.33 NSMD ball pads. 15.5 ±0.15

12 CTR

9 ±0.15 0.25 MIN6.4 CTR 96X Ø0.45 9 8 7 3 2 1 A B C D E F G H J K L M N P R S

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN 27 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications Electrical Specifications Absolute Ratings Stresses greater than those listed in Table 6 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Notes: 1. V DD and VDDQ must be within 300mV of each other at all times, and VREF must not be greater than 0.6 × VDDQ. When VDD and VDDQ are less than 500mV, VREF may be ≤300mV. 2. MAX operating case temperature. T C is measured in the center of the package (see Figure 13 on page 28). 3. Device functionality is no t guaranteed if the DRAM device exceeds the maximum TC during operation. Input/Output Capacitance Notes: 1. V DD = +1.5V ±0.075mV, VDDQ = VDD, VREF = VSS, f = 100 MHz, TC = 25°C. VOUT(DC)=0 . 5×V DDQ, VOUT (peak-to-peak) = 0.1V. 2. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 4. C DIO = CIO (DQ) - 0.5 × (CIO [DQS] + CIO [DQS#]). 5. Excludes CK, CK#; CTRL = ODT, CS#, and CKE; CMD = RAS#, CAS#, and WE#; ADDR = A[ n:0], BA[2:0]. 6. C DI_CTRL = CI (CTRL) - 0.5 × (CCK [CK] + CCK [CK#]). 7. C DI_CMD_ADDR = CI (CMD_ADDR) - 0.5 × (CCK [CK] + CCK [CK#]). Table 6: Absolute Maximum Ratings Symbol Parameter Min Max Units Notes VDD VDD supply voltage relative to VSS –0.4 1.975 V 1 VDDQV DD supply voltage relative to VSSQ– 0 . 4 1 . 9 7 5 V VIN, VOUT Voltage on any pin relative to VSS –0.4 1.975 V TC Operating case temperature 0 95 °C 2, 3 TSTG Storage temperature –55 150 °C Table 7: Input/Output Capacitance Note 1 applies to the entire table Capacitance Parameters Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units NotesMin Max Min Max Min Max Min Max ΔC: CK to CK# C DCK 00 . 1 500 . 1 500 . 1 500 . 1 5 p F Differential I/O: DQS, DQS#, TDQS, TDQS# ΔC: DQS to DQS#, TDQS, TDQS# C DDQS 0 0 . 2 0 0 . 2 00 . 1 500 . 1 5 p F 3

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN 29 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – IDD Specifications and Conditions Electrical Specifications – IDD Specifications and Conditions The following definitions are used within the IDD measurement tables: L O W : VIN ≤ VIL(AC) MAX; HIGH: VIN ≥ VIH(AC) MIN  Stable: Inputs are stable at a HIGH or LOW level  Floating: Inputs are V REF =V DDQ/2  Switching: See Tables 10 and 11 Table 9: I DD Measurement Conditions Reference Table Number Measurement Conditions Table 13 on page 31 I DD0 and IDD1 Table 14 on page 33 I DD2Ps, IDD2Pf, IDD2Q, IDD2N, IDD3P, and IDD3N Table 15 on page 35 I DD4R, IDD4W Table 16 on page 37 I DD5B, IDD6, IDD6ET Table 17 on page 38 I DD7 (see Table 18 on page 38) Table 10: Definition of Switching fo r Command and Address Input Signals Switching for Address (Row/Column) and Command Signals (CS#, RAS#, CAS#, and/or WE#) Address (row/column) If not otherwise stated, inputs are stab le at HIGH or LOW during 4 clocks and then change to the opposite value (Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax . . . ) Bank address If not otherwise stated, the bank addresses should be switched in a similar fashion as the row/column addresses Command (CS#, RAS#, CAS#, WE#) Define command background pattern = D D D D D D D D D D D D . . . where: D = (CS#, RAS#, CAS#, WE#) = (HIGH, LOW, LOW, LOW) D = (CS#, RAS#, CAS#, WE#) = (HIGH, HIGH, HIGH, HIGH) If other commands are necessary (ACTIVATE for IDD0 or READ for IDD4R), the background pattern command is substituted by the respective CS#, RAS#, CAS#, and WE# levels of the necessary command Table 11: Definition of Switching for Data Pins Switching for Data Pins (DQ, DQS, DM) Data strobe (DQS) Data strobe is changing be tween HIGH and LOW after every clock cycle Data (DQ) Data DQ is changing between HIGH and LOW every other data transfer (once per clock) for DQ signals, which means that data DQ is stable during one clock Data masking (DM) No switching; DM must always be driven LOW

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN 30 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – IDD Specifications and Conditions Notes: 1. I DD specifications are tested after the device is properly initialized. 2. Input slew rate is specified by AC parametric test conditions. 3. I DD parameters are specified with ODT and the output buffer is disabled (MR1[12]). 4. Optional ASR is disabl ed unless stated otherwise. Table 12: Timing Parameters IDD Parameter DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units -25E -25 -187E -187 -15F -15E -15 -125F -125E -125 tCK (MIN) IDD 2.5 1.875 1.5 1.25 ns CL IDD 567889 1 0 9 1 0 1 1 C K tRAS (MIN) IDD 37.5 37.5 37.5 37.5 36 36 36 35 35 35 ns tFAW x4, x8 40 40 37.5 37.5 30 30 30 30 30 30 ns x 1 6 5 05 05 05 04 54 5 4 5 4 0 4 0 4 0 n s tRRD IDD x4, x8 10 10 7.5 7.5 6 6 6 6 6 6 ns tRFC 110 110 110 110 110 110 110 110 110 110 ns

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN 31 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – IDD Specifications and Conditions Notes: 1. For further definition of input switching, see Table 10 on page 29. 2. For further definition of data switching, see Table 11 on page 29. Table 13: I DD Measurement Conditions for IDD0 and IDD1 IDD Test IDD0: Operating Current 0 One Bank ACTIVATE to PRECHARGE IDD1: Operating Current 1 One Bank ACTIVATE to READ to PRECHARGE Notes Timing example – Figure 14 on page 32 CKE HIGH HIGH External clock On On tCK tCK (MIN) IDD tCK (MIN) IDD tRC tRC (MIN) IDD tRC (MIN) IDD tRAS tRAS (MIN) IDD tRAS (MIN) IDD tRCD n/a tRCD (MIN) IDD tRRD n/a n/a tRC n/a n/a CL n/a CL I DD AL n/a 0 CS# HIGH between ACTIVATE and PRECHAR GE HIGH between ACTIVATE, READ, and PRECHARGE Command inputs Switching—the only exceptions are ACTIVATE and PRECHARGE commands; Example of -25E I DD0 pattern: A0DDDDDDDDDDDDDDP0 Switching—the only exceptions are ACTIVATE and PRECHARGE commands; Example of -25E IDD1 pattern: A0DDDDR0DDDDDDDDDP0 Row/column addresses Row addresses switching; Address input A10 must be LOW at all times Row addresses switching; Address input A10 must be LOW at all times Bank addresses Bank address is fixed (bank 0) Bank address is fixed (bank 0) Data I/O Switching R ead data: Output data switches after every clock cycle, which means that read data is stable during falling DQS; I/O should be floating when no read data Output buffer DQ, DQS Off Off ODT Disabled Disabled Burst length n/a 8 fixed (via MR0) Active banks Bank 0; ACTIVATE-to-PRECHARGE loop Bank 0; ACTIVATE-to-READ-to-PRECHARGE loop Idle banks All other All other Special notes n/a n/a

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN 32 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – IDD Specifications and Conditions Figure 14: I DD1 Example – DDR3-800, 5-5-5, x8 (-25E) Notes: 1. Data DQ is shown, but the output buffer should be switched off (per MR1[12] = 1) to achieve IOUT = 0mA (MR1[12] = 0 is reflected in this example; however, test conditions are MR1[12] = 1). Address inputs are split into three parts. A[9:0] CK BA[2:0] A10 A[12:11] CS# RAS# CAS# WE# Command IDD1 measurement loop DQ DM 3FF 000 3FF 000 3FF 0 30 30 D D# D# D RD D# D# D D D# D# D D D# PRE D D D# D# 00 1 1 0 0 1 T0 T1 T2 T3 T4 T5 T 6 T7 T8 T9 T10 T12 T14 T1 6 T18 000 ACT T11 T13 T15 T17

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN 33 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – IDD Specifications and Conditions Notes: 1. MR0[12] defines DLL on/off behavior during precharge power-down only; DLL on (fast exit, MR0[12] = 1) and DLL off (slow exit, MR0[12] = 0). 2. For further definition of input switching, see Table 10 on page 29. 3. For further definition of data switching, see Table 11 on page 29. Table 14: I DD Measurement Conditions for Power-Down Currents Name IDD2Ps Precharge Power-Down Current (Slow Exit)1 IDD2Pf Precharge Power-Down Current (Fast Exit)1 IDD2Q Precharge Quiet Standby Current IDD2N Precharge Standby Current IDD3P Active Power-Down Current IDD3N Active Standby Current Notes Timing example n/a n/a n/a Figure 15 on page 34 n/a Figure 15 on page 34 CKE LOW LOW HIGH HIGH LOW HIGH E x t e r n a l c l o c k O nO nO nO nO nO n tCK tCK (MIN) IDD tCK(MIN) IDD tCK(MIN) IDD tCK (MIN) IDD tCK (MIN) IDD tCK (MIN) IDD tRC n/a n/a n/a n/a n/a n/a tRAS n/a n/a n/a n/a n/a n/a tRCD n/a n/a n/a n/a n/a n/a tRRD n/a n/a n/a n/a n/a n/a tRC n/a n/a n/a n/a n/a n/a CL n/a n/a n/a n/a n/a n/a AL n/a n/a n/a n/a n/a n/a CS# Stable Stable HIGH HIGH Stable HIGH Command inputs Stable Stable Stab le Switching Stable Switching 2 Row/column addresses Stable Stable Stable Swit ching Stable Switching 2 Bank addresses Stable Stable Sta ble Switching Stable Switching 2 Data I/O Floating Floating Floating Switching Floating Switching 3 Output buffer DQ, DQS Off Off Off Off Off Off ODT Disabled Disabled Disabled Disabled Disabled Disabled Burst length n/a n/a n/a n/a n/a n/a Active banks None None None None All All Idle banks All All All All None None Special notes n/a n/a n/a n/a n/a n/a

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN 34 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – IDD Specifications and Conditions Figure 15: I DD2N/IDD3N Example – DDR3-800, 5-5-5, x8 (-25E) CK BA[2:0] A[12:0] CS# RAS# CAS# WE# DM 0 70 0000 1FFF 0000 T0 T1 T2 T3 T4 T5 T 6 T7 T8 T9 T10 IDD2N/IDD3N measurement loop DQ[7:0] FF 00 00 FF FF 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 FF 0000 FF Command D# D# D# D D#D# D#DD DD

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN 35 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – IDD Specifications and Conditions Notes: 1. For further definition of input switching, see Table 10 on page 29. 2. For further definition of data switching, see Table 11 on page 29. Table 15: I DD Measurement Conditions for IDD4R, IDD4W IDD Test IDD4R: Burst Read Operating Current IDD4W: Burst Write Operating Current Notes Timing diagram example Figure 16 on page 36 – CKE HIGH HIGH External clock On On tCK tCK (MIN) IDD tCK (MIN) IDD tRC n/a n/a tRAS n/a n/a tRCD n/a n/a tRRD n/a n/a tRC n/a n/a CL CL I DD CL IDD AL 0 0 CS# HIGH between valid commands HIGH between valid commands Command inputs Switching; READ command/pattern: R0DDD R1DDDR2DDDR3DDDR4 . . . Rx = READ from bank x Switching; WRITE command/pattern: W0DDDW1DDDW2DDDW3DDDW4 . . . Wx = WRITE to bank x Row/column addresses Column addresses switching; Address input A10 must always be LOW Column addresses switching; Address input A10 must always be LOW Data I/O Seamless read data burst (BL8): Output data switches after every clock cycle, which means that read data is stable during falling DQS Seamless write data burst (BL8): Input data switches after every clock cycle, which means that write data is stable during falling DQS Output buffer DQ, DQS Off Off ODT Disabled Disabled Burst length 8 fixed (via MR0) 8 fixed (via MR0) Active banks All All Idle banks None None Special notes n/a DM always LOW

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN 36 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – IDD Specifications and Conditions Figure 16: I DD4R Example – DDR3-800, 5-5-5, x8 Notes: 1. Data DQ is shown, but the output buffer should be switched off (per MR1[12] = 1) to achieve IOUT = 0mA (MR1[12] = 0 is reflected in this example; however, test conditions are MR1[12] = 1). Address inputs are split into three parts. CK BA[2:0] A[9:0] A10 A[12:11] CS# RAS# CAS# WE# CMD[2:0] DQ[7:0] DM 01 3 000 3FF 3FF 03 03 RD D D# D# RD D D# D# D D# D# RD D 00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 FF FF T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 RD Start measurement loop 000

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN 37 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – IDD Specifications and Conditions Notes: 1. For further definition of input switching, see Table 10 on page 29. 2. For further definition of data switching, see Table 11 on page 29. Table 16: I DD Measurement Conditions for IDD5B, IDD6, IDD6ET IDD Test IDD5B: Refresh Current IDD6: Self Refresh Current Normal Temperature Range TC = 0°C to 85°C IDD6ET: Self Refresh Current Extended Temperature Range TC = 0°C to 95°C Notes CKE HIGH LOW LOW External clock On Off, CK and CK# = LOW Off, CK and CK# = LOW tCK tCK (MIN) IDD n/a n/a tRC n/a n/a n/a tRAS n/a n/a n/a tRCD n/a n/a n/a tRRD n/a n/a n/a tRC tRFC (MIN) IDD n/a n/a CL n/a n/a n/a AL n/a n/a n/a CS# HIGH between valid commands Floating Floating Command inputs Switching Floating Floating 1 Row/column addresses Switching Floating Floating 1 Bank addresses Switching Floating Floating 1 Data I/O Switching Floating Floating 2 Output buffer DQ, DQS Disabled Disabled Disabled ODT Disabled Disabled Disabled Burst length n/a n/a n/a Active banks REFRESH command every tRFC (MIN) n/a n/a Idle banks None n/a n/a Special notes n/a SRT disabled SRT enabled

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN 38 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – IDD Specifications and Conditions Notes: 1. A0 = ACTIVATE bank 0; RA0 = READ with auto precharge bank 0; D = DESELECT. Table 17: I DD Measurement Conditions for IDD7 IDD Test IDD7: All Banks Interleaved Read Current CKE HIGH External clock On tCK tCK (MIN) IDD tRC tRC (MIN) IDD tRAS tRAS (MIN) IDD tRCD tRCD (MIN) IDD tRRD tRRD (MIN) IDD tRC n/a CL CL I DD AL CL - 1 CS# HIGH between valid commands Command inputs See Table 10 on page 29 for patterns Row/column addresses Stable during DESELECTs (DES) Bank addresses Looping (see Tabl e 10 on page 29 for patterns) Data I/O Read data (BL8): output data switches afte r every clock cycle, which means that read data is stable during falling DQS; I/O should be floating when no read data is being driven Output buffer DQ, DQS Off ODT Disabled Burst length 8 fixed (via MR0) Active banks All, rotational Idle banks n/a Table 18: I DD7 Patterns Speed Bin Width IDD7 Pattern DDR3-800 (-25, -25E) x4, x8 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D A0 . . . x16 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D D D A0 . . . DDR3-1066 (-187, -187E) x4, x8 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D D D A0 . . . x16 A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D A4 RA4 D D D D A5 RA5 D D D D A6 RA6 D D D D A7 RA7 D D D D D D D A0 . . . DDR3-1333 (-15, -15E, -15F) x4, x8 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D D D A0 . . . x16 A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D D D D D D D D D A4 RA4 D D D A5 RA5 D D D A6 RA6 D D D A7 RA7 D D D D D D D D D D D D D A0 . . . DDR3-1600 x4, x8 A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D D D A4 RA4 D D D A5 RA5 D D D A6 RA6 D D D A7 RA7 D D D D D D D A0 . . . x16 A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D D D D D D A4 RA4 D D D D A5 RA5 D D D D A6 RA6 D D D D A7 RA7 D D D D D D D D D D D D A0 . . .

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN 39 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics – IDD Specifications Electrical Characteristics – IDD Specifications IDD values are for full operating range of voltage and temperature unless otherwise noted. Notes: 1. T C = 85°C; SRT and ASR are disabled. 2. Enabling ASR could increase I DDx by up to an additional 2mA. 3. Restricted to T C (MAX) = 85°C. 4. T C = 85°C; ASR and ODT are disabled; SRT is enabled. Table 19: I DD Maximum Limits Speed Bin DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units NotesIDD Width IDD0 x4 65 75 85 95 mA 1, 2 x8 90 100 110 120 mA 1, 2 x16 90 100 110 120 mA 1, 2 IDD1 x4 85 95 105 115 mA 1, 2 x8 110 120 130 140 mA 1, 2 x16 110 130 150 170 mA 1, 2 IDD2 P S l o w ( s ) 1 01 01 01 0 m A 1 , 2 F a s t ( f ) 2 52 52 52 5 m A 1 , 2 IDD2Q All 40 45 50 55 mA 1, 2 IDD2 N A l l 4 55 05 56 0 m A 1 , 2 IDD3P All 25 30 35 40 mA 1, 2 IDD3N x4, x8 50 55 60 65 mA 1, 2 x 1 6 5 05 56 06 5 m A 1 , 2 IDD4R x4 130 160 200 250 mA 1, 2 x8 130 160 200 250 mA 1, 2 x16 190 230 270 315 mA 1, 2 IDD4W x4 130 160 190 225 mA 1, 2 x8 130 160 190 225 mA 1, 2 x16 210 265 325 400 mA 1, 2 IDD5B All 200 220 240 260 mA 1, 2 IDD6 A l l 6666 m A 1 , 2 , 3 IDD6ET All 9 9 9 9 mA 2, 4 IDD7 x4 230 250 315 400 mA 1, 2 x8 350 390 490 600 mA 1, 2 x16 350 380 420 460 mA 1, 2

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 40 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC Electrical Specifications – DC and AC DC Operating Conditions Notes: 1. V DD and VDDQ must track one another. VDDQ must be less than or equal to VDD. VSS = VSSQ. 2. V DD and VDDQ may include AC noise of ±50mV (250 kHz to 20 MHz) in addition to the DC (0Hz to 250 kHz) specifications. VDD and VDDQ must be at same level for valid AC timing parameters. 3. V REF (see Table 21). 4. The minimum limit re quirement is for testing purposes. The leakage current on the VREF pin should be minimal. Input Operating Conditions Notes: 1. V REFCA(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC level. Externally generated peak noise (noncommon mode) on VREFCA may not exceed ±1 percent × VDD around the VREFCA(DC) value. Peak-to-peak AC noise on VREFCA should not exceed ±2 percent of VREFCA(DC). 2. DC values are determined to be less than 20 MHz in fre quency. DRAM must meet specifica- tions if the DRAM induces additional AC noise greater than 20 MHz in frequency. 3. V REFDQ(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC level. Externally generated peak noise (noncommon mode) on VREFDQ may not exceed ±1 percent × VDD around the VREFDQ(DC) value. Peak-to-peak AC noise on VREFDQ should not exceed ±2 percent of VREFDQ(DC). 4. V TT is not applied directly to the device. VTT is a system supply for signal termination resis- tors. MIN and MAX values are system-dependent. Table 20: DC Electrical Characteristics and Operating Conditions All voltages are referenced to VSS Parameter/Condition Symbol Min Nom Max Units Notes Supply voltage V DD 1.425 1.5 1.575 V 1, 2 I/O supply voltage V DDQ 1.425 1.5 1.575 V 1, 2 Input leakage current Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.1V (All other pins not under test = 0V) II –2 – 2 µA VREF supply leakage current VREFDQ = VDD/2 or VREFCA = VDD/2 (All other pins not under test = 0V) IVREF –1 – 1 µA 3, 4 Table 21: DC Electrical Charact eristics and Input Conditions All voltages are referenced to VSS Parameter/Condition Symbol Min Nom Max Units Notes Input reference voltage command/address bus V REFCA(DC)0 . 4 9 × V DD 0.5 × VDD 0.51 × VDD V1 , 2 I/O reference voltage DQ bus V REFDQ(DC)0 . 4 9 × V DD 0.5 × VDD 0.51 × VDD V2 , 3 Command/address termination voltage (system level, not direct DRAM input) VTT –0 . 5 × V DDQ– V 4

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 41 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC Notes: 1. All voltages are referenced to V REF. VREF is VREFCA for control, command, and address. All slew rates and setup/hold times are specified at the DRAM ball. VREF is VREFDQ for DQ and DM inputs. 2. Input setup timing parameters ( tIS and tDS) are referenced at VIL(AC)/VIH(AC), not VREF(DC). 3. Input hold timing parameters ( tIH and tDH) are referenced at VIL(DC)/VIH(DC), not VREF(DC). 4. Single-ended input slew rate = 1 V/ns; maxi mum input voltage swing under test is 900mV (peak-to-peak). 5. For V IH(AC) and VIL(AC) levels of 150mV, special setup and hold derating and different tVAC numbers apply. Table 22: AC Input Operating Conditions Parameter/Condition Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units Command and Address Input high AC voltage: Logic 1 V IH(AC) MIN +175 +150 or +175 mV Input high DC voltage: Logic 1 V IH(DC) MIN +100 +100 mV Input low DC voltage: Logic 0 V IL(DC) MAX –100 –100 mV Input low AC voltage: Logic 0 V IL(AC) MAX –175 –150 or –175 mV DQ and DM Input high AC voltage: Logic 1 V IH(AC) MIN +175 +150 mV Input high DC voltage: Logic 1 V IH(DC) MIN +100 +100 mV Input low DC voltage: Logic 0 V IL(DC) MAX –100 –100 mV Input low AC voltage: Logic 0 V IL(AC) MAX –175 –150 mV

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 42 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC Figure 17: Input Signal Notes: 1. Numbers in diagrams reflect nominal values. AC Overshoot/Undershoot Specification Table 23: Control and Address Pins Parameter DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Maximum peak amplitude allowed for overshoot area (see Figure 18 on page 43) 0.4V 0.4V 0.4V 0.4V Maximum peak amplitude allowed for undershoot area (see Figure 19 on page 43) 0.4V 0.4V 0.4V 0.4V Maximum overshoot area above VDD (see Figure 18 on page 43) 0.67 Vns 0.5 Vns 0.4 Vns 0.33 Vns Maximum undershoot area below VSS (see Figure 19 on page 43) 0.67 Vns 0.5 Vns 0.4 Vns 0.33 Vns 0.575V 0.0V 0.650V 0.720V 0.735V 0.750V 0.765V 0.780V 0.850V 0.925V V IL(AC) VIL(DC) VREF - AC noise VREF - DC error VREF + DC error VREF + AC noise VIH(DC) VIH(AC) 1.50V 1.90V –0.40V VDDQ VDDQ + 0.4V narrow pulse width VSS - 0.4V narrow pulse width VSS 0.575V 0.650V 0.720V 0.735V 0.750V 0.765V 0.780V 0.850V 0.925V Minimum VIL and VIH levels VIH(DC) VIH(AC) VIL(AC) VIL(DC) VIL and VIH levels with ringback

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 44 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC Notes: 1. V MP(DC) specifies the input differential common mode voltage (VTR + VCP)/2 where VTR is the true input (CK, DQS) level and VCP is the complementary input (CK#, DQS#) level. VMP(DC) is expected to be about 0.5 × VDDQ. 2. The typical value of V IX(AC) is expected to be about 0.5 × VDD of the transmitting device, and VIX(AC) is expected to track variations in VDD. VIX(AC) indicates the voltage at which dif- ferential input signals must cross. 3. Reference is V REFCA(DC) for clock and for VREFDQ(DC) for strobe. 4. Clock is referenced to V DD and VSS. Data strobe is referenced to VDDQ and VSSQ. 5. Differential input slew rate = 2 V/ns. 6. The V IX extended range (±175mV) is allowed only for the clock. Additionally, the VIX extended range is only allowed when the following conditions are met: The single-ended input signals are monotonic, have the single-ended swing VSEL, VSEH of at least VDD/2 ±250mV, and the differential slew rate of CK, CK# is greater than 3 V/ns. Figure 20: Single-Ended Requirements for Differential Signals Table 25: Differential Input Operating Conditions (CK, CK# and DQS, DQS#) All voltages are referenced to VSS Parameter/Condition Symbol Min Max Units Differential input voltage V IN –400 V DD + 400 mV Differential input midpoint voltage V MP(DC)6 5 0 8 5 0 m V Differential input voltage logic high V IHDIFF 200 V DD + 400 mV Differential input voltage logic low V ILDIFF VSSQ - 400 –200 mV Differential input crossing voltage relative to VDD/2 for CK, CK# VIX VREF(DC) - 150 V REF(DC) + 150 mV VREF(DC) - 175 V REF(DC) + 175 mV Differential input crossing voltage relative to VDD/2 for DQS, DQS# VREF(DC) - 150 V REF(DC) + 150 mV VSS or VSSQ VDD or VDDQ VSEL (MAX) VSEH (MIN) VSEH VSEL VDD/2 or VDDQ/2 CK or DQS

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 45 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC Figure 21: Definition of Differential AC-Swing and tDVAC Table 26: Allowed Time Before Ringback ( tDVAC) for CK - CK# and DQS - DQS# Below VIL(AC) Slew Rate (V/ns) tDVAC (ps) at |VIHDIFF(AC)/VILDIFF(AC)| 350mV 300mV >4.0 75 175 4.0 57 170 3.0 50 167 2.0 38 163 1.9 34 162 1.6 29 161 1.4 22 159 1.2 13 155 1.0 0 150 <1.0 0 150 VIHDIFF(AC) MIN VIHDIFF(DC) MIN 0.0 VILDIFF(DC) MAX VILDIFF (MAX) tDVAC VIHDIFF (MIN) VILDIFF(AC) MAX half cycle tDVAC CK - CK# DQS - DQS#

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 46 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC Slew Rate Definitions for Single-Ended Input Signals Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF and the first crossing of VIH(AC) MIN. Setup (tIS and tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF and the first crossing of VIL(AC) MAX (see Figure 22 on page 47). Hold (tIH and tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC) MAX and the first crossing of VREF. Hold (tIH and tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC) MIN and the first crossing of VREF (see Figure 22 on page 47). Table 27: Single-Ended Inpu t Slew Rate Definition Input Slew Rates (Linear Signals) Measured CalculationInput Edge From To Setup Rising V REF VIH(AC) MIN Falling V REF VIL(AC) MAX Hold Rising V IL(DC) MAX V REF Falling V IH(DC) MIN V REF VIH(AC) MIN - VREF ΔTRS VREF - VIL(AC) MAX ΔTFS VREF - VIL(DC) MAX ΔTFH VIH(DC) MIN - VREF ΔTRSH

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 47 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC Figure 22: Nominal Slew Rate Definiti on for Single-Ended Input Signals ΔTRS ΔTFS ΔTRH ΔTFH VREFDQ or VREFCA VIH(AC) MIN VIH(DC) MIN VIL(AC) MAX VIL(DC) MAX VREFDQ or VREFCA VIH(AC) MIN VIH(DC) MIN VIL(AC) MAX VIL(DC) MAX Setup Hold Single-ended input voltage (DQ, CMD, ADDR)Single-ended input voltage (DQ, CMD, ADDR)

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 48 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC Slew Rate Definitions for Differential Input Signals Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured, as shown in Table 28 and Figure 23. The nominal slew rate for a rising signal is defined as the slew rate between VIL(DIFF ) MAX and VIH(DIFF ) MIN. The nominal slew rate for a falling signal is defined as the slew rate between VIH(DIFF )M I N a n d VIL(DIFF )M A X . Figure 23: Nominal Differential Input Slew Ra te Definition for DQS, DQS# and CK, CK# Table 28: Differential Input Slew Rate Definition Differential Input Slew Rates (Linear Signals) Measured CalculationInput Edge From To CK and DQS reference Rising V IL(DIFF) MAX V IH(DIFF) MIN Falling V IH(DIFF) MIN V IL(DIFF) MAX VIH(DIFF) MIN - VIL(DIFF) MAX ΔTR(DIFF) VIH(DIFF) MIN - VIL(DIFF) MAX ΔTF(DIFF) ΔTRDIFF ΔTFDIFF VIH(DIFF) MIN VIL(DIFF) MAX Differential input voltage (DQS, DQS#; CK, CK#)

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 49 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics ODT Characteristics ODT effective resistance RTT is defined by MR1[9, 6, and 2]. ODT is applied to the DQ, DM, DQS, DQS#, and TDQS, TDQS# balls (x8 devices only). The ODT target values are listed in Table 29 and Table 30 on page 50. A functional representation of the ODT is shown in Figure 24. The individual pull-up and pull-down resistors (R TTPU and RTTPD) are defined as follows: R TTPU = (VDDQ - VOUT)/|IOUT|, under the condition that RTTPD is turned off R TTPD = (VOUT)/|IOUT|, under the condition that RTTPU is turned off Figure 24: ODT Levels and I-V Characteristics Notes: 1. Tolerance limits are applicable after prop er ZQ calibration has been performed at a stable temperature and voltage (VDDQ = VDD, VSSQ = VSS). Refer to "ODT Sensitivity" on page 50 if either the temperature or voltage changes after calibration. 2. Measurement definition for R TT: Apply VIH(AC) to pin under test and measure current I[VIH(AC)], then apply VIL(AC) to pin under test and measure current I[VIL(AC)]: 3. Measure voltage (VM) at the tested pin with no load: ODT Resistors Table 30 on page 50 provides an overview of the ODT DC electrical characteristics. The values provided are not specification requirements; however, they can be used as design guidelines to indicate what R TT is targeted to provide: R TT 120Ω is made up of RTT120PD240 and RTT120PU240 R TT 60Ω is made up of RTT60PD120 and RTT60PU120 R TT 40Ω is made up of RTT40PD80 and RTT40PU80 R TT 30Ω is made up of RTT30PD60 and RTT30PU60 R TT 20Ω is made up of RTT20PD40 and RTT20PU40 Table 29: On-Die Termination DC Electrical Characteristics Parameter/Condition Symbol Min Nom Max Units Notes RTT effective impedance R TT_EFF See Table 30 on page 50 1, 2 Deviation of VM with respect to VDDQ/2 ΔVM –5 +5 % 1, 2, 3 RTTPU RTTPD ODT Chip in termination mode VDDQ DQ VSSQ IOUT = IPD - IPU IPU IPD IOUT VOUT To other circuitry such as RCV, . . . RTT VIH AC() VIL AC()– ΔVM 2V M× ⎛⎞ 100×=

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 50 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics Notes: 1. Values assume an RZQ of 240 Ω (±1 percent). ODT Sensitivity If either the temperature or voltage changes after I/O calibration, the tolerance limits listed in Table 29 on page 49 and Table 30 can be expected to widen according to Tables 31 and 32 on page 51. Table 30: R TT Effective Impedances MR1 [9, 6, 2] RTT Resistor VOUT Min Nom Max Units 0, 1, 0 120 Ω RTT120PD240 0.2 × VDDQ 0.6 1.0 1.1 RZQ/1 0.5 × VDDQ 0.9 1.0 1.1 RZQ/1 0.8 × VDDQ 0.9 1.0 1.4 RZQ/1 RTT120PU240 0.2 × VDDQ 0.9 1.0 1.4 RZQ/1 0.5 × VDDQ 0.9 1.0 1.1 RZQ/1 0.8 × VDDQ 0.6 1.0 1.1 RZQ/1 120Ω VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/2 0, 0, 1 60Ω RTT60PD120 0.2 × VDDQ 0.6 1.0 1.1 RZQ/2 0.5 × VDDQ 0.9 1.0 1.1 RZQ/2 0.8 × VDDQ 0.9 1.0 1.4 RZQ/2 RTT60PU120 0.2 × VDDQ 0.9 1.0 1.4 RZQ/2 0.5 × VDDQ 0.9 1.0 1.1 RZQ/2 0.8 × VDDQ 0.6 1.0 1.1 RZQ/2 60Ω VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/4 0, 1, 1 40 Ω RTT40PD80 0.2 × VDDQ 0.6 1.0 1.1 RZQ/3 0.5 × VDDQ 0.9 1.0 1.1 RZQ/3 0.8 × VDDQ 0.9 1.0 1.4 RZQ/3 RTT40PU80 0.2 × VDDQ 0.9 1.0 1.4 RZQ/3 0.5 × VDDQ 0.9 1.0 1.1 RZQ/3 0.8 × VDDQ 0.6 1.0 1.1 RZQ/3 40Ω VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/6 1, 0, 1 30Ω RTT30PD60 0.2 × VDDQ 0.6 1.0 1.1 RZQ/4 0.5 × VDDQ 0.9 1.0 1.1 RZQ/4 0.8 × VDDQ 0.9 1.0 1.4 RZQ/4 RTT30PU60 0.2 × VDDQ 0.9 1.0 1.4 RZQ/4 0.5 × VDDQ 0.9 1.0 1.1 RZQ/4 0.8 × VDDQ 0.6 1.0 1.1 RZQ/4 30Ω VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/8 1, 0, 0 20 Ω RTT20PD40 0.2 × VDDQ 0.6 1.0 1.1 RZQ/6 0.5 × VDDQ 0.9 1.0 1.1 RZQ/6 0.8 × VDDQ 0.9 1.0 1.4 RZQ/6 RTT20PU40 0.2 × VDDQ 0.9 1.0 1.4 RZQ/6 0.5 × VDDQ 0.9 1.0 1.1 RZQ/6 0.8 × VDDQ 0.6 1.0 1.1 RZQ/6 20Ω VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/12

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 52 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics Notes: 1. Assume an RZQ of 240 Ω (±1 percent) and that proper ZQ calibration has been performed at a stable temperature and voltage (VDDQ = VDD, VSSQ = VSS). Figure 26: tAON and tAOF Definitions Table 34: Reference Settings fo r ODT Timing Measurements Measured Parameter RTT_NOM Setting RTT_WR Setting VSW1 VSW2 tAON RZQ/4 (60 Ω) n/a 50mV 100mV RZQ/12 (20Ω) n/a 100mV 200mV tAOF RZQ/4 (60 Ω) n/a 50mV 100mV RZQ/12 (20Ω) n/a 100mV 200mV tAONPD RZQ/4 (60 Ω) n/a 50mV 100mV RZQ/12 (20Ω) n/a 100mV 200mV tAOFPD RZQ/4 (60 Ω) n/a 50mV 100mV RZQ/12 (20Ω) n/a 100mV 200mV tADC RZQ/12 (20 Ω)R Z Q / 2 ( 1 2 0 Ω) 200mV 300mV CK CK# tAON VSSQ DQ, DM DQS, DQS# TDQS, TDQS# Begin point: Rising edge of CK - CK# defined by the end point of ODTL on VSW1 End point: Extrapolated point at VSSQ TSW1 TSW2 CK CK# VDDQ/2 tAOF Begin point: Rising edge of CK - CK# defined by the end point of ODTL off End point: Extrapolated point at VRTT_NOM VRTT_NOM VSSQ tAON tAOF VSW2 VSW2 VSW1 TSW1 TSW1

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 54 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance Output Driver Impedance The output driver impedance is selected by MR1[5,1] during initialization. The selected value is able to maintain the tight tolerances specified if proper ZQ calibration is performed. Output specifications refer to the default output driver unless specifically stated otherwise. A functional representation of the output buffer is shown in Figure 29 on page 54. The output driver impedance RON is defined by the value of the external reference resistor RZQ as follows: R ONx =R Z Q /y (with RZQ = 240Ω ±1 percent; x = 34Ω or 40Ω with y = 7 or 6, respec- tively) The individual pull-up and pull-down resistors (RONPU and RONPD) are defined as follows: R ONPU = (VDDQ - VOUT)/|IOUT|, when RONPD is turned off R ONPD = (VOUT)/|IOUT|, when RONPU is turned off Figure 29: Output Driver 34Ω Output Driver Impedance The 34Ω driver (MR1[5, 1] = 01) is the default driver. Unless otherwise stated, all timings and specifications listed herein apply to the 34Ω driver only. Its impedance RON is defined by the value of the external reference resistor RZQ as follows: RON34 =R Z Q / 7 (with nominal RZQ = 240Ω ±1 percent) and is actually 34.3Ω ±1 percent. The 34Ω output driver impedance characteristics are listed in Table 35 on page 55. RONPU RONPD Output driver To other circuitry such as RCV, . . . Chip in drive mode V DDQ VSSQ IPU IPD IOUT VOUT DQ

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 55 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance Notes: 1. Tolerance limits assume RZQ of 240 Ω (±1 percent) and are applicable after proper ZQ cali- bration has been performed at a stable temperature and voltage (VDDQ = VDD, VSSQ=V SS). Refer to "34Ω Driver Output Sensitivity" on page 56 if either the temperature or the volt- age changes after calibration. 2. Measurement definition for mismatch between pull-up and pull-down (MMPUPD). Measure both RONPU and RONPD at 0.5 × VDDQ: 34Ω Driver The 34Ω driver’ s current range has been calculated and summarized in Table 37 on page 56 for VDD = 1.5V , Table 38 on page 56 for VDD = 1.575V , and Table 39 on page 56 for VDD = 1.425V . The individual pull-up and pull-down resistors (RON34PD and RON34PU) are defined as follows: R ON34PD = (VOUT)/|IOUT|; RON34PU is turned off R ON34PU = (VDDQ - VOUT)/|IOUT|; RON34PD is turned off Table 35: 34 Ω Driver Impedance Characteristics MR1[5,1] RON Resistor VOUT Min Nom Max Units Notes 0.5/VDDQ0 . 9 1 . 0 1 . 1 R Z Q /71 0.8/VDDQ0 . 9 1 . 0 1 . 4 R Z Q /71 RON34PU 0.2/VDDQ0 . 9 1 . 0 1 . 4 R Z Q /71 0.5/VDDQ0 . 9 1 . 0 1 . 1 R Z Q /71 0.8/VDDQ0 . 6 1 . 0 1 . 1 R Z Q /71 Pull-up/pull-down mismatch (MMPUPD) 0.5/V DDQ –10% n/a 10 % 1, 2 Table 36: 34 Ω Driver Pull-Up and Pull-Down Impedance Calculations RON Min Nom Max Units RZQ = 240Ω ±1 percent 237.6 240 242.4 Ω RZQ/7 = (240Ω ±1 percent)/7 33.9 34.3 34.6 Ω MR1[5,1] RON Resistor VOUT Min Nom Max Units 0.5 × VDDQ 30.5 34.3 38.1 Ω 0.8 × VDDQ 30.5 34.3 48.5 Ω RON34PU 0.2 × VDDQ 30.5 34.3 48.5 Ω 0.5 × VDDQ 30.5 34.3 38.1 Ω 0.8 × VDDQ 20.4 34.3 38.1 Ω MMPUPD RON PU RON PD– RON NOM

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 56 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance 34Ω Driver Output Sensitivity If either the temperature or the voltage changes after ZQ calibration, the tolerance limits listed in Table 35 on page 55 can be expected to widen according to Table 40 and Table 41 on page 57.Notes: 1. ΔT = T - T(@ calibration), ΔV = VDDQ - VDDQ(@ calibration), and VDD = VDDQ. Table 37: 34 Ω Driver IOH/IOL Characteristics: VDD = VDDQ = 1.5V MR1[5,1] RON Resistor VOUT Max Nom Min Units IOL @ 0.5 × VDDQ 24.6 21.9 19.7 mA IOL @ 0.8 × VDDQ 39.3 35.0 24.8 mA RON34PU IOH @ 0.2 × VDDQ 39.3 35.0 24.8 mA IOH @ 0.5 × VDDQ 24.6 21.9 19.7 mA IOH @ 0.8 × VDDQ1 4 . 7 8 . 8 7 . 9 m A Table 38: 34 Ω Driver IOH/IOL Characteristics: VDD = VDDQ = 1.575V MR1[5,1] RON Resistor VOUT Max Nom Min Units IOL @ 0.5 × VDDQ 25.8 23 20.7 mA IOL @ 0.8 × VDDQ 41.2 36.8 26 mA RON34PU IOH @ 0.2 × VDDQ 41.2 36.8 26 mA IOH @ 0.5 × VDDQ 25.8 23 20.7 mA IOH @ 0.8 × VDDQ1 5 . 5 9 . 2 8 . 3 m A Table 39: 34 Ω Driver IOH/IOL Characteristics: VDD = VDDQ = 1.425V MR1[5,1] RON Resistor VOUT Max Nom Min Units IOL @ 0.5 × VDDQ 23.3 20.8 18.7 mA IOL @ 0.8 × VDDQ 37.3 33.3 23.5 mA RON34PU IOH @ 0.2 × VDDQ 37.3 33.3 23.5 mA IOH @ 0.5 × VDDQ 23.3 20.8 18.7 mA IOH @ 0.8 × VDDQ1 4 . 0 8 . 3 7 . 5 m A Table 40: 34 Ω Output Driver Sensitivity Definition Symbol Min Max Units RON @ 0.8 × VDDQ 0.9 - dR ONdTH × |ΔT| - dRONdVH × |ΔV| 1.1 + dR ONdTH × |ΔT| + dRONdVH × |ΔV| RZQ /7 RON @ 0.5 × VDDQ 0.9 - dR ONdTM × |ΔT| - dRONdVM × |ΔV| 1.1 + dR ONdTM × |ΔT| + dRONdVM × |ΔV| RZQ/7 RON @ 0.2 × VDDQ 0.9 - dR ONdTL × |ΔT| - dRONdVL × |ΔV| 1.1 + dR ONdTL × |ΔT| + dRONd V L×|ΔV| RZQ /7

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 57 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance Alternative 40Ω Driver Notes: 1. Tolerance limits assume RZQ of 240 Ω (±1 percent) and are applicable after proper ZQ cali- bration has been performed at a stable temperature and voltage (VDDQ = VDD, VSSQ = VSS). Refer to "40Ω Driver Output Sensitivity" on page 57 if either the temperature or the volt- age changes after calibration. 2. Measurement definition for mismatch between pull-up and pull-down (MMPUPD). Measure both RONPU and RONPD at 0.5 × VDDQ: 40Ω Driver Output Sensitivity If either the temperature or the voltage changes after I/O calibration, the tolerance limits listed in Table 42 can be expected to widen according to Table 43 and Table 44 on page 58. Notes: 1. ΔT = T - T(@ calibration), ΔV = VDDQ - VDDQ(@ calibration), and VDD = VDDQ. Table 41: 34 Ω Output Driver Voltage and Temperature Sensitivity Change Min Max Units dRONdTM 0 1.5 %/°C dRONdVM 0 0.13 %/mV dRONdTL 0 1.5 %/°C dRONdVL 0 0.13 %/mV dRONdTH 0 1.5 %/°C dRONdVH 0 0.13 %/mV Table 42: 40 Ω Driver Impedance Characteristics MR1[5,1] RON Resistor VOUT Min Nom Max Units Notes 0,0 40 Ω RON40PD 0.2 × VDDQ 0.6 1.0 1.1 RZQ/6 1, 2 0.5 × VDDQ 0.9 1.0 1.1 RZQ/6 1, 2 0.8 × VDDQ 0.9 1.0 1.4 RZQ/6 1, 2 RON40PU 0.2 × VDDQ 0.9 1.0 1.4 RZQ/6 1, 2 0.5 × VDDQ 0.9 1.0 1.1 RZQ/6 1, 2 0.8 × VDDQ 0.6 1.0 1.1 RZQ/6 1, 2 Pull-up/pull-down mismatch (MMPUPD)0 . 5 × V DDQ –10% n/a 10 % 1, 2 Table 43: 40 Ω Output Driver Sensitivity Definition Symbol Min Max Units RON @ 0.8 × VDDQ 0.9 - dR ONdTH × |ΔT| - dRONdVH × |ΔV| 1.1 + dR ONdTH × |ΔT| + dRONdVH × |ΔV| RZQ/6 RON @ 0.5 × VDDQ 0.9 - dR ONdTM × |ΔT| - dRONdVM × |ΔV| 1.1 + dR ONdTM × |ΔT| + dRONdVM × |ΔV| RZQ/6 RON @ 0.2 × VDDQ 0.9 - dR ONdTL × |ΔT| - dRONdVL × |ΔV| 1.1 + dR ONdTL × |ΔT| + dRONd V L×|ΔV| RZQ/6 MM PUPD RON PU RON PD RON Nom

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 58 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Output Characteristics and Operating Conditions Output Characteristics and Operating Conditions The DRAM uses both single-ended and differential output drivers. The single-ended output driver is summarized in Table 45 while the differential output driver is summa- rized in Table 46 on page 59. Notes: 1. RZQ of 240 Ω (±1 percent) with RZQ/7 enabled (default 34Ω driver) and is applicable after proper ZQ calibration has been performed at a stable temperature and voltage (VDDQ=V DD, VSSQ=V SS). 2. V TT = VDDQ/2. 3. See Figure 32 on page 60 for the test load configuration. 4. See Table 35 on page 55 for IV curve linearity. Do not use AC test load. 5. See Table 47 on page 61 for output slew rate. 6. See Table 35 on page 55 fo r additional information. 7. See Figure 30 on page 59 for an exampl e of a single-ended output signal. Table 44: 40 Ω Output Driver Voltage and Temperature Sensitivity Change Min Max Unit dRONdTM 0 1.5 %/°C dRONdVM 0 0.15 %/mV dRONdTL 0 1.5 %/°C dRONdVL 0 0.15 %/mV dRONdTH 0 1.5 %/°C dRONdVH 0 0.15 %/mV Table 45: Single-Ended Output Driver Characteristics All voltages are referenced to Vss Parameter/Condition Symbol Min Max Units Notes Output leakage current: DQ are disabled; 0V ≤ VOUT ≤ VDDQ; ODT is disabled; ODT is HIGH IOZ –5 +5 µA 1 Output slew rate: Single-ended; For rising and falling edges, measure between VOL(AC) = VREF - 0.1 × VDDQ and VOH(AC)=V REF +0 . 1×V DDQ SRQSE 2.5 5 V/ns 1, 2, 3 Single-ended DC high-level output voltage V OH(DC)0 . 8 × V DDQV 1 , 2 , 4 Single-ended DC mid-point level output voltage V OM(DC)0 . 5 × V DDQV 1 , 2 , 4 Single-ended DC low-level output voltage V OL(DC)0 . 2 × V DDQV 1 , 2 , 4 Single-ended AC high-level output voltage V OH(AC)V TT + 0.1 × VDDQ V 1, 2, 3, 5 Single-ended AC low-level output voltage V OL(AC)V TT - 0.1 × VDDQ V 1, 2, 3, 5 Delta RON between pull-up and pull-down for DQ/DQS MM PUPD –10 +10 % 1, 6 Test load for AC timing and output slew rates Output to V TT (VDDQ/2) via 25Ω resistor 3

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 59 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Output Characteristics and Operating Conditions Notes: 1. RZQ of 240 Ω (±1 percent) with RZQ/7 enabled (default 34Ω driver) and is applicable after proper ZQ calibration has been performed at a stable temperature and voltage (VDDQ=V DD, VSSQ=V SS). 2. V REF = VDDQ/2. 3. See Figure 32 on page 60 for the test load configuration. 4. See Table 48 on page 62 for the output slew rate. 5. See Table 35 on page 55 fo r additional information. 6. See Figure 31 on page 60 for an exampl e of a differential output signal. Figure 30: DQ Output Signal Table 46: Differential Output Driver Characteristics All voltages are referenced to Vss Parameter/Condition Symbol Min Max Units Notes Output leakage current: DQ are disabled; 0V ≤ VOUT ≤ VDDQ; ODT is disabled; ODT is HIGH IOZ –5 +5 µA 1 Output slew rate: Differential; For rising and falling edges, measure between VOLDIFF(AC) = –0.2 × VDDQ and VOHDIFF(AC) = +0.2 × VDDQ SRQDIFF 51 0 V / n s 1 Output differential cross-point voltage V OX(AC)V REF - 100 V REF + 100 mV 1, 2, 3 Differential high-level output voltage V OHDIFF(AC)+ 0 . 2 × V DDQV 1 , 4 Differential low-level output voltage V OLDIFF(AC)– 0 . 2 × V DDQV 1 , 4 Delta RON between pull-up and pull-down for DQ/DQS MM PUPD –10 +10 % 1, 5 Test load for AC timing and output slew rates Output to V TT (VDDQ/2) via 25Ω resistor 3 VOH(AC) MIN output MAX output VOL(AC)

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 61 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Output Characteristics and Operating Conditions Slew Rate Definitions for Single-Ended Output Signals The single-ended output driver is summarized in Table 45 on page 58. With the refer- ence load for timing measurements, the output slew rate for falling and rising edges is defined and measured between V OL(AC) and VOH(AC) for single-ended signals, as shown in Table 47 and Figure 33. Figure 33: Nominal Slew Rate Definiti on for Single-Ended Output Signals Table 47: Single-Ended Outp ut Slew Rate Definition Single-Ended Output Slew Rates (Linear Signals) Measured CalculationOutput Edge From To DQ Rising V OL(AC)V OH(AC) Falling V OH(AC)V OL(AC) VOH(AC) - VOL(AC) ΔTRSE VOH(AC) - VOL(AC) ΔTFSE ΔTRSE ΔTFSE VOH(AC) VOL(AC) VTT

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 62 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Output Characteristics and Operating Conditions Slew Rate Definitions for Differential Output Signals The differential output driver is summarized in Table 46 on page 59. With the reference load for timing measurements, the output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for differential signals, as shown in Table 48 and Figure 34. Figure 34: Nominal Differential Output Slew Rate Definition for DQS, DQS# Table 48: Differential Outp ut Slew Rate Definition Differential Output Slew Rates (Linear Signals) Measured CalculationOutput Edge From To DQS, DQS# Rising V OLDIFF(AC)V OHDIFF(AC) Falling V OHDIFF(AC)V OLDIFF(AC) VOHDIFF(AC) - VOLDIFF(AC) ΔTRDIFF VOHDIFF(AC) - VOLDIFF(AC) ΔTFDIFF ΔTRDIFF ΔTFDIFF VOH(DIFF)AC VOL(DIFF)AC

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 63 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Speed Bin Tables Notes: 1. tREFI depends on TOPER. 2. The CL and CWL settings result in tCK requirements. When making a selection of tCK, both CL and CWL requirement settings need to be fulfilled. 3. Reserved settings are not allowed. Table 49: DDR3-800 Speed Bins DDR3-800 Speed Bin -25E -25 Units Notes CL-tRCD-tRP 5-5-5 6-6-6 Parameter Symbol Min Max Min Max ACTIVATE to internal READ or WRITE delay time tRCD 12.5 – 15 – ns PRECHARGE command period tRP 12.5 – 15 – ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC 50 – 52.5 – ns ACTIVATE-to-PRECHARGE command period tRAS 37.5 9 × tREFI 37.5 9 × tREFI ns 1 CL = 5 CWL = 5 tCK (AVG) 2.5 3.3 Reserved ns 2, 3 CL = 6 CWL = 5 tCK (AVG) 2.5 3.3 2.5 3.3 ns 2 Supported CL settings 5, 6 6 CK Supported CWL settings 5 5 CK

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 64 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Notes: 1. tREFI depends on TOPER. 2. The CL and CWL settings result in tCK requirements. When making a selection of tCK, both CL and CWL requirement settings need to be fulfilled. 3. Reserved settings are not allowed. Table 50: DDR3-1066 Speed Bins DDR3-1066 Speed Bin -187E -187 Units Notes CL-tRCD-tRP 7-7-7 8-8-8 Parameter Symbol Min Max Min Max ACTIVATE to internal READ or WRITE delay time tRCD 13.125 – 15 – ns PRECHARGE command period tRP 13.125 – 15 – ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC 50.625 – 52.5 – ns ACTIVATE-to-PRECHARGE command period tRAS 37.5 9 × tREFI 37.5 9 × tREFI ns 1 CL = 5 CWL = 5 tCK (AVG) Reserved Reserved ns 2, 3 CWL = 6 tCK (AVG) Reserved Reserved ns 3 CL = 6 CWL = 5 tCK (AVG) 2.5 3.3 2.5 3.3 ns 2 CWL = 6 tCK (AVG) Reserved Reserved ns 2, 3 CL = 7 CWL = 5 tCK (AVG) Reserved Reserved ns 3 CWL = 6 tCK (AVG) 1.875 <2.5 Reserved ns 2, 3 CL = 8 CWL = 5 tCK (AVG) Reserved Reserved ns 3 CWL = 6 tCK (AVG) 1.875 <2.5 1.875 <2.5 ns 2 Supported CL settings 6, 7, 8 6, 8 CK Supported CWL settings 5, 6 5, 6 CK

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 65 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Notes: 1. tREFI depends on TOPER. 2. The CL and CWL settings result in tCK requirements. When making a selection of tCK, both CL and CWL requirement settings need to be fulfilled. 3. Reserved settings are not allowed. Table 51: DDR3-1333 Speed Bins DDR3-1333 Speed Bin -15F -15E -15 Units Notes CL-tRCD-tRP 8-8-8 9-9-9 10-10-10 Parameter Symbol Min Max Min Max Min Max ACTIVATE to internal READ or WRITE delay time tR C D 1 2– 1 3 . 5 –1 5– n s PRECHARGE command period tRP 12 – 13.5 – 15 – ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC 48 – 49.5 – 51 – ns ACTIVATE-to-PRECHARGE command period tRAS 36 9 × tREFI 36 9 × tREFI 36 9 × tREFI ns 1 CL = 5 CWL = 5 tCK (AVG) 2.5 3.3 Reserved Reserved ns 2, 3 CWL = 6, 7 tCK (AVG) Reserved Reserved Reserved ns 3 CWL = 6 tCK (AVG) Reserved Reserved Reserved ns 2, 3 CWL = 7 tCK (AVG) Reserved Reserved Reserved ns 3 CL = 7 CWL = 5 tCK (AVG) Reserved Reserved Reserved ns 3 CWL = 6 tCK (AVG) 1.875 <2.5 1.875 <2.5 Reserved ns 2, 3 CWL = 7 tCK (AVG) Reserved Reserved Reserved ns 2, 3 CL = 8 CWL = 5 tCK (AVG) Reserved Reserved Reserved ns 3 CWL = 7 tCK (AVG) 1.5 <1.875 Reserved Reserved ns 2, 3 CL = 9 CWL = 5, 6 tCK (AVG) Reserved Reserved Reserved ns 3 CWL = 7 tCK (AVG) 1.5 <1.875 1.5 <1.875 Reserved ns 2, 3 CL = 10 CWL = 5, 6 tCK (AVG) Reserved Reserved Reserved ns 3 Supported CL settings 5, 6, 7, 8, 9, 10 6, 7, 8, 9, 10 6, 8, 10 CK Supported CWL settings 5, 6, 7 5, 6, 7 5, 6, 7 CK

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 66 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Notes: 1. tREFI depends on TOPER. 2. The CL and CWL settings result in tCK requirements. When making a selection of tCK, both CL and CWL requirement settings need to be fulfilled. 3. Reserved settings are not allowed. Table 52: DDR3-1600 Speed Bins DDR3-1600 Speed Bin -125F -125E -125 Units Notes CL-tRCD-tRP 9-9-9 10-10-10 11-11-11 Parameter Symbol Min Max Min Max Min Max ACTIVATE to internal READ or WRITE delay time tRCD 11.25 – 12.5 – 13.75 – ns PRECHARGE command period tRP 11.25 – 12.5 – 13.75 – ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC 46.25 – 47.5 – 48.75 – ns ACTIVATE-to-PRECHARGE command period tRAS 35 9 × tREFI 35 9 × tREFI 35 9 × tREFI ns 1 CL = 5 CWL = 5 tCK (AVG) 2.5 3.3 2.5 3.3 Reserved ns 2, 3 CWL = 6, 7, 8 tCK (AVG) Reserved Reserved Reserved ns 3 CWL = 6 tCK (AVG) Reserved Reserved Reserved ns 2, 3 CWL = 7, 8 tCK (AVG) Reserved Reserved Reserved ns 3 CL = 7 CWL = 5 tCK (AVG) Reserved Reserved Reserved ns 3 CWL = 6 tCK (AVG) 1.875 <2.5 1.875 <2.5 Reserved ns 2, 3 CWL = 7 tCK (AVG) Reserved Reserved Reserved ns 2, 3 CWL = 8 tCK (AVG) Reserved Reserved Reserved ns 3 CL = 8 CWL = 5 tCK (AVG) Reserved Reserved Reserved ns 3 CWL = 7 tCK (AVG) 1.5 <1.875 Reserved Reserved ns 2, 3 CWL = 8 tCK (AVG) Reserved Reserved Reserved ns 2, 3 CL = 9 CWL = 5, 6 tCK (AVG) Reserved Reserved Reserved ns 3 CWL = 7 tCK (AVG) 1.5 <1.875 1.5 <1.875 Reserved ns 2, 3 CWL = 8 tCK (AVG) 1.25 <1.5 Reserved Reserved ns 2, 3 CL = 10 CWL = 5, 6 tCK (AVG) Reserved Reserved Reserved ns 3 CWL = 8 tCK (AVG) 1.25 <1.5 1.25 <1.5 Reserved ns 2, 3 CL = 11 CWL = 5, 6, 7 tCK (AVG) Reserved Reserved Reserved ns 3 Supported CL settings 5, 6, 7, 8, 9, 10, 11 5, 6, 7, 8, 9, 10, 11 6, 8, 10, 11 CK Supported CWL settings 5, 6, 7, 8 5, 6, 7, 8 5, 6, 7, 8 CK

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 67 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Table 53: Electrical Characteristics and AC Operating Conditions (Sheet 1 of 7) Notes: 1–8 apply to the entire table; notes appear on page 74 Parameter Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units NotesMin Max Min Max Min Max Min Max Clock Timing Clock period average: DLL disable mode TC = 0°C to 85°C tCKDLL_DIS 87 , 8 0 087 , 8 0 087 , 8 0 087 , 8 0 0 n s9 TC = > 8 5 ° C t o 9 5 ° C 83 , 9 0 083 , 9 0 083 , 9 0 083 , 9 0 0 n s Clock period average: DLL enable mode tCK (AVG) See “Speed Bin Tables” on page 63 for tCK range allowed ns 10 , 11 Clock period jitter DLL locked tJITPER –100 100 –90 90 –80 80 –70 70 ps 13 DLL locking tJITPER, LCK –90 90 –80 80 –70 70 –60 60 ps 13 Clock absolute period tCK(ABS) MIN = tCK (AVG) MIN + tJITPER MIN; MAX = tCK (AVG) MAX + tJITPER MAX ps Clock absolute high pulse width tCH (ABS) 0.43 – 0.43 – 0.43 – 0.43 – tCK (AVG) Clock absolute low pulse width tCL (ABS) 0.43 – 0.43 – 0.43 – 0.43 – tCK (AVG) Cycle-to-cycle jitter DLL locked tJITCC 200 180 160 140 ps 16 DLL locking tJITCC, LCK 180 160 140 120 ps 16 Cumulative error across 2 cycles tERR2PER –147 147 –132 132 –118 118 –103 103 ps 17 3 cycles tERR3PER –175 175 –157 157 –140 140 –122 122 ps 17 4 cycles tERR4PER –194 194 –175 175 –155 155 –136 136 ps 17 5 cycles tERR5PER –209 209 –188 188 –168 168 –147 147 ps 17 6 cycles tERR6PER –222 222 –200 200 –177 177 –155 155 ps 17 7 cycles tERR7PER –232 232 –209 209 –186 186 –163 163 ps 17 8 cycles tERR8PER –241 241 –217 217 –193 193 –169 169 ps 17 9 cycles tERR9PER –249 249 –224 224 –200 200 –175 175 ps 17 10 cycles tERR10PER –257 257 –231 231 –205 205 –180 180 ps 17 11 cycles tERR11PER –263 263 –237 237 –210 210 –184 184 ps 17 12 cycles tERR12PER –269 269 –242 242 –215 215 –188 188 ps 17 cycles tERRnPER tERRnPER MIN = (1 + 0.68ln[n]) × tJITPER MIN tERRnPER MAX = (1 + 0.68ln[n]) × tJITPER MAX ps 17

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 68 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables DQ Input Timing Data setup time to DQS, DQS# Base (specification) tDS AC175 VREF @ 1 V / n s 2 5 0 – 2 0 0 ––––– p s 1 9 , 2 0 Data hold time from DQS, DQS# Base (specification) tDH AC175 1 5 0 – 1 0 0 ––––– p s 1 8 , 1 9 VREF @ 1 V / n s 2 5 0 – 2 0 0 ––––– p s 1 9 , 2 0 Data setup time to DQS, DQS# Base (specification) tDS AC150 19, 21 VREF @ 1 V / n s –––– 1 8 0 – 1 6 0 – p s 1 9 , 20,21 Data hold time from DQS, DQS# Base (specification) tDH AC150 19, 21 VREF @ 1 V / n s –––– 1 6 5 – 1 4 5 – p s 1 9 , 20, 21 Minimum data pulse width tDIPW 600 – 490 – 400 – 360 – ps 42 DQ Output Timing DQS, DQS# to DQ skew, per access tDQSQ – 200 – 150 – 125 – 100 ps DQ output hold time from DQS, DQS# tQH 0.38 – 0.38 – 0.38 – 0.38 – tCK (AVG) DQ Low-Z time from CK, CK# tLZ (DQ) –800 400 –600 300 –500 250 –450 225 ps 23 , 24 DQ High-Z time from CK, CK# tHZ (DQ) – 400 – 300 – 250 – 225 ps 23 , 24 DQ Strobe Input Timing DQS, DQS# falling setup to CK, CK# rising tDSS 0.2 – 0.2 – 0.2 – 0.18 – CK 26 DQS, DQS# falling hold from CK, CK# rising tDSH 0.2 – 0.2 – 0.2 – 0.18 – CK 26 DQS, DQS# differential WRITE preamble tWPRE 0.9 – 0.9 – 0.9 – 0.9 – CK DQS, DQS# differential WRITE postamble tWPST 0.3 – 0.3 – 0.3 – 0.3 – CK Table 53: Electrical Characteristics and AC Operating Conditions (Sheet 2 of 7) Notes: 1–8 apply to the entire table; notes appear on page 74 Parameter Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units NotesMin Max Min Max Min Max Min Max

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 69 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables DQ Strobe Output Timing DQS, DQS# rising to/from rising CK, CK# tDQSCK –400 400 –300 300 –255 255 –225 225 ps 24 DQS, DQS# rising to/from rising CK, CK# when DLL is disabled tDQSCK DLL_DIS 11 011 011 011 0 n s 2 7 DQS, DQS# differential output high time tQSH 0.38 – 0.38 – 0.40 – 0.40 – CK 22 DQS, DQS# differential output low time tQSL 0.38 – 0.38 – 0.40 – 0.40 – CK 22 DQS, DQS# Low-Z time (RL - 1) tLZ (DQS) –800 400 –600 300 –500 250 –450 225 ps 23 , 24 DQS, DQS# High-Z time (RL + BL/2) tHZ (DQS) – 400 – 300 – 250 – 225 ps 23 , 24 DQS, DQS# differential READ preamble tRPRE 0.9 Note 25 0.9 Note 25 0.9 Note 25 0.9 Note 25 CK 24 , 25 DQS, DQS# differential READ postamble tRPST 0.3 Note 28 0.3 Note 28 0.3 Note 28 0.3 Note 28 CK 24 , 28 Table 53: Electrical Characteristics and AC Operating Conditions (Sheet 3 of 7) Notes: 1–8 apply to the entire table; notes appear on page 74 Parameter Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units NotesMin Max Min Max Min Max Min Max

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 70 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Command and Address Timing DLL locking time tDLLK 512 – 512 – 512 – 512 – CK 29 CTRL, CMD, ADDR setup to CK,CK# Base (specification) tIS AC175 200 – 125 – 65 – 45 – ps 30, 31 VREF @ 1 V/ns 375 – 300 – 240 – 220 – ps 20, 31 CTRL, CMD, ADDR hold from CK,CK# Base (specification) tIH 275 – 200 – 140 – 120 – ps 30, 31 VREF @ 1 V/ns 375 – 300 – 240 – 220 – ps 20, 31 CTRL, CMD, ADDR setup to CK,CK# Base (specification) tIS AC150 –––– 1 9 0 – 1 7 0 – p s 2 1 , 30, 31 VREF @ 1 V / n s –––– 3 4 0 – 3 2 0 – p s 2 0 , 21, 31 Minimum CTRL, CMD, ADDR pulse width tIPW 900 – 780 – 620 – 560 – ps 42 ACTIVATE to internal READ or WRITE delay tRCD See “Speed Bin Tables” on page 63 for tRCD ns 32 PRECHARGE command period tRP See “Speed Bin Tables” on page 63 for tRP ns 32 ACTIVATE-to-PRECHARGE command period tRAS See “Speed Bin Tables” on page 63 for tRAS ns 32, 33 ACTIVATE-to-ACTIVATE command period tRC See “Speed Bin Tables” on page 63 for tRC ns 32 ACTIVATE-to- ACTIVATE minimum command period 1KB page size tRRD MIN = greater of 4CK or 10ns MIN = greater of 4CK or 7.5ns MIN = greater of 4CK or 6ns MIN = greater of 4CK or 6ns CK 32 2KB page size MIN = greater of 4CK or 10ns MIN = greater of 4CK or 7.5ns CK 32 Four ACTIVATE windows for 1KB page size tFAW 40 – 37.5 – 30 – 30 – ns 32 Four ACTIVATE windows for 2KB page size 50 – 50 – 45 – 40 – ns 32 Write recovery time tWR MIN = 15ns; MAX = n/a ns 32, 33, 34 Delay from start of internal WRITE transaction to internal READ command tWTR MIN = greater of 4CK or 7.5ns; MAX = n/a CK 32, 35 READ-to-PRECHARGE time tRTP MIN = greater of 4CK or 7.5ns; MAX = n/a CK 32, 33 CAS#-to-CAS# command delay tCCD MIN = 4CK; MAX = n/a CK Auto precharge write recovery + precharge time tDAL MIN = WR + tRP/tCK (AVG); MAX = n/a CK MODE REGISTER SET command cycle time tMRD MIN = 4CK; MAX = n/a CK MODE REGISTER SET command update delay tMOD MIN = greater of 12CK or 15ns; MAX = n/a CK MULTIPURPOSE REGISTER READ burst end to mode register set for multipurpose register exit tMPRR MIN = 1CK; MAX = n/a CK Table 53: Electrical Characteristics and AC Operating Conditions (Sheet 4 of 7) Notes: 1–8 apply to the entire table; notes appear on page 74 Parameter Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units NotesMin Max Min Max Min Max Min Max

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 71 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Calibration Timing ZQCL command: Long calibration time POWER-UP and RESET operation tZQINIT 512 – 512 – 512 – 512 – CK Normal operation tZQOPER 256 – 256 – 256 – 256 – CK ZQCS command: Short calibration time tZQCS 64 – 64 – 64 – 64 – CK Initialization and Reset Timing Exit reset from CKE HIGH to a valid command tXPR MIN = greater of 5CK or tRFC + 10ns; MAX = n/a CK Begin power supply ramp to power supplies stable tVDDPR MIN = n/a; MAX = 200 ms RESET# LOW to power supplies stable tRPS MIN = 0; MAX = 200 ms RESET# LOW to I/O and RTT High-Z tIOz MIN = n/a; MAX = 20 ns 36 Refresh Timing REFRESH-to-ACTIVATE or REFRESH command period tRFC MIN = 110; MAX = 9 × tREFI (REFRESH-to-REFRESH command period) ns Maximum refresh period TC = 0°C to 85°C – 64 (1X) ms 37 TC = >85°C to 95°C 32 (2X) ms 37 Maximum average periodic refresh TC = 0°C to 85°C tREFI 7.8 (64ms/8,192) µs 37 TC = >85°C to 95°C 3.9 (32ms/8,192) µs 37 Self Refresh Timing Exit self refresh to commands not requiring a locked DLL tXS MIN = greater of 5CK or tRFC + 10ns; MAX = n/a CK Exit self refresh to commands requiring a locked DLL tXSDLL MIN = tDLLK (MIN); MAX = n/a CK 29 Minimum CKE low pulse width for self refresh entry to self refresh exit timing tCKESR MIN = tCKE (MIN) + CK; MAX = n/a CK Valid clocks after self refresh entry or power- down entry tCKSRE MIN = greater of 5CK or 10ns; MAX = n/a CK Valid clocks before self refresh exit, power- down exit, or reset exit tCKSRX MIN = greater of 5CK or 10ns; MAX = n/a CK Table 53: Electrical Characteristics and AC Operating Conditions (Sheet 5 of 7) Notes: 1–8 apply to the entire table; notes appear on page 74 Parameter Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units NotesMin Max Min Max Min Max Min Max

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 72 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Power-Down Timing CKE MIN pulse width tCKE (MIN) Greater of 3CK or 7.5ns Greater of 3CK or 5.625ns Greater of 3CK or 5.625ns Greater of 3CK or 5ns CK Command pass disable delay tCPDED MIN = 1; MAX = n/a CK Power-down entry to power-down exit timing tPD MIN = tCKE (MIN); MAX = 9 × tREFI CK Begin power-down period prior to CKE registered HIGH tANPD WL - 1CK CK Power-down entry period: ODT either synchronous or asynchronous PDE Greater of tANPD or tRFC - REFRESH command to CKE LOW time CK Power-down exit period: ODT either synchronous or asynchronous PDX tANPD + tXPDLL CK Power-Down Entry Minimum Timing ACTIVATE command to power-down entry tACTPDEN MIN = 1 CK PRECHARGE/PRECHARGE ALL command to power-down entry tPRPDEN MIN = 1 CK REFRESH command to power-down entry tREFPDEN MIN = 1 CK 38 MRS command to power-down entry tMRSPDEN MIN = tMOD (MIN) CK READ/READ with auto precharge command to power-down entry tRDPDEN MIN = RL + 4 + 1 CK WRITE command to power-down entry BL8 (OTF , MRS) BC4OTF tWRPDEN MIN = WL + 4 + tWR/tCK (AVG) CK BC4MRS tWRPDEN MIN = WL + 2 + tWR/tCK (AVG) CK WRITE with auto precharge command to power-down entry BL8 (OTF , MRS) BC4OTF tWRAPDEN MIN = WL + 4 + WR + 1 CK BC4MRS tWRAPDEN MIN = WL + 2 + WR + 1 CK Power-Down Exit Timing DLL on, any valid command, or DLL off to commands not requiring locked DLL tXP MIN = greater of 3CK or 7.5ns; MAX = n/a MIN = greater of 3CK or 6ns; MAX = n/a CK Precharge power-down with DLL off to commands requiring a locked DLL tXPDLL MIN = greater of 10CK or 24ns; MAX = n/a CK 29 Table 53: Electrical Characteristics and AC Operating Conditions (Sheet 6 of 7) Notes: 1–8 apply to the entire table; notes appear on page 74 Parameter Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units NotesMin Max Min Max Min Max Min Max

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 73 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables ODT Timing RTT synchronous turn-on delay ODTL on CWL + AL - 2CK CK 39 RTT synchronous turn-off delay ODTL off CWL + AL - 2CK CK 41 RTT turn-on from ODTL on reference tAON –400 400 –300 300 –250 250 –225 225 ps 24 , 39 Asynchronous RTT turn-on delay (power-down with DLL off) tAONPD MIN = 1; MAX = 9 ns 39 Asynchronous RTT turn-off delay (power-down with DLL off) tAOFPD MIN = 1; MAX = 9 ns 41 ODT HIGH time with WRITE command and BL8 ODTH8 MIN = 6; MAX = n/a CK ODT HIGH time without WRITE command or with WRITE command and BC4 ODTH4 MIN = 4; MAX = n/a CK Dynamic ODT Timing RTT_NOM-to-RTT_WR change skew ODTL CNW WL - 2CK CK RTT_WR-to-RTT_NOM change skew - BC4 ODTL CNW4 4CK + ODTL off CK RTT_WR-to-RTT_NOM change skew - BL8 ODTL CNW8 6CK + ODTL off CK Write Leveling Timing First DQS, DQS# rising edge tWLMRD 40 – 40 – 40 – 40 – CK DQS, DQS# delay tWLDQSEN 25 – 25 – 25 – 25 – CK Write leveling setup from rising CK, CK# crossing to rising DQS, DQS# crossing tWLS 325 – 245 – 195 – 163 – ps Write leveling hold from rising DQS, DQS# crossing to rising CK, CK# crossing tWLH 325 – 245 – 195 – 163 – ps Write leveling output delay tW L O 0909090 7 . 5 n s Write leveling output error tW L O E 02020202 n s Table 53: Electrical Characteristics and AC Operating Conditions (Sheet 7 of 7) Notes: 1–8 apply to the entire table; notes appear on page 74 Parameter Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units NotesMin Max Min Max Min Max Min Max

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 74 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Notes 1. Parameters are applicable with 0°C ≤ TC ≤ +95°C and VDD/VDDQ = +1.5V ±0.075V . 2. All voltages are referenced to V SS. 3. Output timings are only valid for R ON34 output buffer selection. 4. Unit “ tCK (AVG)” represents the actual tCK (AVG) of the input clock under operation. Unit “CK” represents one clock cycle of the input clock, counting the actual clock edges. 5. AC timing and I DD tests may use a VIL-to-VIH swing of up to 900mV in the test envi- ronment, but input timing is still referenced to VREF (except tIS, tIH, tDS, and tDH use the AC/DC trip points and CK, CK# and DQS, DQS# use their crossing points). The minimum slew rate for the input signals used to test the device is 1 V/ns for single- ended inputs and 2 V/ns for differential inputs in the range between VIL(AC) and VIH(AC). 6. All timings that use time-based values (ns, µs, ms) should use tCK (AVG) to determine the correct number of clocks (Table 53 on page 67 uses “CK” or “tCK [AVG]” inter- changeably). In the case of noninteger results, all minimum limits are to be rounded up to the nearest whole integer, and all maximum limits are to be rounded down to the nearest whole integer. 7. The use of “strobe” or “DQS DIFF” refers to the DQS and DQS# differential crossing point when DQS is the rising edge. The use of “clock” or “CK” refers to the CK and CK# differential crossing point when CK is the rising edge. 8. This output load is used for all AC timing (except ODT reference timing) and slew rates. The actual test load may be different. The output signal voltage reference point is V DDQ/2 for single-ended signals and the crossing point for differential signals (see Figure 32 on page 60). 9. When operating in DLL disable mode, Micr on does not warrant compliance with nor- mal mode timings or functionality. 10. The clock’ s tCK (AVG) is the average clock over any 200 consecutive clocks and tCK(AVG) MIN is the smallest clock rate allowed, with the exception of a deviation due to clock jitter. Input clock jitter is allowed provided it does not exceed values specified and must be of a random Gaussian distribution in nature. 11. Spread spectrum is not included in the ji tter specification values. However, the input clock can accommodate spread-spectrum at a sweep rate in the range of 20–60 kHz with an additional 1 percent of tCK (AVG) as a long-term jitter component; however, the spread-spectrum may not use a clock rate below tCK (AVG) MIN. 12. The clock’ s tCH (AVG) and tCL (AVG) are the average half clock period over any 200 consecutive clocks and is the smallest clock half period allowed, with the exception of a deviation due to clock jitter. Input clock jitter is allowed provided it does not exceed values specified and must be of a random Gaussian distribution in nature. 13. The period jitter ( tJITPER) is the maximum deviation in the clock period from the aver- age or nominal clock. It is allowed in either the positive or negative direction. 14. tCH(ABS) is the absolute instantaneous clock high pulse width as measured from one rising edge to the following falling edge. 15. tCL(ABS) is the absolute instantaneous clock low pulse width as measured from one falling edge to the following rising edge. 16. The cycle-to-cycle jitter ( tJITCC) is the amount the clock period can deviate from one cycle to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL locking time.

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 75 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables 17. The cumulative jitter error ( tERRnPER), where n is the number of clocks between 2 and 50, is the amount of clock time allowed to accumulate consecutively away from the average clock over n number of clock cycles. 18. tDS (base) and tDH (base) values are for a single-ended 1 V/ns DQ slew rate and 2 V/ns differential DQS, DQS# slew rate. 19. These parameters are meas ured from a data signal (DM, DQ0, DQ1, and so forth) transition edge to its respective data strobe signal (DQS, DQS#) crossing. 20. The setup and hold times ar e listed converting the base specification values (to which derating tables apply) to VREF when the slew rate is 1 V/ns. These values, with a slew rate of 1 V/ns, are for reference only. 21. Special setup and hold derating and different tVAC numbers apply when using 150mV AC threshold. 22. When the device is operated with input cl ock jitter, this parameter needs to be der- ated by the actual tJITPER of the input clock (output deratings are relative to the SDRAM input clock). 23. Single-ended signal parameter. 24. The DRAM output timing is aligned to the nominal or average clock. Most output parameters must be derated by the actual jitter error when input clock jitter is present, even when within specification. This results in each parameter becoming larger. The following parameters are required to be derated by subtracting tERR10PER (MAX): tDQSCK (MIN), tLZ (DQS) MIN, tLZ (DQ) MIN, and tAON (MIN). The following parameters are required to be derated by subtracting tERR10PER (MIN): tDQSCK (MAX), tHZ (MAX), tLZ (DQS) MAX, tLZ (DQ) MAX, and tAON (MAX). The parameter tRPRE (MIN) is derated by subtracting tJITPER (MAX), while tRPRE (MAX) is derated by subtracting tJITPER (MIN). 25. The maximum preamble is bound by tLZDQS (MAX). 26. These parameters ar e measured from a data strobe signal (DQS, DQS#) crossing to its respective clock signal (CK, CK#) crossing. The specification values are not affected by the amount of clock jitter applied, as these are relative to the clock signal crossing. These parameters should be met whether clock jitter is present. 27. The tDQSCK DLL_DIS parameter begins CL + AL - 1 cycles after the READ command. 28. The maximum postamble is bound by tHZDQS (MAX). 29. Commands requiring a locked DLL are: READ (and RDAP) and synchronous ODT commands. In addition, after any change of latency tXPDLL, timing must be met. 30. tIS (base) and tIH (base) values are for a single-ended 1 V/ns control/command/ address slew rate and 2 V/ns CK, CK# differential slew rate. 31. These parameters are meas ured from a command/address signal transition edge to its respective clock (CK, CK#) signal crossing. The specification values are not affected by the amount of clock jitter applied as the setup and hold times are relative to the clock signal crossing that latches the command/address. These parameters should be met whether clock jitter is present. 32. For these parameters, the DDR3 SDRAM device supports tnPARAM (nCK) = RU(tPARAM [ns]/tCK[AVG] [ns]), assuming all input clock jitter specifications are sat- isfied. For example, the device will support tnRP (nCK) = RU(tRP/tCK[AVG]) if all input clock jitter specifications are met. This means for DDR3-800 6-6-6, of which tRP = 15ns, the device will support tnRP = RU(tRP/tCK[AVG]) = 6 as long as the input clock jitter specifications are met. That is, the PRECHARGE command at T0 and the ACTIVATE command at T0 + 6 are valid even if six clocks are less than 15ns due to input clock jitter. 33. During READs and WRITEs with auto prec harge, the DDR3 SDRAM will hold off the internal PRECHARGE command until tRAS (MIN) has been satisfied.

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 76 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables 34. When operating in DLL disable mode, the greater of 4CK or 15ns is satisfied for tWR. 35. The start of the write recovery time is defined as follows: – For BL8 (fixed by MRS and OTF): Rising clock edge four clock cycles after WL – For BC4 (OTF): Rising clock edge four clock cycles after WL – For BC4 (fixed by MRS): Rising cl ock edge two clock cycles after WL 36. RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in High-Z. Until RESET# is LOW, the outputs are at risk of driving and could result in excessive current, depending on bus activity. 37. The refresh period is 64ms. This equates to an average refresh rate of 7.8125µs. How- ever, nine REFRESH commands must be asserted at least once every 70.3µs. 38. Although CKE is allowed to be registered LOW after a REFRESH command when tREFPDEN (MIN) is satisfied, there are cases where additional time such as tXPDLL (MIN) is required. 39. ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins to turn on. ODT turn-on time maximum is when the ODT resistance is fully on. The ODT reference load is shown in Figure 24 on page 49. 40. Half-clock output parameters must be derated by the actual tERR10PER and tJITDTY when input clock jitter is present. This results in each parameter becoming larger. The parameters tADC (MIN) and tAOF (MIN) are each required to be derated by sub- tracting both tERR10PER (MAX) and tJITDTY (MAX). The parameters tADC (MAX) and tAOF (MAX) are required to be derated by subtracting both tERR10PER (MAX) and tJITDTY (MAX). 41. ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT turn-off time maximum is when the DRAM buffer is in High-Z. The ODT refer- ence load is shown in Figure 25 on page 51. This output load is used for ODT timings (see Figure 32 on page 60). 42. Pulse width of a input signal is defined as the width between the first crossing of V REF(DC) and the consecutive crossing of VREF(DC).

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 77 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Command and Address Setup, Hold, and Derating The total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS (base) and tIH (base) values (see Table 54; values come from Table 53 on page 67) to the ΔtIS and ΔtIH derating values (see Table 55 on page 78 and Table 56 on page 78), respectively. Example: tIS (total setup time) = tIS (base) + ΔtIS. For a valid tran- sition, the input signal has to remain above/below VIH(AC)/VIL(AC) for some time tVAC (see Table 56 on page 78). Although the total setup time for slow slew rates might be negative (for example, a valid input signal will not have reached VIH[AC]/VIL[AC] at the time of the rising clock transi- tion), a valid input signal is still required to complete the transition and to reach VIH(AC)/ VIL(AC) (see Figure 17 on page 42 for input signal requirements). For slew rates which fall between the values listed in Table 56 on page 78 and Table 57 on page 79, the derating values may be obtained by linear interpolation. Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC) MIN. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC) MAX. If the actual signal is always earlier than the nominal slew rate line between the shaded “VREF(DC)-to-AC region,” use the nominal slew rate for derating value (see Figure 35 on page 80). If the actual signal is later than the nominal slew rate line anywhere between the shaded “V REF(DC)-to-AC region,” the slew rate of a tangent line to the actual signal from the AC level to the DC level is used for derating value (see Figure 37 on page 82). Hold ( tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC) MAX and the first crossing of VREF(DC). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC) MIN and the first crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line between the shaded “DC-to-VREF(DC) region,” use the nominal slew rate for derating value (see Figure 36 on page 81). If the actual signal is earlier than the nominal slew rate line anywhere between the shaded “DC-to-V REF(DC) region,” the slew rate of a tangent line to the actual signal from the DC level to the VREF(DC) level is used for derating value (see Figure 38 on page 83). Table 54: Command and Address Setup and Hold Va lues Referenced at 1 V/ns – AC/DC-Based Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units Reference tIS (base) 200 125 65 45 ps V IH(AC)/VIL(AC) tIH (base) 275 200 140 120 ps V IH(DC)/VIL(DC) tIS (base): AC150 n/a n/a 190 170 ps V IH(AC)/VIL(AC)

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 78 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Table 55: DDR3-800, DDR3-1066, DDR3-1333, and DDR3-1600 Derating Values for tIS/tIH – AC/DC- Based AC175 threshold ΔtIS, ΔtIH Derating (ps) – AC/DC-Based AC175 Threshold: VIH(AC) = VREF(DC) + 175mV, VIL(AC) = VREF(DC) - 175mV CMD/ ADDR Slew Rate V/ns CK, CK# Differential Slew Rate ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIH ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH 2.0 88 50 88 50 88 50 96 58 104 66 112 74 120 84 128 100 1 . 5 5 93 45 93 45 93 46 74 27 55 08 35 89 16 89 98 4 1 . 0 00000088 1 6 1 6 2 4 2 4 3 2 3 4 4 0 5 0 0 . 9 – 2– 4– 2– 4– 2– 4 6 4 1 41 22 22 03 0 3 0 3 8 4 6 0.8 –6 –10 –6 –10 –6 –10 2 –2 10 6 18 14 26 24 34 40 0.7 –11 –16 –11 –16 –11 –16 –3 –8 5 0 13 8 21 18 29 34 0.6 –17 –26 –17 –26 –17 –26 –9 –18 –1 –10 7 –2 15 8 23 24 Table 56: DDR3-1333 and DDR3-1600 Derating Values for tIS/tIH – AC/DC-Based AC150 threshold ΔtIS, ΔtIH Derating (ps) – AC/DC-Based AC150 Threshold: VIH(AC) = VREF(DC) + 150mV, VIL(AC) = VREF(DC) - 150mV CMD/ ADDR Slew Rate V/ns CK, CK# Differential Slew Rate ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIH ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH 2 . 0 7 55 07 55 07 55 08 35 89 16 69 97 4 1 0 7 8 4 1 1 5 1 0 0 1 . 5 5 03 45 03 45 03 45 84 26 65 07 45 88 26 89 08 4 1 . 0 00000088 1 6 1 6 2 4 2 4 3 2 3 4 4 0 5 0 0.9 0 –4 0 –4 0 –4 8 4 16 12 24 20 32 30 40 46 0 . 8 0– 1 00– 1 00– 1 08 – 21 6 6 2 41 43 22 44 04 0 0.7 0 –16 0 –16 0 –16 8 –8 16 0 24 8 32 18 40 34 0.6 –1 –26 –1 –26 –1 –26 7 –18 15 –10 23 –2 31 8 39 24 0.5 –10 –40 –10 –40 –10 –40 –2 –32 6 –24 14 –16 22 –6 30 10

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 79 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Table 57: Minimum Required Time tVAC Above VIH(AC) for Valid Transition Below VIL(AC) Slew Rate (V/ns) tVAC at 175mV (ps) tVAC at 150mV (ps) >2.0 75 175 2.0 57 170 1.5 50 167 1.0 38 163 0.9 34 162 0.8 29 161 0.7 22 159 0.6 13 155 0.5 0 150 <0.5 0 150

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 80 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Figure 35: Nominal Slew Rate and tVAC for tIS (Command and Address – Clock) Notes: 1. Both the clock and the strobe are drawn on different time scales. VSS Setup slew rate rising signal Setup slew rate falling signal ΔTF ΔTR VDDQ VIH(AC) MIN VIH(DC) MIN VREF(DC) VIL(DC) MAX VIL(DC) MAX Nominal slew rate VREF to AC region tVAC tVAC DQS DQS# CK# CK tIS tIH tIS tIH Nominal slew rate VREF to AC region VREF(DC) - VIL(AC) MAX ΔTF VIH(AC) MIN - VREF(DC) ΔTR

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 81 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Figure 36: Nominal Slew Rate for tIH (Command and Address – Clock) Notes: 1. Both the clock and the strobe are drawn on different time scales. VSS Hold slew rate falling signal Hold slew rate rising signal ΔTR ΔTF = = VDDQ VIH(AC) MIN VIH(DC) MIN VREF(DC) VIL(DC) MAX VIL(AC) MAX Nominal slew rate DC to VREF region DQS DQS# CK# CK tIS tIH tIS tIH DC to VREF region Nominal slew rate VREF(DC) - VIL(DC) MAX ΔTR VIH(DC) MIN - VREF(DC) ΔTF

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 82 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Figure 37: Tangent Line for tIS (Command and Address – Clock) Notes: 1. Both the clock and the strobe are drawn on different time scales. VSS Setup slew rate rising signal Setup slew rate falling signal ΔTF ΔTR VDDQ VIH(AC) MIN VIH(DC) MIN VREF(DC) VIL(DC) MAX VIL(AC) MAX Tangent line VREF to AC region Nominal line tVAC tVAC DQS DQS# CK# CK tIS tIH tIS tIH VREF to AC region Tangent line Nominal line Tangent line (VIH[DC] MIN - VREF[DC]) ΔTR Tangent line (VREF[DC] - VIL[AC] MAX) ΔTF

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 83 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Figure 38: Tangent Line for tIH (Command and Address – Clock) Notes: 1. Both the clock and the strobe are drawn on different time scales. VSS Hold slew rate falling signal ΔTR VDDQ VIH(AC) MIN VIH(DC) MIN VREF(DC) VIL(DC) MAX VIL(AC) MAX Tangent line DC to VREF region Hold slew rate rising signal = DQS DQS# CK# CK tIS tIH tIS tIH DC to VREF region Tangent line Nominal line Nominal line ΔTR Tangent line (VREF[DC] - VIL[DC] MAX) ΔTR Tangent line (VIH[DC] MIN - VREF[DC]) ΔTF

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 84 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Data Setup, Hold, and Derating The total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS (base) and tDH (base) values (see Table 58; values come from Table 53 on page 67) to the ΔtDS and ΔtDH derating values (see Table 59 on page 85), respectively. Example: tDS (total setup time) = tDS (base) + ΔtDS. For a valid transition, the input signal has to remain above/below VIH(AC)/VIL(AC) for some time tVAC (see Table 61 on page 86). Although the total setup time for slow slew rates might be negative (for example, a valid input signal will not have reached VIH[AC]/VIL[AC]) at the time of the rising clock transi- tion), a valid input signal is still required to complete the transition and to reach VIH/ VIL(AC). For slew rates which fall between the values listed in Table 59 on page 85, the derating values may obtained by linear interpolation. Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC) MIN. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC) MAX. If the actual signal is always earlier than the nominal slew rate line between the shaded “VREF(DC)-to-AC region,” use the nominal slew rate for derating value (see Figure 39 on page 87). If the actual signal is later than the nominal slew rate line anywhere between the shaded “V REF(DC)-to-AC region,” the slew rate of a tangent line to the actual signal from the AC level to the DC level is used for derating value (see Figure 41 on page 89). Hold ( tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC) MAX and the first crossing of VREF(DC). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC) MIN and the first crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line between the shaded “DC-to-VREF(DC) region,” use the nominal slew rate for derating value (see Figure 40 on page 88). If the actual signal is earlier than the nominal slew rate line anywhere between the shaded “DC-to-V REF(DC) region,” the slew rate of a tangent line to the actual signal from the “DC-to-VREF(DC) region” is used for derating value (see Figure 42 on page 90). Table 58: Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units Reference tDS AC175 (base) 75 25 – – ps V IH(AC)/VIL(AC) tDH AC175 (base) 150 100 – – ps V IH(DC)/VIL(DC) tDS AC150 (base) – – 30 10 ps V IH(AC)/VIL(AC) tDH AC150 (base) – – 65 45 ps V IH(DC)/VIL(DC)

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 85 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Table 59: DDR3-800, DDR3-1066, DDR3-1333, and DDR3-1600 Derating Values for tDS/tDH – AC/DC- Based AC175 threshold; shaded cells indicate slew rate combinations not supported ΔtDS, ΔtDH Derating (ps) – AC/DC-Based DQ Slew Rate V/ns DQS, DQS# Differential Slew Rate ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH 2 . 0 8 85 08 85 08 85 0 1 . 5 5 93 45 93 45 93 46 74 2 1 . 0 00000088 1 6 1 6 0.9 –2 –4 –2 –4 6 4 14 12 22 20 0.8 –6 –10 2 –2 10 6 18 14 26 24 0.7 – 3 – 8 5 0 1 3 8 2 11 82 93 4 0.6 –1 –10 7 –2 15 8 23 24 0.5 –11 –16 –2 –6 5 10 Table 60: DDR3-1333and DDR3-1600 Derating Values for tDS/tDH – AC/DC-Based AC150 threshold; shaded cells indicate slew rate combinations not supported ΔtDS, ΔtDH Derating (ps) – AC/DC-Based CMD/ ADDR Slew Rate V/ns DQS, DQS# Differential Slew Rate ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIH ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH 2 . 0 7 55 07 55 07 55 0 1 . 5 5 03 45 03 45 03 45 84 2 1 . 0 00000088 1 6 1 6 0.9 0 –4 0 –4 8 4 16 12 24 20 0.8 0 – 1 0 8– 2 1 662 4 1 4 3 2 2 4 0.7 8 –8 16 0 24 8 32 18 40 34 0.6 15 –10 23 –2 31 8 39 24 0.5 1 4 – 1 6 2 2– 63 01 0 0.4 7 –26 15 –10

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 86 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Table 61: Required Time tVAC Above VIH(AC) (Below VIL[AC]) for Valid Transition Slew Rate (V/ns) tVAC at 175mV (ps) tVAC at 150mV (ps) Min Min >2.0 75 175 2.0 57 170 1.5 50 167 1.0 38 163 0.9 34 162 0.8 29 161 0.7 22 159 0.6 13 155 0.5 0 150 <0.5 0 150

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 87 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Figure 39: Nominal Slew Rate and tVAC for tDS (DQ – Strobe) Notes: 1. Both the clock and the strobe are drawn on different time scales. VSS Setup slew rate rising signal Setup slew rate falling signal ΔTF ΔTR = = VDDQ VIH(AC) MIN VIH(DC) MIN VREF(DC) VIL(DC) MAX VIL(AC) MAX Nominal slew rate VREF to AC region tVAC tVAC tDHtDS DQS DQS# tDHtDS CK# CK VREF to AC region Nominal slew rate VIH(AC) MIN - VREF(DC) ΔTR VREF(DC) - VIL(AC) MAX ΔTF

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 88 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Figure 40: Nominal Slew Rate for tDH (DQ – Strobe) Notes: 1. Both the clock and the strobe are drawn on different time scales. VSS Hold slew rate falling signal Hold slew rate rising signal ΔTR ΔTF VDDQ VIH(AC) MIN VIH(DC) MIN VREF(DC) VIL(DC) MAX VIL(AC) MAX Nominal slew rateDC to VREF region tDHtDS DQS DQS# tDHtDS CK# CK DC to VREF region Nominal slew rate VREF(DC) - VIL(DC) MAX ΔTR VIH(DC) MIN - VREF(DC) ΔTF

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 89 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Figure 41: Tangent Line for tDS (DQ – Strobe) Notes: 1. Both the clock and the strobe are drawn on different time scales. VSS Setup slew rate rising signal Setup slew rate falling signal ΔTF ΔTR VDDQ VIH(AC) MIN VIH(DC) MIN VREF(DC) VIL(DC) MAX VIL(AC) MAX Tangent line VREF to AC region Nominal line tVAC tVAC tDHtDS DQS DQS# tDHtDS CK# CK VREF to AC region Tangent line Nominal line ΔTR Tangent line (VREF[DC] - VIL[AC] MAX) ΔTF Tangent line (VIH[AC] MIN - VREF[DC])

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_3.fm - Rev. D 8/1/08 EN 90 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Figure 42: Tangent Line for tDH (DQ – Strobe) Notes: 1. Both the clock and the strobe are drawn on different time scales. VSS Hold slew rate falling signal ΔTFΔTR VDDQ VIH(AC) MIN VIH(DC) MIN VREF(DC) VIL(DC) MAX VIL(AC) MAX Tangent line DC to VREF region Hold slew rate rising signal = DQS DQS# CK# CK DC to VREF region Tangent line Nominal line Nominal line Tangent line (VIH[DC] MIN - VREF[DC]) ΔTF Tangent line (VREF[DC] - VIL[DC] MAX) ΔTR tDS tDH tDS tDH

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 91 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Commands Commands Truth Tables Notes: 1. Commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock. The MSB of BA, RA, and CA are device-density and configuration-dependent. 2. RESET# is LOW enabled and used only for asynch ronous reset. Thus, RESET# must be held HIGH during any normal operation. 3. The state of ODT does not affect the states described in this table. Table 62: Truth Table – Command Notes 1–5 apply to the entire table Function Symbol CKE CS# RAS# CAS# WE# BA [2:0] An A12 A10 A[11, 9:0] Notes Prev Cycle Next Cycle MODE REGISTER SET MRS H H L L L L BA OP code REFRESH REF H H L L L H V V V V V Self refresh entry SRE H L L L L H V V V V V 6 Self refresh exit SRX L H H V V V V V V V V 6, 7 LH HH Single-bank PRECHARGE PRE H H L L H L BA V V L V PRECHARGE all banks PREA H H L L H L V V V H V Bank ACTIVATE ACT H H L L H H BA Row address (RA) WRITE BL8MRS, BC4MRS WR H H L H L L BA RFU V L CA 8 BC4OTF WRS4 H H L H L L BA RFU L L CA 8 BL8OTF WRS8 H H L H L L BA RFU H L CA 8 WRITE with auto precharge BL8MRS, BC4MRS WRAP H H L H L L BA RFU V H CA 8 BC4OTF WRAPS4 H H L H L L BA RFU L H CA 8 BL8OTF WRAPS8 H H L H L L BA RFU H H CA 8 READ BL8MRS, BC4MRS RD H H L H L H BA RFU V L CA 8 BC4OTF RDS4 H H L H L H BA RFU L L CA 8 BL8OTF RDS8 H H L H L H BA RFU H L CA 8 READ with auto precharge BL8MRS, BC4MRS RDAP H H L H L H BA RFU V H CA 8 BC4OTF RDAPS4 H H L H L H BA RFU L H CA 8 BL8OTF RDAPS8 H H L H L H BA RFU H H CA 8 NO OPERATION NOP H H L H H H V V V V V 9 Device DESELECTED DES H H H X X X X X X X X 10 Power-down entry PDE H L L H H H V V V V V 6 HV V V Power-down exit PDX L H L H H H V V V V V 6, 11 HV V V ZQ CALIBRATION LONG ZQCL H H L H H L X X X H X 12 ZQ CALIBRATION SHORT ZQCS H H L H H L X X X L X

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 92 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Commands 4. Operations apply to the bank defined by the bank address. For MRS, BA selects one of four mode registers. 5. “V” means “H” or “L” (a defined logi c level), and “X” means “Don’t Care.” 6. See Table 63 for additional in formation on CKE transition. 7. Self refresh exit is asynchronous. 8. Burst READs or WRITEs cannot be terminated or interrupted. MRS (fixed) and OTF BL/BC are defined in MR0. 9. The purpose of the NOP command is to prev ent the DRAM from registering any unwanted commands. A NOP will not terminate an operation that is executing. 10. The DES and NOP commands perform similarly. 11. The power-down mode does not perform any REFRESH operations. 12. ZQ CALIBRATION LONG is used for either ZQ INIT (first ZQCL command during initialization) or ZQOPER (ZQCL command after initialization). Notes: 1. All states and se quences not shown are illegal or reserved unless explicitly described else- where in this document. 2. tCKE (MIN) means CKE must be registered at multiple consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the required number of registration clocks. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + tCKE (MIN) + tIH. 3. Current state = The state of the DR AM immediately prior to clock edge n. 4. CKE ( n) is the logic state of CKE at clock edge n; CKE (n - 1) was the state of CKE at the pre- vious clock edge. 5. COMMAND is the command registered at the clock edge (must be a legal command as defined in Table 62 on page 91). Action is a result of COMMAND. ODT does not affect the states described in this table and is not listed. 6. Idle state = All banks are closed, no data burst s are in progress, CKE is HIGH, and all timings from previous operations are satisfied. All self refresh exit and power-down exit parameters are also satisfied. DESELECT (DES) The DES command (CS# HIGH) prevents new commands from being executed by the DRAM. Operations already in progress are not affected. Table 63: Truth Table – CKE Notes 1–2 apply to the entire table; see Table 62 on page 91 for additional command details Current State3 CKE Command5 (RAS#, CAS#, WE#, CS#) Action5 Notes Previous Cycle4 (n -1 ) Present Cycle4 (n) Power-down L L “Don’t Care” Maintain power-down L H DES or NOP Power-down exit Self refresh L L “Don’t Care” Maintain self refresh L H DES or NOP Self refresh exit Bank(s) active H L DES or NO P Active power-down entry Reading H L DES or NOP Power-down entry Writing H L DES or NOP Power-down entry Precharging H L DES or NOP Power-down entry Refreshing H L DES or NOP Precharge power-down entry All banks idle H L DES or NOP P recharge power-down entry 6 H L REFRESH Self refresh

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 93 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Commands NO OPERATION (NOP) The NOP command (CS# LOW) prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. ZQ CALIBRATION ZQ CALIBRATION LONG (ZQCL) The ZQCL command is used to perform the initial calibration during a power-up initial- ization and reset sequence (see Figure 51 on page 107). This command may be issued at any time by the controller depending on the system environment. The ZQCL command triggers the calibration engine inside the DRAM. After calibration is achieved, the cali- brated values are transferred from the calibration engine to the DRAM I/O, which are reflected as updated R ON and ODT values. The DRAM is allowed a timing window defined by either tZQINIT or tZQOPER to perform the full calibration and transfer of values. When ZQCL is issued during the initialization sequence, the timing parameter tZQINIT must be satisfied. When initialization is complete, subsequent ZQCL commands require the timing parameter tZQOPER to be satisfied. ZQ CALIBRATION SHORT (ZQCS) The ZQCS command is used to perform periodic calibrations to account for small voltage and temperature variations. The shorter timing window is provided to perform the reduced calibration and transfer of values as defined by timing parameter tZQCS. A ZQCS command can effectively correct a minimum of 0.5 percent RON and RTT impedance error within 64 clock cycles, assuming the maximum sensitivities specified in Table 40 on page 56 and Table 41 on page 57. ACTIVATE The ACTIVATE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA[2:0] inputs selects the bank, and the address provided on inputs A[n:0] selects the row. This row remains open (or active) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The address provided on inputs A[2:0] selects the starting column address depending on the burst length and burst type selected (see Table 68 on page 111 for additional information). The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst. If auto precharge is not selected, the row will remain open for subsequent accesses. The value on input A12 (if enabled in the mode register) when the READ command is issued determines whether BC4 (chop) or BL8 is used. After a READ command is issued, the READ burst may not be interrupted. A summary of READ commands is shown in Table 64 on page 94.

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 94 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Commands WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA[2:0] inputs selects the bank. The value on input A10 determines whether or not auto precharge is used. The value on input A12 (if enabled in the MR) when the WRITE command is issued determines whether BC4 (chop) or BL8 is used. The WRITE command summary is shown in Table 65. Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to memory. If the DM signal is registered HIGH, the corresponding data inputs will be ignored and a WRITE will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or in all banks. The bank(s) are available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued, except in the case of concurrent auto precharge. A READ or WRITE command to a different bank is allowed during concurrent auto precharge as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Input A10 determines whether one or all banks are precharged. In the case where only one bank is precharged, inputs BA[2:0] select the bank; otherwise, BA[2:0] are treated as “Don’t Care.” After a bank is precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command is treated as a NOP if Table 64: READ Command Summary Function Symbol CKE CS# RAS# CAS# WE# BA [3:0] An A12 A10 A[11, 9:0] Previous Cycle Next Cycle READ BL8MRS, BC4MRS RD H L H L H BA RFU V L CA BC4OTF RDS4 H L H L H BA RFU L L CA BL8OTF RDS8 H L H L H BA RFU H L CA READ with auto precharge BL8MRS, BC4MRS RDAP H L H L H BA RFU V H CA BC4OTF RDAPS4 H L H L H BA RFU L H CA BL8OTF RDAPS8 H L H L H BA RFU H H CA Table 65: WRITE Command Summary Function Symbol CKE CS# RAS# CAS# WE# BA [3:0] An A12 A10 A[11, 9:0] Prev Cycle Next Cycle WRITE BL8MRS, BC4MRS WR H L H L L BA RFU V L CA BC4OTF WRS4 H L H L L BA RFU L L CA BL8OTF WRS8 H L H L L BA RFU H L CA WRITE with auto precharge BL8MRS, BC4MRS WRAP H L H L L BA RFU V H CA BC4OTF WRAPS4 H L H L L BA RFU L H CA BL8OTF WRAPS8 H L H L L BA RFU H H CA

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 95 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Commands there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. However, the precharge period is determined by the last PRECHARGE command issued to the bank. REFRESH REFRESH is used during normal operation of the DRAM and is analogous to CAS#- before-RAS# (CBR) refresh or auto refresh. This command is nonpersistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a “Don’t Care” during a REFRESH command. The DRAM requires REFRESH cycles at an average interval of 7.8µs (maximum when T C ≤ 85°C or 3.9µs MAX when TC ≤ 95°C). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight REFRESH commands can be posted to any given DRAM, meaning that the maximum absolute interval between any REFRESH command and the next REFRESH command is nine times the maximum average interval refresh rate. The REFRESH period begins when the REFRESH command is registered and ends tRFC (MIN) later. Figure 43: Refresh Mode Notes: 1. NOP commands are shown for ease of illus tration; other valid commands may be possible at these times. CKE must be active during the PRECHARGE, ACTIVATE, and REFRESH com- mands, but may be inactive at other times (see "Power-Down Mode" on page 151). 2. The second REFRESH is not re quired but depicts two back-to-back REFRESH commands. 3. “Don’t Care” if A10 is HIGH at this point; however, A10 must be HIGH if more than one bank is active (must precharge all active banks). 4. For operations shown, DM, DQ, and DQS signals are all “Don’t Care”/High-Z. NOP1NOP1 NOP1PRE RA Bank(s)3 BA REF NOP 1 REF2 NOP1 ACTNOP1 One bank All banks tCK tCH tCL RA tRFC2tRP tRFC (MIN) T0 T1 T2 T3 T4 Ta0 Tb0Ta1 Tb1 Tb2 Don’t CareIndicates A Break in Time Scale Valid1 Valid1 Valid1 CK CK# Command CKE Address A10 BA[2:0] DQ4 DM4 DQS, DQS#4

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 96 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Commands SELF REFRESH The SELF REFRESH command is used to retain data in the DRAM, even if the rest of the system is powered down. When in the self refresh mode, the DRAM retains data without external clocking. The self refresh mode is also a convenient method used to enable/ disable the DLL (see “DLL Disable Mode” on page 96) as well as to change the clock frequency within the allowed synchronous operating range (see “Input Clock Frequency Change” on page 99). All power supply inputs (including V REFCA and VREFDQ) must be maintained at valid levels upon entry/exit and during SELF REFRESH operation. DLL Disable Mode If the DLL is disabled by the mode register (MR1[0] can be switched during initialization or later), the DRAM is targeted, but not guaranteed, to operate similarly to the normal mode with a few notable exceptions:  The DRAM supports only one value of CAS latency (CL = 6) and one value of CAS WRITE latency (CWL = 6).  DLL disable mode affects the read data clock-to-data strobe relationship (tDQSCK), but not the read data-to-data strobe relationship (tDQSQ, tQH). Special attention is needed to line the read data up with the controller time domain when the DLL is disabled.  In normal operation (DLL on), tDQSCK starts from the rising clock edge AL + CL cycles after the READ command. In DLL disable mode, tDQSCK starts AL + CL - 1 cycles after the READ command. Additionally, with the DLL disabled, the value of tDQSCK could be larger than tCK. The ODT feature is not supported during DLL disable mode (including dynamic ODT). The ODT resistors must be disabled by continuously registering the ODT ball LOW by programming RTT_NOM MR1[9, 6, 2] and RTT_WR MR2[10, 9] to “0” while in the DLL disable mode. Specific steps must be followed to switch between the DLL enable and DLL disable modes due to a gap in the allowed clock rates between the two modes (tCK [AVG] MAX and tCK [DLL disable] MIN, respectively). The only time the clock is allowed to cross this clock rate gap is during self refresh mode. Thus, the required procedure for switching from the DLL enable mode to the DLL disable mode is to change frequency during self refresh (see Figure 44 on page 97): 1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT is turned off, and R TT_NOM and RTT_WR are High-Z), set MR1[0] to “1” to disable the DLL. 2. Enter self refresh mode after tMOD has been satisfied. 3. After tCKSRE is satisfied, change the frequency to the desired clock rate. 4. Self refresh may be exited when the clock is stable with the new frequency for tCKSRX. After tXS is satisfied, update the mode registers with appropriate values. 5. The DRAM will be ready for its next command in the DLL disable mode after the greater of tMRD or tMOD has been satisfied. A ZQCL command should be issued with appropriate timings met as well.

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 97 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Commands Figure 44: DLL Enable Mode to DLL Disable Mode Notes: 1. Any valid command. 2. Disable DLL by setting MR1[0] to “1.” 3. Enter SELF REFRESH. 4. Exit SELF REFRESH. 5. Update the mode registers with the DLL disable parameters setting. 6. Starting with the idle state, R TT is in the High-Z state. 7. Change fre quency. 8. Clock must be stable tCKSRX. 9. Static LOW in case R TT_NOM or RTT_WR is enabled; otherwise, static LOW or HIGH. A similar procedure is required for switching from the DLL disable mode back to the DLL enable mode. This also requires changing the frequency during self refresh mode (see Figure 45 on page 98). 1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT is turned off, and R TT_NOM and RTT_WR are High-Z), enter self refresh mode. 2. After tCKSRE is satisfied, change the frequency to the new clock rate. 3. Self refresh may be exited when the clock is stable with the new frequency for tCKSRX. After tXS is satisfied, update the mode registers with the appropriate values. At a min- imum, set MR1[0] to “0” to enable the DLL. Wait tMRD, then set MR0[8] to “1” to enable DLL RESET . 4. After another tMRD delay is satisfied, then update the remaining mode registers with the appropriate values. 5. The DRAM will be ready for its next command in the DLL enable mode after the greater of tMRD or tMOD has been satisfied. However, before applying any command or function requiring a locked DLL, a delay of tDLLK after DLL RESET must be satis- fied. A ZQCL command should be issued with the appropriate timings met as well. Command T0 T1 Ta0 Ta1 T b0T c0 Td0T d1 Te0 Te1 Tf0 CK CK# ODT9 Valid1 Don’t Care Valid1 SRE3 NOPMRS2 NOP SRX4 MRS5 Valid1NOP NOP Indicates A Break in Time Scale tMOD tCKSRE tMODtXS tCKESR CKE tCKSRX8

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 98 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Commands Figure 45: DLL Disable Mode to DLL Enable Mode Notes: 1. Enter SELF REFRESH. 2. Exit SELF REFRESH. 3. Wait tXS, then set MR1[0] to “0” to enable DLL. 4. Wait tMRD, then set MR0[8] to “1” to begin DLL RESET. 5. Wait tMRD, update registers (CL, CWL, and write recovery may be necessary). 6. Wait tMOD, any valid command. 7. Starting with the idle state. 8. Change fre quency. 9. Clock must be stable at least tCKSRX. 10. Static LOW in case R TT_NOM or RTT_WR is enabled; otherwise, static LOW or HIGH. The clock frequency range for the DLL disable mode is specified by the parameter tCKDLL_DIS. Due to latency counter and timing restrictions, only CL = 6 and CWL = 6 are supported. DLL disable mode will affect the read data clock to data strobe relationship (tDQSCK) but not the data strobe to data relationship (tDQSQ, tQH). Special attention is needed to line up read data to the controller time domain. Compared to the DLL on mode where tDQSCK starts from the rising clock edge AL + CL cycles after the READ command, the DLL disable mode tDQSCK starts AL + CL - 1 cycles after the READ command (see Figure 46 on page 99). WRITE operations function similarly between the DLL enable and DLL disable modes; however, ODT functionality is not allowed with DLL disable mode. CKE T0 Ta0 Ta1 T b0T c0T c1T d0 Te0 Tf0 T g0 CK CK# ODT10 SRE1 NOPCommand NOP SRX2 MRS3 MRS4 MRS5 Valid6 Valid Don’t Care Indicates A Break in Time Scale tCKSRE tCKSRX9 tXS tMRD tMRD tCKESR ODTL off + 1 × tCK Th0 tDLLK

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 99 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Commands Figure 46: DLL Disable tDQSCK Timing Input Clock Frequency Change When the DDR3 SDRAM is initialized, it requires the clock to be stable during most normal states of operation. This means that after the clock frequency has been set to the stable state, the clock period is not allowed to deviate except what is allowed for by the clock jitter and spread spectrum clocking (SSC) specifications. The input clock frequency can be changed from one stable clock rate to another under two conditions: self refresh mode and precharge power-down mode. Outside of these two modes, it is illegal to change the clock frequency. For the self refresh mode condi- tion, when the DDR3 SDRAM has been successfully placed into self refresh mode and tCKSRE has been satisfied, the state of the clock becomes a “Don’t Care.” When the clock becomes a “Don’t Care,” changing the clock frequency is permissible, provided the new clock frequency is stable prior to tCKSRX. When entering and exiting self refresh mode for the sole purpose of changing the clock frequency, the self refresh entry and exit spec- ifications must still be met. The precharge power-down mode condition is when the DDR3 SDRAM is in precharge power-down mode (either fast exit mode or slow exit mode). Either ODT must be at a logic LOW or R TT_NOM and RTT_WR must be disabled via MR1 and MR2. This ensures RTT_NOM and RTT_WR are in an off state prior to entering precharge power-down mode, and CKE must be at a logic LOW . A minimum of tCKSRE must occur after CKE goes LOW before the clock frequency can change. The DDR3 SDRAM input clock frequency is allowed to change only within the minimum and maximum operating frequency specified for the particular speed grade ( tCK [AVG] MIN to tCK [AVG] MAX). During the input clock frequency change, CKE must be held at a stable LOW level. When the input clock frequency is changed, a stable clock must be provided to the DRAM tCKSRX before precharge power-down may be exited. After precharge power-down is exited and tXP has Table 66: READ Electrical Chara cteristics, DLL Disable Mode Parameter Symbol Min Max Units Access window of DQS from CK, CK# tDQSCK (DLL_DIS)1 1 0 n s T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Don’t CareTransitioning Data Valid NOPREAD NOP NOP NOP NOP NOP NOP NOP NOP NOP CK CK# Command Address DI b + 3DI b + 2DI b + 1DI b DI b + 7DI b + 6DI b + 5DI b + 4 DQ BL8 DLL on DQS, DQS# DLL on DQ BL8 DLL disable DQS, DQS# DLL off DQ BL8 DLL disable DQS, DQS# DLL off RL = AL + CL = 6 (CL = 6, AL = 0) CL = 6 DI b + 3DI b + 2DI b + 1DI b DI b + 7DI b + 6DI b + 5DI b + 4 DI b + 3DI b + 2DI b + 1DI b DI b + 7DI b + 6DI b + 5DI b + 4 tDQSCK (DLL_DIS) MIN tDQSCK (DLL_DIS) MAX RL (DLL disable) = AL + (CL - 1) = 5

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 100 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Commands been satisfied, the DLL must be reset via the MRS. Depending on the new clock frequency, additional MRS commands may need to be issued. During the DLL lock time, R TT_NOM and RTT_WR must remain in an off state. After the DLL lock time, the DRAM is ready to operate with a new clock frequency. This process is depicted in Figure 47. Figure 47: Change Frequency During Precharge Power-Down Notes: 1. Applicable fo r both slow-exit and fast-exit precharge power-down modes. 2. tAOFPD and tAOF must be satisfied and outputs High-Z prior to T1 (see "On-Die Termina- tion (ODT)" on page 160 for exact requirements). 3. If the R TT_NOM feature was enabled in the mode register prior to entering precharge power-down mode, the ODT signal must be continuously registered LOW ensuring RTT is in an off state. If the RTT_NOM feature was disabled in the mode register prior to entering pre- charge power-down mode, RTT will remain in the off state. The ODT signal can be regis- tered either LOW or HIGH in this case. CK CK# Command NOPNOPNOP Address CKE DQ DM DQS, DQS# NOP tCK Enter precharge power-down mode Exit precharge power-down mode T0 T1 Ta0 Tc0 Tb0T2 Don’t Care tCKE tXP MRS DLL RESET Valid Valid NOP tCH tIH tIS tCL Tc1 Td0 Te1 Td1 tCKSRE tCHb tCLb tCKb tCHb tCLb tCKb tCHb tCLb tCKb tCPDED ODT NOP Te0 Previous clock frequency New clock frequency Frequency change Indicates A Break in Time Scale tIH tIS tIH tIS tDLLK tAOFPD/tAOF tCKSRX High-Z High-Z

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 101 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Commands Write Leveling For better signal integrity, DDR3 SDRAM memory modules adopted fly-by topology for the commands, addresses, control signals, and clocks. Write leveling is a scheme for the memory controller to adjust or deskew the DQS strobe (DQS, DQS#) to CK relationship at the DRAM with a simple feedback feature provided by the DRAM. Write leveling is generally used as part of the initialization process, if required. For normal DRAM opera- tion, this feature must be disabled. This is the only DRAM operation where the DQS functions as an input (to capture the incoming clock) and the DQ function as outputs (to report the state of the clock). Note that nonstandard ODT schemes are required. The memory controller using the write leveling procedure must have adjustable delay settings on its DQS strobe to align the rising edge of DQS to the clock at the DRAM pins. This is accomplished when the DRAM asynchronously feeds back the CK status via the DQ bus and samples with the rising edge of DQS. The controller repeatedly delays the DQS strobe until a CK transition from “0” to “1” is detected. The DQS delay established through this procedure helps ensure tDQSS, tDSS, and tDSH specifications in systems that use fly-by topology by deskewing the trace length mismatch. A conceptual timing of this procedure is shown in Figure 48. Figure 48: Write Leveling Concept CK CK# Source Differential DQS Differential DQS Differential DQS DQ DQ CK CK# Destination Destination Push DQS to capture 0–1 transition T0 T1 T2 T3 T4 T5 T6 T7 T0 T1 T2 T3 T4 T5 T6 Tn CK CK# T0 T1 T2 T3 T4 T5 T6 Tn Don’t Care 1 1 0 0

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 102 ©2006 Micron Technology, Inc. All rights reserved. enable each byte lane to be leveled independently. Table 67. It should also be noted that when the outputs are enabled during write leveling 4 is generally used when DRAM are on the rank that is being leveled.

1. Since the DRAM DQS is not being driven (M R1[12] = 1), DQS ignores the input strobe, and

all RTT_NOM values are allowed. This simulates a normal standby state to DQS.

1. Since the DRAM DQS is being driven (MR1[12] = 0), DQS captures the input strobe, and only

some RTT_NOM values are allowed. This simulates a normal write state to DQS.

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 103 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Commands Write Leveling Procedure A memory controller initiates the DRAM write leveling mode by setting MR1[7] to a “1,” assuming the other programable features (MR0, MR1, MR2, and MR3) are first set and the DLL is fully reset and locked. The DQ balls enter the write leveling mode going from a High-Z state to an undefined driving state, so the DQ bus should not be driven. During write leveling mode, only the NOP or DES commands are allowed. The memory controller should attempt to level only one rank at a time; thus, the outputs of other ranks should be disabled by setting MR1[12] to a “1” in the other ranks. The memory controller may assert ODT after a tMOD delay as the DRAM will be ready to process the ODT transition. ODT should be turned on prior to DQS being driven LOW by at least ODTL on delay (WL - 2 tCK), provided it does not violate the aforementioned tMOD delay requirement. The memory controller may drive DQS LOW and DQS# HIGH after tWLDQSEN has been satisfied. The controller may begin to toggle DQS after tWLMRD (one DQS toggle is DQS transitioning from a LOW state to a HIGH state with DQS# transitioning from a HIGH state to a LOW state, then both transition back to their original states). At a minimum, ODTL on and tAON must be satisfied at least one clock prior to DQS toggling. After tWLMRD and a DQS LOW preamble (tWPRE) have been satisfied, the memory controller may provide either a single DQS toggle or multiple DQS toggles to sample CK for a given DQS-to-CK skew. Each DQS toggle must not violate tDQSL (MIN) and tDQSH (MIN) specifications. tDQSL (MAX) and tDQSH (MAX) specifications are not applicable during write leveling mode. The DQS must be able to distinguish the CK’ s rising edge within tWLS and tWLH. The prime DQ will output the CK’ s status asynchronously from the associated DQS rising edge CK capture within tWLO. The remaining DQ that always drive LOW when DQS is toggling must be LOW within tWLOE after the first tWLO is satisfied (the prime DQ going LOW). As previously noted, DQS is an input and not an output during this process. Figure 49 on page 104 depicts the basic timing parameters for the overall write leveling procedure. The memory controller will likely sample each applicable prime DQ state and determine whether to increment or decrement its DQS delay setting. After the memory controller performs enough DQS toggles to detect the CK’ s “0-to-1” transition, the memory controller should lock the DQS delay setting for that DRAM. After locking the DQS setting, leveling for the rank will have been achieved, and the write leveling mode for the rank should be disabled or reprogrammed (if write leveling of another rank follows).

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 104 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Commands Figure 49: Write Leveling Sequence Notes: 1. MRS: Load MR1 to enter write leveling mode. 2. NOP: NOP or DES. 3. DQS, DQS# needs to fulf ill minimum pulse width requirements tDQSH (MIN) and tDQSL (MIN) as defined for regular writes. The maximum pulse width is system-dependent. 4. Differential DQS is th e differential data strobe (DQS, DQS#). Timing reference points are the zero crossings. The solid line represents DQS; the dotted line represents DQS#. 5. DRAM drives leveling feedback on a prime DQ (DQ0 for x4 and x8). The remaining DQ are driven low and remain in this state throughout the leveling procedure. Write Leveling Mode Exit Procedure After the DRAM are leveled, they must exit from write leveling mode before the normal mode can be used. Figure 50 on page 105 depicts a general procedure in exiting write leveling mode. After the last rising DQS (capturing a “1” at T0), the memory controller should stop driving the DQS signals after tWLO (MAX) delay plus enough delay to enable the memory controller to capture the applicable prime DQ state (at ~Tb0). The DQ balls become undefined when DQS no longer remains LOW, and they remain undefined until tMOD after the MRS command (at Te1). The ODT input should be deasserted LOW such that ODTL off (MIN) expires after the DQS is no longer driving LOW. When ODT LOW satisfies tIS, ODT must be kept LOW (at ~Tb0) until the DRAM is ready for either another rank to be leveled or until the normal mode can be used. After DQS termination is switched off, write level mode should be disabled via the MRS command (at Tc2). After tMOD is satisfied (at Te1), any valid command may be registered by the DRAM. Some MRS commands may be issued after tMRD (at Td1). CK CK# Command T1 T2 Early remaining DQ Late remaining DQ tWLOE NOP2 NOP MRS1 NOP NOP NOP NOP NOP NOP NOP NOP NOP tWLS tWLS tWLH tWLH Don’t Care Undefined Driving Mode Indicates A Break in Time Scale Prime DQ5 Differential DQS4 ODT tMOD tDQSL3 tDQSL3 tDQSH3 tDQSH3 tWLO tWLMRD tWLDQSEN tWLO tWLO tWLO

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 105 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Commands Figure 50: Exit Write Leveling Notes: 1. The DQ result, “= 1,” between Ta0 and Tc0, is a result of the DQS, DQS# signals capturing CK HIGH just after the T0 state. NOP CK T0 T1 T2 Ta0 T b0T c0T c1T c2T d0T d1 Te0 Te1 CK# Command ODT RTT_DQ NOPNOP NOP NOP NOP NOP MR S NOP NOP Address MR1 Valid Valid Valid Valid Don’t CareTransitioning RTT DQS, RTT DQS#R TT_NOM Undefined Driving Mode tAOF (MAX) tMRD Indicates A Break in Time Scale DQS, DQS# CK = 1DQ tIS tAOF (MIN) tMOD tWLO + tWLOE ODTL off

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 106 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Operations Initialization The following sequence is required for power up and initialization, as shown in Figure 51 on page 107: 1. Apply power. RESET# is recommended to be below 0.2 × V DDQ during power ramp to ensure the outputs remain disabled (High-Z) and ODT off (RTT is also High-Z). All other inputs, including ODT , may be undefined. During power up, either of the following conditions may exist and must be met:  Condition A: –V DD and VDDQ are driven from a single-power converter output and are ramped with a maximum delta voltage between them of ΔV ≤ 300mV . Slope reversal of any power supply signal is allowed. The voltage levels on all balls other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one side, and must be greater than or equal to VSSQ and VSS on the other side. –B o t h VDD and VDDQ power supplies ramp to VDD (MIN) and VDDQ (MIN) within tVDDPR = 200ms. –V REFDQ tracks VDD × 0.5, VREFCA tracks VDD ×0 . 5 . –V TT is limited to 0.95V when the power ramp is complete and is not applied directly to the device; however, tVTD should be greater than or equal to zero to avoid device latchup.  Condition B: –V DD may be applied before or at the same time as VDDQ. –V DDQ may be applied before or at the same time as VTT, VREFDQ, and VREFCA. – No slope reversals are allowed in the power supply ramp for this condition. 2. Until stable power, maintain RESET# LOW to ensure the outputs remain disabled (High-Z). After the power is stable, RESET# must be LOW for at least 200µs to begin the initialization process. ODT will remain in the High-Z state while RESET# is LOW and until CKE is registered HIGH. 3. CKE must be LOW 10ns prior to RESET# transitioning HIGH. 4. After RESET# transitions HIGH, wait 500µs (minus one clock) with CKE LOW . 5. After this CKE LOW time, CKE may be br ought HIGH (synchronously) and only NOP or DES commands may be issued. The clock must be present and valid for at least 10ns (and a minimum of five clocks) and ODT must be driven LOW at least tIS prior to CKE being registered HIGH. When CKE is registered HIGH, it must be continuously registered HIGH until the full initialization process is complete. 6. After CKE is registered HIGH and after tXPR has been satisfied, MRS commands may be issued. Issue an MRS (LOAD MODE) command to MR2 with the applicable settings (provide LOW to BA2 and BA0 and HIGH to BA1). 7. Issue an MRS command to MR3 with the applicable settings. 8. Issue an MRS command to MR1 with the applicable settings, including enabling the DLL and configuring ODT . 9. Issue an MRS command to MR0 with the a pplicable settings, including a DLL RESET command. tDLLK (512) cycles of clock input are required to lock the DLL. 10. Issue a ZQCL command to calibrate R TT and RON values for the process voltage tem- perature (PVT). Prior to normal operation, tZQINIT must be satisfied. 11. When tDLLK and tZQINIT have been satisfied, the DDR3 SDRAM will be ready for nor- mal operation.

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 107 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 51: Initialization Sequence CKE RTT BA[2:0] All voltage supplies valid and stable T = 200µs (MIN) DM DQS Address A10 CK CK# tCL Command NOP T0 Ta0 Don’t Care tCL tIS tCK ODT DQ Tb0 tDLLK MR1 with DLL enable MR0 with DLL reset tMRD tMOD MRSMRS BA0 = H BA1 = L BA2 = L BA0 = L BA1 = L BA2 = L Code Code Code Code Valid Valid Valid Valid Normal operation MR2 MR3 tMRD tMRD MRSMRS BA0 = L BA1 = H BA2 = L BA0 = H BA1 = H BA2 = L Code Code Code Code Tc0T d0 VTT VREF VDDQ VDD RESET# T = 500µs (MIN) tCKSRX Stable and valid clock Valid Power-up ramp T (MAX) = 200ms DRAM ready for external commands tZQINIT ZQ calibration A10 = H ZQCL tIS See power-up conditions in the initialization sequence text, set up 1 tXPR Valid = 20nstIOz Indicates A Break in Time Scale T (MIN) = 10ns tVTD

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 110 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 54: Mode Register 0 (MR0) Definitions Notes: 1. MR0[16, 13, 7, 2] are reserved for future use and must be programmed to “0.” Burst Type Accesses within a given burst may be programmed to either a sequential or an inter- leaved order. The burst type is selected via MR0[3], as shown in Figure 54. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table 68 on page 111. DDR3 only supports 4-bit burst chop and 8-bit burst access modes. Full interleave address ordering is supported for READs, while WRITEs are restricted to nibble (BC4) or word (BL8) boundaries.

01 BLCAS# latency BTPD

A9 A7 A6 A5 A4 A3A8 A2 A1 A0 Mode register 0 (MR0) Address bus 97 6 5 4 382 1 0 A10A12 A11BA0BA1 10111213 READ Burst Type Sequential (nibble) Interleaved CAS Latency Reserved 11 (DDR3-1600) DLL Write Recovery Reserved Reserved WR00 M12 Precharge PD DLL off (slow exit) DLL on (fast exit) BA2 Burst Length Fixed BL8 4 or 8 (on-the-fly via A12) Fixed BC4 (chop) Reserved M10 M11 M14 M15 Mode Register Mode register 0 (MR0) Mode register 1 (MR1) Mode register 2 (MR2) Mode register 3 (MR3) A13 01 01 DLL Reset No Yes

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 111 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Notes: 1. Internal READ and WRITE operations start at the same point in time for BC4 as they do for BL8. 2. Z = Data and strobe output drivers are in tri-state. 3. V = A valid logic level (0 or 1), but the respec tive input buffer ignores level-on input pins. 4. X = “Don’t Care.” DLL RESET DLL RESET is defined by MR0[8] (see Figure 54 on page 110). Programming MR0[8] to “1” activates the DLL RESET function. MR0[8] is self-clearing, meaning it returns to a value of “0” after the DLL RESET function has been initiated. Anytime the DLL RESET function is initiated, CKE must be HIGH and the clock held stable for 512 (tDLLK) clock cycles before a READ command can be issued. This is to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in invalid output timing specifications, such as tDQSCK timings. Write Recovery WRITE recovery time is defined by MR0[11:9] (see Figure 54 on page 110). Write recovery values of 5, 6, 7, 8, 10, or 12 may be used by programming MR0[11:9]. The user is required to program the correct value of write recovery and is calculated by dividing tWR (ns) by tCK (ns) and rounding up a noninteger value to the next integer: WR (cycles) = roundup (tWR [ns]/tCK [ns]). Table 68: Burst Order Burst Length READ/ WRITE Starting Column Address (A[2, 1, 0]) Burst Type = Sequential (Decimal) Burst Type = Interleaved (Decimal) Notes 4 chop READ 0 0 0 0, 1, 2, 3, Z, Z, Z, Z 0, 1, 2, 3, Z, Z, Z, Z 1, 2 WRITE 0 V V 0, 1, 2, 3, X, X, X, X 0, 1, 2, 3, X, X, X, X 1, 3, 4

8 READ 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 1

WRITE V V V 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 1, 3

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 112 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Precharge Power-Down (Precharge PD) The precharge PD bit applies only when precharge power-down mode is being used. When MR0[12] is set to “0,” the DLL is off during precharge power-down providing a lower standby current mode; however, tXPDLL must be satisfied when exiting. When MR0[12] is set to “1,” the DLL continues to run during precharge power-down mode to enable a faster exit of precharge power-down mode; however, tXP must be satisfied when exiting (see "Power-Down Mode" on page 151). CAS Latency (CL) The CL is defined by MR0[6:4], as shown in Figure 54 on page 110. CAS latency is the delay, in clock cycles, between the internal READ command and the availability of the first bit of output data. The CL can be set to 5, 6, 7, 8, 9, or 10. DDR3 SDRAM do not support half-clock latencies. Examples of CL = 6 and CL = 8 are shown in Figure 55. If an internal READ command is registered at clock edge n, and the CAS latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 49 on page 63 through Table 51 on page 65 indicate the CLs supported at various operating frequencies. Figure 55: READ Latency Notes: 1. For illustration purposes, on ly CL = 6 and CL = 8 are shown. Other CL values are possible. 2. Shown with nominal tDQSCK and nominal tDSDQ. READ NOP NOP NOP NOP NOP NOPNOP CK CK# Command DQ DQS, DQS# DQS, DQS# T0 T1 T2 T3 T4 T5 T6 T7 T8 Don’t Care CK CK# Command DQ READ NOP NOP NOP NOP NOP NOPNOP T0 T1 T2 T3 T4 T5 T6 T7 T8 DI n + 3 DI n + 1 DI n + 2 DI n + 4 DI n DI n NOP NOP AL = 0, CL = 8 AL = 0, CL = 6 Transitioning Data

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 113 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Mode Register 1 (MR1) The mode register 1 (MR1) controls additional functions and features not available in the other mode registers: Q OFF (OUTPUT DISABLE), TDQS (for the x8 configuration only), DLL ENABLE/DLL DISABLE, R TT_NOM value (ODT), WRITE LEVELING, POSTED CAS ADDITIVE latency, and OUTPUT DRIVE STRENGTH. These functions are controlled via the bits shown in Figure 56. The MR1 register is programmed via the MRS command and retains the stored information until it is reprogrammed, until RESET# goes LOW, or until the device loses power. Reprogramming the MR1 register will not alter the contents of the memory array, provided it is performed correctly. The MR1 register must be loaded when all banks are idle and no bursts are in progress. The controller must satisfy the specified timing parameters tMRD and tMOD before initiating a subsequent operation. Figure 56: Mode Register 1 (MR1) Definition Notes: 1. MR1[16, 13, 10, 8] ar e reserved for future use and must be programmed to “0.” 2. During write leveling, if MR1[7] and MR1[12] are “1” then all R TT_NOM values are available for use. 3. During write leveling, if MR1[7] is a “1,” but MR1[12] is a “0,” then only RTT_NOM write val- ues are available for use. DLL Enable/DLL Disable The DLL may be enabled or disabled by programming MR1[0] during the LOAD MODE command, as shown in Figure 56. The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal opera- tion after having disabled the DLL for the purpose of debugging or evaluation. Enabling the DLL should always be followed by resetting the DLL using the appropriate LOAD MODE command. If the DLL is enabled prior to entering self refresh mode, the DLL is automatically disabled when entering SELF REFRESH operation and is automatically reenabled and reset upon exit of SELF REFRESH operation. If the DLL is disabled prior to entering self refresh mode, the DLL remains disabled even upon exit of SELF REFRESH operation until it is reenabled and reset. AL R TTQ Off A9 A7 A6 A5 A4 A3 A8 A2 A1 A0 Mode register 1 (MR1) Address bus 9 7 6 5 4 3 8 2 1 0 A10 A12 A11 BA0 BA1 10 11 12 13 DLL Enable Enable (normal) Disable Output Drive Strength RZQ/6 (40Ω [NOM]) RZQ/7 (34Ω [NOM]) Reserved Reserved WL 1 0 ODS DLL RTTTDQS M12 Q Off Enabled Disabled BA2 Write Levelization Disable (normal) Enable Additive Latency (AL) Disabled (AL = 0) AL = CL - 1 AL = CL - 2 Reserved RTT ODS A13 M11 TDQS Disabled Enabled 01 01 RTT_NOM (ODT)2 Non-Writes RTT_NOM disabled RZQ/4 (60Ω [NOM]) RZQ/2 (120Ω [NOM]) RZQ/6 (40Ω [NOM]) RZQ/12 (20Ω [NOM]) RZQ/8 (30Ω [NOM]) Reserved Reserved RTT_NOM (ODT)3 Writes RTT_NOM disabled RZQ/4 (60Ω [NOM]) RZQ/2 (120Ω [NOM]) RZQ/6 (40Ω [NOM]) n/a n/a Reserved Reserved Mode Register Mode register set 0 (MR0) Mode register set 1 (MR1) Mode register set 2 (MR2) Mode register set 3 (MR3) M14 M15

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 114 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations The DRAM is not tested to check—nor does Micron warrant compliance with—normal mode timings or functionality when the DLL is disabled. An attempt has been made to have the DRAM operate in the normal mode where reasonably possible when the DLL has been disabled; however, by industry standard, a few known exceptions are defined: 1. ODT is not allowed to be used. 2. The output data is no longer edge-aligned to the clock. 3. CL and CWL can only be six clocks. When the DLL is disabled, timing and functionality can vary from the normal operation specifications when the DLL is enabled (see “DLL Disable Mode” on page 96). Disabling the DLL also implies the need to change the clock frequency (see “Input Clock Frequency Change” on page 99). Output Drive Strength The DDR3 SDRAM uses a programmable impedance output buffer. The drive strength mode register setting is defined by MR1[5, 1]. RZQ/7 (34Ω [NOM]) is the primary output driver impedance setting for DDR3 SDRAM devices. To calibrate the output driver impedance, an external precision resistor (RZQ) is connected between the ZQ ball and V SSQ. The value of the resistor must be 240Ω ±1 percent. The output impedance is set during initialization. Additional impedance calibration updates do not affect device operation, and all data sheet timings and current specifica- tions are met during an update. To meet the 34Ω specification, the output drive strength must be set to 34Ω during initialization. To obtain a calibrated output driver impedance after power-up, the DDR3 SDRAM needs a calibration command that is part of the initialization and reset proce- dure. OUTPUT ENABLE/DISABLE The OUTPUT ENABLE function is defined by MR1[12], as shown in Figure 56 on page 113. When enabled (MR1[12] = 0), all outputs (DQ, DQS, DQS#) function when in the normal mode of operation. When disabled (MR1[12] = 1), all DDR3 SDRAM outputs (DQ and DQS, DQS#) are tri-stated. The output disable feature is intended to be used during I DD characterization of the READ current and during tDQSS margining (write leveling) only. TDQS Enable Termination data strobe (TDQS) is a feature of the x8 DDR3 SDRAM configuration, which provides termination resistance (RTT), that may be useful in some system config- urations. TDQS is not supported in x4 or x16 configurations. When enabled via the mode register (MR1[11]), the RTT that is applied to DQS and DQS# is also applied to TDQS and TDQS#. In contrast to the RDQS function of DDR2 SDRAM, TDQS provides the termina- tion resistance RTT only. The OUTPUT DATA STROBE function of RDQS is not provided by TDQS; thus, RON does not apply to TDQS and TDQS#. The TDQS and DM functions share the same ball. When the TDQS function is enabled via the mode register, the DM function is not supported. When the TDQS function is disabled, the DM function is provided, and the TDQS# ball is not used. The TDQS function is available in the x8 DDR3 SDRAM configuration only and must be disabled via the mode register for the x4 and x16 configurations.

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 115 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations On-Die Termination ODT resistance RTT_NOM is defined by MR1[9, 6, 2] (see Figure 56 on page 113). The RTT termination value applies to the DQ, DM, DQS, DQS#, and TDQS, TDQS# balls. DDR3 supports multiple RTT termination values based on RZQ/n where n can be 2, 4, 6, 8, or 12 and RZQ is 240Ω. Unlike DDR2, DDR3 ODT must be turned off prior to reading data out and must remain off during a READ burst. RTT_NOM termination is allowed any time after the DRAM is initialized, calibrated, and not performing read access, or when it is not in self refresh mode. Additionally, write accesses with dynamic ODT enabled (RTT_WR) temporarily replaces RTT_NOM with RTT_WR. The actual effective termination, RTT_EFF, may be different from the RTT targeted due to nonlinearity of the termination. For RTT_EFF values and calculations (see "On-Die Termination (ODT)" on page 160). The ODT feature is designed to improve signal integrity of the memory channel by enabling the DDR3 SDRAM controller to independently turn on/off ODT for any or all devices. The ODT input control pin is used to determine when R TT is turned on (ODTL on) and off (ODTL off), assuming ODT has been enabled via MR1[9, 6, 2]. Timings for ODT are detailed in "On-Die Termination (ODT)" on page 160. WRITE LEVELING The WRITE LEVELING function is enabled by MR1[7], as shown in Figure 56 on page 113. Write leveling is used (during initialization) to deskew the DQS strobe to clock offset as a result of fly-by topology designs. For better signal integrity, DDR3 SDRAM memory modules adopted fly-by topology for the commands, addresses, control signals, and clocks. The fly-by topology benefits from a reduced number of stubs and their lengths. However, fly-by topology induces flight time skews between the clock and DQS strobe (and DQ) at each DRAM on the DIMM. Controllers will have a difficult time maintaining tDQSS, tDSS, and tDSH specifications without supporting write leveling in systems which use fly-by topology-based modules. Write leveling timing and detailed operation informa- tion is provided in “Write Leveling” on page 101. POSTED CAS ADDITIVE Latency (AL) AL is supported to make the command and data bus efficient for sustainable band- widths in DDR3 SDRAM. MR1[4, 3] define the value of AL as shown in Figure 57 on page 116. MR1[4, 3] enable the user to program the DDR3 SDRAM with an AL = 0, CL - 1, or CL - 2. With this feature, the DDR3 SDRAM enables a READ or WRITE command to be issued after the ACTIVATE command for that bank prior to tRCD (MIN). The only restriction is ACTIVATE to READ or WRITE + AL ≥ tRCD (MIN) must be satisfied. Assuming tRCD (MIN) = CL, a typical application using this feature sets AL = CL - 1tCK = tRCD (MIN) - 1 tCK. The READ or WRITE command is held for the time of the AL before it is released internally to the DDR3 SDRAM device. READ latency (RL) is controlled by the sum of the AL and CAS latency (CL), RL = AL + CL. WRITE latency (WL) is the sum of CAS WRITE latency and AL, WL = AL + CWL (see "Mode Register 2 (MR2)" on page 116). Examples of READ and WRITE latencies are shown in Figure 57 on page 116 and Figure 59 on page 117.

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 116 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 57: READ Latency (AL = 5, CL = 6) Mode Register 2 (MR2) The mode register 2 (MR2) controls additional functions and features not available in the other mode registers. These additional functions are CAS WRITE latency (CWL), AUTO SELF REFRESH (ASR), SELF REFRESH TEMPERATURE (SRT), and DYNAMIC ODT (R TT_WR). These functions are controlled via the bits shown in Figure 58. The MR2 is programmed via the MRS command and will retain the stored information until it is programmed again or until the device loses power. Reprogramming the MR2 register will not alter the contents of the memory array, provided it is performed correctly. The MR2 register must be loaded when all banks are idle and no data bursts are in progress, and the controller must wait the specified time tMRD and tMOD before initiating a subse- quent operation. Figure 58: Mode Register 2 (MR2) Definition Notes: 1. MR2[16, 13:11, 8, and 2:0] are reserved for future use and must all be programmed to “0.” CK CK# Command DQ DQS, DQS# ACTIVE n T0 T1 Don’t Care NOP NOP T6 T12 NOPREAD n T13 NOP DO n + 3 DO n + 2 DO n + 1 RL = AL + CL = 11 T14 NOP DO n tRCD (MIN) AL = 5 CL = 6 T11 BC4 Indicates A Break in Time Scale Transitioning Data NOP M14 M15 Mode Register Mode register set 0 (MR0) Mode register set 1 (MR1) Mode register set 2 (MR2) Mode register set 3 (MR3) A9 A7 A 6 A5 A4 A3A8 A2 A1 A0 Mode register 2 (MR2) Address bus 97 6 5438 2 1 0 A10A12 A11BA0BA1 101112131415

1 CWL010

01 01 01 01 0101 SRTRTT_WR Auto Self Refresh (Optional) Disabled: Manual Enabled: Automatic Self Refresh Temperature Normal (0°C to 85°C) Extended (0°C to 95°C) CAS Write Latency (CWL) 5 CK (tCK ≥ 2.5ns) 6 CK (2.5ns > tCK ≥ 1.875ns) 7 CK (1.875ns > tCK ≥ 1.5ns) 8 CK (1.5ns > tCK ≥ 1.25ns) Reserved Reserved Reserved Reserved M10 Dynamic ODT ( R TT_WR ) RTT_WR disabled RZQ/4 RZQ/2 Reserved

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 117 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations CAS Write Latency (CWL) CWL is defined by MR2[5:3] and is the delay, in clock cycles, from the releasing of the internal write to the latching of the first data in. CWL must be correctly set to the corre- sponding operating clock frequency (see Figure 58 on page 116). The overall WRITE latency (WL) is equal to CWL + AL (Figure 56 on page 113), as shown in Figure 59. Figure 59: CAS Write Latency AUTO SELF REFRESH (ASR) Mode register MR2[6] is used to disable/enable the ASR function. When ASR is disabled, the self refresh mode’ s refresh rate is assumed to be at the normal 85°C limit (sometimes referred to as 1X refresh rate). In the disabled mode, ASR requires the user to ensure the DRAM never exceeds a T C of 85°C while in self refresh unless the user enables the SRT feature listed below when the TC is between 85°C and 95°C. Enabling ASR assumes the DRAM self refresh rate is changed automatically from 1X to 2X when the case temperature exceeds 85°C. This enables the user to operate the DRAM beyond the standard 85°C limit up to the optional extended temperature range of 95°C while in self refresh mode. The standard self refresh current test specifies test conditions to normal case tempera- ture (85°C) only, meaning if ASR is enabled, the standard self refresh current specifica- tions do not apply (see “Extended Temperature Usage” on page 150). SELF REFRESH TEMPERATURE (SRT) Mode register MR2[7] is used to disable/enable the SRT function. When SRT is disabled, the self refresh mode’ s refresh rate is assumed to be at the normal 85°C limit (sometimes referred to as 1X refresh rate). In the disabled mode, SRT requires the user to ensure the DRAM never exceeds a T C of 85°C while in self refresh mode unless the user enables ASR. When SRT is enabled, the DRAM self refresh is changed internally from 1X to 2X, regard- less of the case temperature. This enables the user to operate the DRAM beyond the standard 85°C limit up to the optional extended temperature range of 95°C while in self refresh mode. The standard self refresh current test specifies test conditions to normal case temperature (85°C) only, meaning if SRT is enabled, the standard self refresh current specifications do not apply (see “Extended Temperature Usage” on page 150). CK CK# Command DQ DQS, DQS# ACTIVE n BC4 T0 T1 Don’t Care NOP NOP T6 T12 NOPWRITE n T13 NOP DI n + 3 DI n + 2 DI n + 1 T14 NOP DI n tRCD (MIN) NOP AL = 5 T11 Indicates A Break in Time Scale WL = AL + CWL = 11 Transitioning Data CWL = 6

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 118 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations SRT vs. ASR If the normal case temperature limit of 85°C is not exceeded, then neither SRT nor ASR is required, and both can be disabled throughout operation. However, if the extended temperature option of 95°C is needed, the user is required to provide a 2X refresh rate during (manual) refresh and to enable either the SRT or the ASR to ensure self refresh is performed at the 2X rate. SRT forces the DRAM to switch the internal self refresh rate from 1X to 2X. Self refresh is performed at the 2X refresh rate regardless of the case temperature. ASR automatically switches the DRAM’s internal self refresh rate from 1X to 2X. However, while in self refresh mode, ASR enables the refresh rate to automatically adjust between 1X to 2X over the supported temperature range. One other disadvantage with ASR is the DRAM cannot always switch from a 1X to a 2X refresh rate at an exact case temperature of 85°C. Although the DRAM will support data integrity when it switches from a 1X to a 2X refresh rate, it may switch at a lower temperature than 85°C. Since only one mode is neccesary, SRT and ASR cannot be enabled at the same time. DYNAMIC ODT The dynamic ODT (R TT_WR) feature is defined by MR2[10, 9]. Dynamic ODT is enabled when a value is selected. This new DDR3 SDRAM feature enables the ODT termination value to change without issuing an MRS command, essentially changing the ODT termi- nation “on-the-fly.” With dynamic ODT (RTT_WR) enabled, the DRAM switches from normal ODT (RTT_NOM) to dynamic ODT (RTT_WR) when beginning a WRITE burst and subsequently switches back to ODT (RTT_NOM) at the completion of the WRITE burst. If RTT_NOM is disabled, the RTT_NOM value will be High-Z. Special timing parameters must be adhered to when dynamic ODT (RTT_WR) is enabled: ODTLCNW, ODTLCNW4, ODTLCNW8, ODTH4, ODTH8, and tADC. Dynamic ODT is only applicable during WRITE cycles. If ODT (RTT_NOM) is disabled, dynamic ODT (RTT_WR) is still permitted. RTT_NOM and RTT_WR can be used indepen- dent of one other. Dynamic ODT is not available during write leveling mode, regardless of the state of ODT (R TT_NOM). For details on dynamic ODT operation, refer to “On-Die Termination (ODT)” on page 160.

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 119 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Mode Register 3 (MR3) The mode register 3 (MR3) controls additional functions and features not available in the other mode registers. Currently defined is the MULTIPURPOSE REGISTER (MPR). This function is controlled via the bits shown in Figure 60. The MR3 is programmed via the LOAD MODE command and retains the stored information until it is programmed again or until the device loses power. Reprogramming the MR3 register will not alter the contents of the memory array, provided it is performed correctly. The MR3 register must be loaded when all banks are idle and no data bursts are in progress, and the controller must wait the specified time tMRD and tMOD before initiating a subsequent operation. Figure 60: Mode Register 3 (MR3) Definition Notes: 1. MR3[16 and 13:4] are reserved for fu ture use and must all be programmed to “0.” 2. When MPR control is set for normal DRAM operation, MR3[1, 0] will be ignored. 3. Intended to be used for READ synchronization. MULTIPURPOSE REGISTER (MPR) The MULTIPURPOSE REGISTER function is used to output a predefined system timing calibration bit sequence. Bit 2 is the master bit that enables or disables access to the MPR register, and bits 1 and 0 determine which mode the MPR is placed in. The basic concept of the multipurpose register is shown in Figure 61 on page 120. If MR3[2] is a “0,” then the MPR access is disabled, and the DRAM operates in normal mode. However, if MR3[2] is a “1,” then the DRAM no longer outputs normal read data but outputs MPR data as defined by MR3[0, 1]. If MR3[0, 1] is equal to “00,” then a predefined read pattern for system calibration is selected. To enable the MPR, the MRS command is issued to MR3, and MR3[2] = 1 (see Table 69 on page 120). Prior to issuing the MRS command, all banks must be in the idle state (all banks are precharged, and tRP is met). When the MPR is enabled, any subsequent READ or RDAP commands are redirected to the multipurpose register. The resulting operation when either a READ or a RDAP command is issued, is defined by MR3[1:0] when the MPR is enabled (see Table 70 on page 121). When the MPR is enabled, only READ or RDAP commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3[2] = 0). Power-down mode, self refresh, and any other nonREAD/RDAP command is not allowed during MPR enable mode. The RESET function is supported during MPR enable mode. A9 A7 A 6 A5 A4 A3A8 A2 A1 A0 Mode register 3 (MR3) Address bus 97 6 5438 2 1 0 A10A12 A11BA0BA1 101112131415 A13 10 1 01 01 01 01 01 01 MPR 1 BA2 01 01 01 01 01 MPR Enable Normal DRAM operations2 Dataflow from MPR MPR_RF M14 M15 Mode Register Mode register set (MR0) Mode register set 1 (MR1) Mode register set 2 (MR2) Mode register set 3 (MR3) MPR READ Function Predefined pattern3 Reserved Reserved Reserved

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 120 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 61: Multipurpose Register (MPR) Block Diagram Notes: 1. A predefined data pattern can be read out of the MPR with an external READ command. 2. MR3[2] defines whether the da ta flow comes from the memory core or the MPR. When the data flow is defined, the MPR contents can be read out continuously with a regular READ or RDAP command. MPR Functional Description The MPR is a 1-bit-wide logical interface via all DQ balls during a READ command. DQ0 on a x4 and a x8 is the prime DQ and outputs the MPR data while the remaining DQ are driven LOW . Similarly, for the x16, DQ0 (lower byte) and DQ8 (upper byte) are the prime DQ and output the MPR data while the remaining DQ drive LOW. The MPR readout supports fixed READ burst and READ burst chop (MRS and OTF via A12/BC#) with regular READ latencies and AC timings applicable, provided the DLL is locked as required. MPR addressing for a valid MPR read is as follows:  A[1:0] must be set to “00” as the burst order is fixed per nibble A 2 s e l e c t s t h e b u r s t o r d e r : – BL8, A2 is set to “0,” and the burst order is fixed to 0, 1, 2, 3, 4, 5, 6, 7  For burst chop 4 cases, the burst order is switched on the nibble base and: – A2 = 0; burst order = 0, 1, 2, 3 – A2 = 1; burst order = 4, 5, 6, 7  Burst order bit 0 (the first bit) is assigned to LSB, and burst order bit 7 (the last bit) is assigned to MSB Table 69: MPR Functional Description of MR3 Bits MR3[2] MR3[1:0] FunctionMPR MPR READ Function 0 “Don’t Care” Normal operat ion, no MPR transaction All subsequent READs come from the DRAM memory array All subsequent WRITEs go to the DRAM memory array

1 A[1:0]

(see Table 70 on page 121) Enable MPR mode, subsequent READ/RDAP commands defined by bits 1 and 2 Memory core MR3[2] = 0 (MPR off) DQ, DM, DQS, DQS# Multipurpose register predefined data for READs MR3[2] = 1 (MPR on)

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 121 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations  A[9:3] are a “Don’t Care”  A10 is a “Don’t Care”  A11 is a “Don’t Care”  A12: Selects burst chop mode on-t he-fly, if enabled within MR0  A13 is a “Don’t Care”  BA[2:0] are a “Don’t Care” MPR Register Address Definitions and Bursting Order The MPR currently supports a single data format. This data format is a predefined read pattern for system calibration. The predefined pattern is always a repeating 0–1 bit pattern. Examples of the different types of predefined READ pattern bursts are shown in Figure 62 on page 122, Figure 63 on page 123, Figure 64 on page 124, and Figure 65 on page 125. Notes: 1. Burst order bit 0 is assigned to LSB, and bu rst order bit 7 is assigned to MSB of the selected MPR agent. Table 70: MPR Readouts and Burst Order Bit Mapping MR3[2] MR3[1:0] Function Burst Length Read A[2:0] Burst Order and Data Pattern 1 00 READ predefined pattern for system calibration BL8 000 Burst order: 0, 1, 2, 3, 4, 5, 6, 7 Predefined pattern: 0, 1, 0, 1, 0, 1, 0, 1 BC4 000 Burst order: 0, 1, 2, 3 Predefined pattern: 0, 1, 0, 1 BC4 100 Burst order: 4, 5, 6, 7 Predefined pattern: 0, 1, 0, 1 1 01 RFU n/a n/a n/a n/a n/a n/a n/a n/a n/a 1 10 RFU n/a n/a n/a n/a n/a n/a n/a n/a n/a 1 11 RFU n/a n/a n/a n/a n/a n/a n/a n/a n/a

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 122 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 62: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout Notes: 1. READ with BL8 ei ther by MRS or OTF . 2. Memory controller mu st drive 0 on A[2:0]. T0 Ta0 T b0T b1T c0T c1T c2T c3T c4T c5 Tc6 Tc7T c8T c9T c10 CK CK# MRSPREA READ1 NOPNOP NOP NOP NOP NOP NOP NOP MR S NOP NOP Vali dCommand tMPRR Don’t CareIndicates A Break in Time Scale DQS, DQS# Bank address 3 Vali d 3 0A[1:0] Valid02 1A2 02 0 00A[9:3] Vali d 00 01A10/AP Valid 0 0A11 Vali d 0 0A12/BC# Valid1 0 0A[15:13] Vali d 0 DQ tMODtRP tMOD RL

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 123 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 63: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout Notes: 1. READ with BL8 ei ther by MRS or OTF . 2. Memory controller mu st drive 0 on A[2:0]. T0 Ta T b Tc0T c1T c2T c3 Tc4T c5T c6 Tc7T c8T c9T c10 T d CK CK# tMPRR Don’t CareIndicates A Break in Time Scale RL

3 Vali d 3Bank address Vali d

A[1:0] Valid02020 A2 12021 0 0A[15:13] Valid Valid 0 A[9:3] Vali d Valid 0000 A11 Vali d Valid 00 A12/BC# Valid1 00 A10/AP Vali d Valid 001 RL PREA READ1 NOP NOP NOP NOP NOP NOP NOP NOP NOP MR S ValidCommand READ1MRS DQ Valid DQS, DQS# tRP tMOD tCCD tMOD

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 124 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 64: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble Notes: 1. READ with BC4 either by MRS or OTF. 2. Memory controller mu st drive 0 on A[1:0]. T0 Ta T b CK CK# DQ DQS, DQS# tMODtMPRR Don’t Care Tc0T c1T c2T c3T c4T c5T c6 Tc7T c8T c9T c10 T d NOP NOP NOP NOP NOP MR S NOP NOP Vali dCommand MRSPREA READ1 READ1 NOP NOP Indicates A Break in Time Scale Bank address 3 Vali d 3Valid 0A[1:0] Valid0202 1A2 1403 0 00A[9:3] Vali d Valid 00 01A10/AP Vali d Valid 0 0A11 Vali d Valid 0 0A12/BC# Valid1 Valid1 0 0A[15:13] Valid Valid 0 RL RL tRF tMOD tCCD

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 125 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 65: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble Notes: 1. READ with BC4 either by MRS or OTF. 2. Memory controller mu st drive 0 on A[1:0]. T0 Ta T b 01A10/AP Vali d Valid 0 CK CK# MRSPREA READ1 READ1 NOP NOP NOP NOP NOP NOP NOP MR S NOP NOP Vali dCommand 004131A2 tMODtMPRR 02020A[1:0] Valid 00A[15:13] Vali d Valid 00A11 Vali d Valid 0000A[9:3] Vali d Valid Don’t Care Tc0T c1T c2T c3T c4T c5T c6 Tc7T c8T c9T c10 T d Indicates A Break in Time Scale RL DQ DQS, DQS# 0A12/BC# Valid1 Valid1 0 RL tRF tMOD tCCD

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 126 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations MPR Read Predefined Pattern The predetermined read calibration pattern is a fixed pattern of 0, 1, 0, 1, 0, 1, 0, 1. The following is an example of using the read out predetermined read calibration pattern. The example is to perform multiple reads from the multipurpose register in order to do system level read timing calibration based on the predetermined and standardized pattern. The following protocol outlines the steps used to perform the read calibration:  Precharge all banks A f t e r tRP is satisfied, set MRS, MR3[2] = 1 and MR3[1:0] = 00. This redirects all subse- quent reads and loads the predefined pattern into the MPR. As soon as tMRD and tMOD are satisfied, the MPR is available  Data WRITE operations are not allowed until the MPR returns to the normal DRAM state  Issue a read with burst order information (all other address pins are “Don’t Care”): – A[1:0] = 00 (data burst order is fixed starting at nibble) – A2 = 0 (for BL8, burst order is fixed as 0, 1, 2, 3, 4, 5, 6, 7) – A12 = 1 (use BL8)  After RL = AL + CL, the DRAM bursts out the predefined read calibration pattern  The memory controller repeats the calibr ation reads until read data capture at memory controller is optimized  After the last MPR READ burst and after tMPRR has been satisfied, issue MRS, MR3[2] = 0, and MR3[1:0] = “Don’t Care” to the normal DRAM state. All subsequent read and write accesses will be regular reads and writes from/to the DRAM array W h e n tMRD and tMOD are satisfied from the last MRS, the regular DRAM commands (such as activate a memory bank for regular read or write access) are permitted MODE REGISTER SET (MRS) The mode registers are loaded via inputs BA[2:0], A[13:0]. BA[2:0] determine which mode register is programmed:  BA2 = 0, BA1 = 0, BA0 = 0 for MR0  BA2 = 0, BA1 = 0, BA0 = 1 for MR1  BA2 = 0, BA1 = 1, BA0 = 0 for MR2  BA2 = 0, BA1 = 1, BA0 = 1 for MR3 The MRS command can only be issued (or reissued) when all banks are idle and in the precharged state ( tRP is satisfied and no data bursts are in progress). The controller must wait the specified time tMRD before initiating a subsequent operation such as an ACTI- VATE command (see Figure 52 on page 108). There is also a restriction after issuing an MRS command with regard to when the updated functions become available. This parameter is specified by tMOD. Both tMRD and tMOD parameters are shown in Figure 52 on page 108 and Figure 53 on page 109. Violating either of these requirements will result in unspecified operation. ZQ CALIBRATION The ZQ CALIBRATION command is used to calibrate the DRAM output drivers (RON) and ODT values (RTT) over process, voltage, and temperature, provided a dedicated 240Ω (±1 percent) external resistor is connected from the DRAM’ s ZQ ball to VSSQ.

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 136 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 79: Data Output Timing – tDQSQ and Data Valid Window Notes: 1. NOP commands are shown for ease of illustrati on; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1, 0] = 0, 0 or MR0[0, 1] = 0, 1 and A12 = 1 during READ command at T0. 3. DO n = data-out from column n. 4. BL8, RL = 5 (AL = 0, CL = 5). 5. Output timings ar e referenced to VDDQ/2 and DLL on and locked. 6. tDQSQ defines the skew between DQS, DQS# to data and does not define DQS, DQS# to clock. 7. Early data transitions may not always happen at the same DQ . Data transitions of a DQ can vary (either early or late) within a burst. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Bank,Col n tRPST NOPREAD NOPNOP NOP NOP NOP NOP NOP NOP NOP CK CK# Command1 Address 2 tDQSQ (MAX) DQS, DQS# DQ3 (last data valid) DQ3 (first data no longer valid) All DQ collectively DOn DOn + 3DOn + 2DOn + 1 DOn + 7DOn + 6DOn + 5DOn + 4 DOn + 2DOn + 1 DOn + 7DOn + 6DOn + 5DOn + 4 DO n + 3 DO n + 2 DO n + 1 DO n DO n + 7 DO n + 6 DO n + 5 DO n DOn + 3 tRPRE Don’t CareTransitioning Data Data valid Data valid tQHtQH tHZ (DQ) MAX DO n + 4 RL = AL + CL tDQSQ (MAX) tLZ (DQ) MIN

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 139 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations WRITE WRITE bursts are initiated with a WRITE command. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst. If auto precharge is not selected, the row will remain open for subsequent accesses. After a WRITE command has been issued, the WRITE burst may not be interrupted. For the generic WRITE commands used in Figure 86 on page 141 through Figure 94 on page 146, auto precharge is disabled. During WRITE bursts, the first valid data-in element is registered on a rising edge of DQS following the WRITE latency (WL) clocks later and subsequent data elements will be registered on successive edges of DQS. WRITE latency (WL) is defined as the sum of POSTED CAS ADDITIVE latency (AL) and CAS WRITE latency (CWL): WL = AL + CWL. The values of AL and CWL are programmed in the MR0 and MR2 registers, respectively. Prior to the first valid DQS edge, a full cycle is needed (including a dummy crossover of DQS, DQS#) and specified as the WRITE preamble shown in Figure 86 on page 141. The half cycle on DQS following the last data-in element is known as the WRITE postamble. The time between the WRITE command and the first valid edge of DQS is WL clocks tDQSS. Figure 87 on page 142 through Figure 94 on page 146 show the nominal case where tDQSS = 0ns; however, Figure 86 on page 141 includes tDQSS (MIN) and tDQSS (MAX) cases. Data may be masked from completing a WRITE using data mask. The mask occurs on the DM ball aligned to the write data. If DM is LOW, the write completes normally. If DM is HIGH, that bit of data is masked. Upon completion of a burst, assuming no other commands have been initiated, the DQ will remain High-Z, and any additional input data will be ignored. Data for any WRITE burst may be concatenated with a subsequent WRITE command to provide a continuous flow of input data. The new WRITE command can be tCCD clocks following the previous WRITE command. The first data element from the new burst is applied after the last element of a completed burst. Figures 87 and 88 on page 142 show concatenated bursts. An example of nonconsecutive WRITEs is shown in Figure 89 on page 143. Data for any WRITE burst may be followed by a subsequent READ command after tWTR has been met (see Figures 90 and 91 on page 144 and Figure 92 on page 145). Data for any WRITE burst may be followed by a subsequent PRECHARGE command providing tWR has been met, as shown in Figure 93 on page 146 and Figure 94 on page 146. Both tWTR and tWR starting time may vary depending on the mode register settings (fixed BC4, BL8 vs. OTF).

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 141 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 86: Write Burst Notes: 1. NOP commands are shown for ease of illus tration; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1: 0] = 00 or MR0[1:0] = 01 and A12 = 1 during the WRITE command at T0. 3. DI n = data-in for column n. 4. BL8, WL = 5 (AL = 0, CWL = 5). 5. tDQSS must be met at each rising clock edge. 6. tWPST is usually depicted as ending at the crossing of DQS, DQS#; however, tWPST actually ends when DQS no longer drives LOW and DQS# no longer drives HIGH. DI n + 3DI n + 2DI n + 1DI n T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Don’t CareTransitioning Data DI n + 7DI n + 6DI n + 5DIn + 4 Bank,Col n NOPWRITE NOPNOP NOP NOP NOP NOP NOP NOP NOP CK CK# Command1 DQ3 DQS, DQS# Address2 tWPST tWPRE tWPST tDQSL DQ3 DQ3 tWPST DQS, DQS# DQS, DQS# tDQSL tWPRE tDQSS tDQSS tDSH tDSH tDSH tDSH tDSS tDSS tDSS tDSS tDSS tDSS tDSS tDSS tDSS tDSS tDSH tDSH tDSH tDSH tDQSLtDQSH tDQSLtDQSH tDQSLtDQSH tDQSH tDQSL tDQSL tDQSL tDQSLtDQSHtDQSH tDQSH tDQSH tDQSLtDQSH tDQSLtDQSH tDQSH tDQSLtDQSH tDQSLtDQSH tDQSLtDQSH tDQSH WL = AL + CWL tDQSS (MIN) tDQSS (NOM) tDQSS (MAX) tDQSL tWPRE DI n + 3DI n + 2DI n + 1DI n DI n + 7DI n + 6DI n + 5DIn + 4 DI n + 3DI n + 2DI n + 1DI n DI n + 7DI n + 6DI n + 5DIn + 4

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 144 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 91: WRITE to READ (BC4 Mode Register Setting) Notes: 1. NOP commands are shown for ease of illustrati on; other commands may be valid at these times. 2. tWTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last write data shown at T7. 3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0 and the READ command at Ta0. 4. DI n = data-in for column n. 5. BC4 (fixed), WL = 5 (AL = 0, CW L = 5), RL = 5 (AL = 0, CL = 5). WL = 5 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 Ta0 Don’t CareTransitioning Data NOPWRITE Valid READ Valid NOP NOP NOP NOP NOP NOP NOP NOP CK CK# Command1 DQ4 DQS, DQS# Address3 tWPST tWTR2 tWPRE Indicates A Break in Time Scale DIn + 3DIn + 2DIn + 1DIn

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 145 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 92: WRITE (BC4 OTF) to READ (BC4 OTF) Notes: 1. NOP commands are shown for ease of illustrati on; other commands may be valid at these times. 2. tWTR controls the WRITE-to-READ delay to the same device and starts after tBL. 3. The BC4 OTF setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and the READ command at Tn. 4. DI n = data-in for column n. 5. BC4, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5). WL = 5 RL = 5 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 tWPRE T10 T11 Don’t CareTransitioning Data Tn NOPWRITE READ ValidValid NOP NOP NOP NOP NOP NOP NOP NOPNOP CK CK# Command1 DQ4 DQS, DQS# Address3 tWPST tBL = 4 clocks NOP tWTR2 Indicates A Break in Time Scale DI n + 3DI n + 2DI n + 1DI n

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 148 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 96: Data Input Timing PRECHARGE Input A10 determines whether one bank or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA[2:0] select the bank. When all banks are to be precharged, inputs BA[2:0] are treated as “Don’t Care.” After a bank is precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued. SELF REFRESH The SELF REFRESH command is initiated like a REFRESH command except CKE is LOW . The DLL is automatically disabled upon entering SELF REFRESH and is automatically enabled and reset upon exiting SELF REFRESH. The DRAM must be idle with all banks in the precharge state ( tRP is satisfied and no bursts are in progress) before a self refresh entry command can be issued. ODT must also be turned off before self refresh entry by registering the ODT ball LOW prior to the self refresh entry command (see “On-Die Termination (ODT)” on page 160 for timing requirements). If R TT_NOM and RTT_WR are disabled in the mode registers, ODT can be a “Don’t Care.” After the self refresh entry command is registered, CKE must be held LOW to keep the DRAM in self refresh mode. After the DRAM has entered self refresh mode, all external control signals, except CKE and RESET#, become “Don’t Care.” The DRAM initiates a minimum of one REFRESH command internally within the tCKE period when it enters self refresh mode. The requirements for entering and exiting self refresh mode depend on the state of the clock during self refresh mode. First and foremost, the clock must be stable (meeting tCK specifications) when self refresh mode is entered. If the clock remains stable and the frequency is not altered while in self refresh mode, then the DRAM is allowed to exit self refresh mode after tCKESR is satisfied (CKE is allowed to transition HIGH tCKESR later than when CKE was registered LOW). Since the clock remains stable in self refresh mode (no frequency change), tCKSRE and tCKSRX are not required. However, if the clock is altered during self refresh mode (turned-off or frequency change), then tCKSRE and tCKSRX must be satisfied. When entering self refresh mode, tCKSRE must be satisfied prior to altering the clock's frequency. Prior to exiting self refresh mode, tCKSRX must be satisfied prior to registering CKE HIGH. When CKE is HIGH during self refresh exit, NOP or DES must be issued for tXS time. tXS is required for the completion of any internal refresh that is already in progress and must be satisfied before a valid command not requiring a locked DLL can be issued to the device. tXS is also the earliest time self refresh reentry may occur (see Figure 97 on tDH tDS DM DQ DI b DQS, DQS# Don’t CareTransitioning Data tDQSH tDQSLtWPRE tWPST

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 149 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations page 149). Before a command requiring a locked DLL can be applied, a ZQCL command must be issued, tZQOPER timing must be met, and tXSDLL must be satisfied. ODT must be off during tXSDLL. Figure 97: Self Refresh Entry/Exit Timing Notes: 1. The clock must be valid and stable meeting tCK specifications at least tCKSRE after entering self refresh mode, and at least tCKSRX prior to exiting self refresh mode, if the clock is stopped or altered between states Ta0 and Tb0. If the clock remains valid and unchanged from entry and during self refresh mode, then tCKSRE and tCKSRX do not apply; however, tCKESR must be satisfied prior to exiting at SRX. 2. ODT must be disabled and R TT off prior to entering self refresh at state T1. If both RTT_NOM and RTT_WR are disabled in the mode registers, ODT can be a “Don’t Care.” 3. Self refresh entry (SRE) is synchronous via a REFRESH command with CKE LOW. 4. A NOP or DES command is re quired at T2 after the SRE command is issued prior to the inputs becoming “Don’t Care.” 5. NOP or DES commands are re quired prior to exiting self refresh mode until state Te0. 6. tXS is required before any commands not requiring a locked DLL. 7. tXSDLL is required before any commands requiring a locked DLL. 8. The device must be in the all banks idle state prior to entering self refresh mode. For exam- ple, all banks must be precharged, tRP must be met, and no data bursts can be in progress. 9. Self refresh exit is asynchronous; however, tXS and tXSDLL timings start at the first rising clock edge where CKE HIGH satisfies tISXR at Tc1. tCKSRX timing is also measured so that tISXR is satisfied at Tc1. CK CK# Command NOP NOP4SRE (REF)3 Address CKE ODT2 RESET#2 Valid Valid6SRX (NOP) NOP5 tRP8 tXS6, 9 tXSDLL7, 9 ODTL tIStCPDEDtIS tIS Enter self refresh mode (synchronous) Exit self refresh mode (asynchronous) T0 T1 T2 T c0T c1T d0Tb0 Don’t Care Te0 Valid Valid7 Valid Valid Valid tIH Ta0 Tf0 Indicates A Break in Time Scale tCKSRX1tCKSRE1 tCKESR (MIN)1

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 150 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Extended Temperature Usage Micron’ s DDR3 SDRAM support the optional extended temperature range of 0°C to 95°C, TC. Thus, the SRT and ASR options must be used at a minimum. The extended temperature range DRAM must be refreshed externally at 2X (double refresh) anytime the case temperature is above 85°C (and does not exceed 95°C). The external refreshing requirement is accomplished by reducing the refresh period from 64ms to 32ms. However, self refresh mode requires either ASR or SRT to support the extended temperature. Thus either ASR or SRT must be enabled when T C is above 85°C or self refresh cannot be used until the case temperature is at or below 85°C. Table 71 summarizes the two extended temperature options and Table 72 summarizes how the two extended temperature options relate to one another. Table 71: Self Refresh Temperature and Auto Self Refresh Description Field MR2 Bits Description Self Refresh Temperature (SRT) SRT 7 If ASR is disabled (MR2[6] = 0), SRT must be programmed to indicate TOPER during self refresh: *MR2[7] = 0: Normal operating temperature range (0°C to 85°C) *MR2[7] = 1: Extended operating temperature range (0°C to 95°C) If ASR is enabled (MR2[7] = 1), SRT must be set to 0, even if the extended temperature range is supported *MR2[7] = 0: SRT is disabled Auto Self Refresh (ASR) ASR 6 When ASR is enabled, the DRAM automatically provides SELF REFRESH power management functions, (refresh rate for all supported operating temperature values) * MR2[6] = 1: ASR is enabled (M7 must = 0) When ASR is not enabled, the SRT bit must be programmed to indicate TOPER during SELF REFRESH operation * MR2[6] = 0: ASR is disabled, must use manual self refresh temperature (SRT) Table 72: Self Refresh Mode Summary MR2[6] (ASR) MR2[7] (SRT) SELF REFRESH Operation Permitted Operating Temperature Range for Self Refresh Mode 0 0 Self refresh mode is supp orted in the normal temperature range Normal (0°C to 85°C) 0 1 Self refresh mode is supported in normal and extended temperature ranges; When SRT is enabled, it increases self refresh power consumption Normal and extended (0°C to 95°C) 1 0 Self refresh mode is supported in normal and extended temperature ranges; Self refresh power consumption may be temperature-dependent Normal and extended (0°C to 95°C) 1 1 Illegal

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 151 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Power-Down Mode Power-down is synchronously entered when CKE is registered LOW coincident with a NOP or DES command. CKE is not allowed to go LOW while either an MRS, MPR, ZQCAL, READ, or WRITE operation is in progress. CKE is allowed to go LOW while any of the other legal operations (such as ROW ACTIVATION, PRECHARGE, auto precharge, or REFRESH) are in progress. However, the power-down I DD specifications are not appli- cable until such operations have been completed. Depending on the previous DRAM state and the command issued prior to CKE going LOW, certain timing constraints must be satisfied (as noted in Table 73). Timing diagrams detailing the different power-down mode entry and exits are shown in Figure 98 on page 152 through Figure 107 on page 157. Notes: 1. If slow-exit mode precharge power-down is enabled and entered, ODT becomes asynchro- nous tANPD prior to CKE going LOW and remains asynchronous until tANPD + tXPDLL after CKE goes HIGH. Entering power-down disables the input and output buffers, excluding CK, CK#, ODT , CKE, and RESET#. NOP or DES commands are required until tCPDED has been satisfied, at which time all specified input/output buffers will be disabled. The DLL should be in a locked state when power-down is entered for the fastest power-down exit timing. If the DLL is not locked during power-down entry, the DLL must be reset after exiting power- down mode for proper READ operation as well as synchronous ODT operation. During power-down entry, if any bank remains open after all in-progress commands are complete, the DRAM will be in active power-down mode. If all banks are closed after all in-progress commands are complete, the DRAM will be in precharge power-down mode. Precharge power-down mode must be programmed to exit with either a slow exit mode or a fast exit mode. When entering precharge power-down mode, the DLL is turned off in slow exit mode or kept on in fast exit mode. The DLL remains on when entering active power-down as well. ODT has special timing constraints when slow exit mode precharge power-down is enabled and entered. Refer to “ Asynchronous ODT Mode” on page 172 for detailed ODT usage requirements in slow exit mode precharge power-down. A summary of the two power-down modes is listed in Table 74 on page 152. Table 73: Command to Power-Down Entry Parameters DRAM Status Last Command Prior to CKE LOW1 Parameter (Min) Parameter Value Figure Idle or active ACTIVATE tACTPDEN 1 tCK Figure 105 on page 156 Idle or active PRECHARGE tPRPDEN 1 tCK Figure 106 on page 156 Active READ or READAP tRDPDEN RL + 4 tCK + 1tCK Figure 101 on page 154 Active WRITE: BL8OTF, BL8MRS, BC4OTF tWRPDEN WL + 4 tCK + tWR/tCK Figure 102 on page 154 Active WRITE: BC4MRS WL + 2 tCK + tWR/tCK Figure 102 on page 154 Active WRITEAP: BL8OTF, BL8MRS, BC4OTF tWRAPDEN WL + 4 tCK + WR + 1tCK Figure 103 on page 155 Active WRITEAP: BC4MRS WL + 2 tCK + WR + 1tCK Figure 103 on page 155 Idle REFRESH tREFPDEN 1 tCK Figure 104 on page 155 Power-down REFRESH tXPDLL Greater of 10 tCK or 24ns Figure 108 on page 157 Idle MODE REGISTER SET tMRSPDEN tMOD Figure 107 on page 157

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 152 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations While in either power-down state, CKE is held LOW, RESET# is held HIGH, and a stable clock signal must be maintained. ODT must be in a valid state but all other input signals are a “Don’t Care.” If RESET# goes LOW during power-down, the DRAM will switch out of power-down mode and go into the reset state. After CKE is registered LOW, CKE must remain LOW until tPD (MIN) has been satisfied. The maximum time allowed for power- down duration is tPD (MAX) (9 × tREFI). The power-down states are synchronously exited when CKE is registered HIGH (with a required NOP or DES command). CKE must be maintained HIGH until tCKE has been satisfied. A valid, executable command may be applied after power-down exit latency, tXP tXPDLL have been satisfied. A summary of the power-down modes is listed in Table 74. For certain CKE-intensive operations, for example, repeating a power-down exit to refresh to power-down entry sequence, the number of clock cycles between power-down exit and power-down entry may not be sufficient enough to keep the DLL properly updated. In addition to meeting tPD when the REFRESH command is used in between power-down exit and power-down entry, two other conditions must be met. First, tXP must be satisfied before issuing the REFRESH command. Second, tXPDLL must be satis- fied before the next power-down may be entered. An example is shown in Figure 108 on page 157. Figure 98: Active Power-Down Entry and Exit Table 74: Power-Down Modes DRAM State MR1[12] DLL State Power-Down Exit Relevant Parameters Active (any bank open) “Don’t Care” On Fast tXP to any other valid command Precharged (all banks precharged) 1O n F a s t tXP to any other valid command 0O f fS l o w tXPDLL to commands that require the DLL to be locked (READ, RDAP, or ODT on) tXP to any other valid command CK CK# Command NOP NOP NOP NOP Address CKE tCK tCH tCL Enter power-down mode Exit power-down mode Don’t Care ValidValid Valid tCPDED Valid tIS tIH tIH tIS T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 NOP tXP tCKE (MIN) Indicates A Break in Time Scale tPD

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 158 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations RESET The RESET signal (RESET#) is an asynchronous signal that triggers any time it drops LOW, and there are no restrictions about when it can go LOW. After RESET# goes LOW, it must remain LOW for 100ns. During this time, the outputs are disabled, ODT (R TT) turns off (High-Z), and the DRAM resets itself. CKE should be brought LOW prior to RESET# being driven HIGH. After RESET# goes HIGH, the DRAM must be reinitialized as though a normal power up were executed (see Figure 109 on page 159). All refresh counters on the DRAM are reset, and data stored in the DRAM is assumed unknown after RESET# has gone LOW.

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_4.fm - Rev. D 8/1/08 EN 159 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 109: RESET Sequence CKE RTT BA[2:0] All voltage supplies valid and stable High-Z DM DQS High-Z Address A10 CK CK# tCL Command NOP T0 Ta0 Don’t Care tCL tIS ODT DQ High-Z Tb0 tDLLK MR1 with DLL ENABLE MRS MRS BA0 = H BA1 = L BA2 = L BA0 = L BA1 = L BA2 = L Code Code Code Code Valid Valid Valid Valid Normal operation MR2 MR3 MRS MRS BA0 = L BA1 = H BA2 = L BA0 = H BA1 = H BA2 = L Code Code Code Code Tc0 T d0 RESET# Stable and valid clock Valid Valid DRAM ready for external commands tZQINIT A10 = H ZQCL tIS tIOZ Valid Valid Valid System RESET (warm boot) ZQ CAL MR0 with DLL RESET T=10ns (MIN) T = 100ns (MIN) Indicates A Break in Time Scale T = 500µs (MIN) tXPR tMRD tMRD tMRD tMOD T (MIN) = MAX (10ns, 5tCK) tCK

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_5.fm - Rev. D 8/1/08 EN 160 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) On-Die Termination (ODT) ODT is a feature that enables the DRAM to enable/disable and turn on/off termination resistance for each DQ, DQS, DQS#, and DM for the x4 and x8 configurations (and TDQS, TDQS# for the x8 configuration, when enabled). ODT is applied to each DQ, UDQS, UDQS#, LDQS, LDQS#, UDM, and LDM signal for the x16 configuration. The ODT feature is designed to improve signal integrity of the memory channel by enabling the DRAM controller to independently turn on/off the DRAM’ s internal termi- nation resistance for any grouping of DRAM devices. The ODT feature is not supported during DLL disable mode. A simple functional representation of the DRAM ODT feature is shown in Figure 110. The switch is enabled by the internal ODT control logic, which uses the external ODT ball and other control information. Figure 110: On-Die Termination Functional Representation of ODT The value of RTT (ODT termination value) is determined by the settings of several mode register bits (see Table 78 on page 163). The ODT ball is ignored while in self refresh mode (must be turned off prior to self refresh entry) or if mode registers MR1 and MR2 are programmed to disable ODT . ODT is comprised of nominal ODT and dynamic ODT modes and either of these can function in synchronous or asynchronous mode (when the DLL is off during precharge power-down or when the DLL is synchronizing). Nominal ODT is the base termination and is used in any allowable ODT state. Dynamic ODT is applied only during writes and provides OTF switching from no R TT or RTT_NOM to RTT_WR. The actual effective termination, RTT_EFF, may be different from the RTT targeted due to nonlinearity of the termination. For RTT_EFF values and calculations, see "ODT Charac- teristics" on page 49. Nominal ODT ODT (NOM) is the base termination resistance for each applicable ball, it is enabled or disabled via MR1[9, 6, 2] (see Figure 47 on page61), and it is turned on or off via the ODT ball (see Table 75 on page 161). ODT VDDQ/2 RTT Switch DQ, DQS, DQS#, DM, TDQS, TDQS# To other circuitry such as RCV, . . .

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_5.fm - Rev. D 8/1/08 EN 161 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Notes: 1. Assumes dynamic ODT is disabled (see "Dynamic ODT" on page 162 when enabled). 2. ODT is enabled and active during most writes for proper termination, but it is not illegal to have it off during writes. 3. ODT must be disabled during reads. The RTT_NOM value is restricted during writes. Dynamic ODT is applicable if enabled. Nominal ODT resistance RTT_NOM is defined by MR1[9, 6, 2], as shown in Figure 47 on page 61. The RTT_NOM termination value applies to the output pins previously mentioned. DDR3 SDRAM supports multiple RTT_NOM values based on RZQ/n where n can be 2, 4, 6, 8, or 12 and RZQ is 240Ω. RTT_NOM termination is allowed any time after the DRAM is initialized, calibrated, and not performing read access or when it is not in self refresh mode. Write accesses use R TT_NOM if dynamic ODT (RTT_WR) is disabled. If RTT_NOM is used during writes, only RZQ/2, RZQ/4, and RZQ/6 are allowed (see Table 78 on page 163). ODT timings are summarized in Table 76, as well as listed in Table 53 on page 67. Examples of nominal ODT timing are shown in conjunction with the synchronous mode of operation in “Synchronous ODT Mode” on page 167. Table 75: Truth Table – ODT (Nominal) Note 1 applies to the entire table MR1[9, 6, 2] ODT Pin DRAM Termination State DRAM State Notes 000 0 R TT_NOM disabled, ODT off Any valid 2 000 1 R TT_NOM disabled, ODT on Any valid ex cept self refresh, read 3 000–101 0 R TT_NOM enabled, ODT off Any valid 2 000–101 1 R TT_NOM enabled, ODT on Any valid except self refresh, read 3 110 and 111 X R TT_NOM reserved, ODT on or off Illegal Table 76: ODT Parameter Symbol Description Begins at Defined to Definition for All DDR3 Speed Bins Units ODTL on ODT synchronous turn on delay ODT registered HIGH R TT_ON ±tA O N C W L+A L-2 tCK ODTL off ODT synchronous turn off delay ODT registered HIGH R TT_OFF ±tA O F C W L+A L-2 tCK tAONPD ODT asynchronous turn on delay ODT registered HIGH R TT_ON 1–9 ns tAOFPD ODT asynchronous turn off delay ODT registered HIGH R TT_OFF 1–9 ns ODTH4 ODT minimum HIGH time after ODT assertion or write (BC4) ODT registered HIGH or write registration with ODT HIGH ODT registered LOW 4tCK tCK ODTH8 ODT minimum HIGH time after write (BL8) Write registration with ODT HIGH ODT registered LOW 6tCK tCK tAON ODT turn-on relative to ODTL on completion Completion of ODTL on RTT_ON See Table 53 on page 67 ps tAOF ODT turn-off relative to ODTL off completion Completion of ODTL off RTT_OFF 0.5tCK ± 0.2tCK tCK

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_5.fm - Rev. D 8/1/08 EN 162 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Dynamic ODT In certain application cases, and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the DDR3 SDRAM can be changed without issuing an MRS command, essentially changing the ODT termination on the fly. With dynamic ODT (R TT_WR) enabled, the DRAM switches from nominal ODT (RTT_NOM) to dynamic ODT (RTT_WR) when beginning a WRITE burst and subsequently switches back to nominal ODT (RTT_NOM) at the completion of the WRITE burst. This requirement is supported by the dynamic ODT feature, as described below: Functional Description The dynamic ODT mode is enabled if either MR2[9] or MR2[10] is set to “1.” Dynamic ODT is not supported during DLL disable mode so RTT_WR must be disabled. The dynamic ODT function is described, as follows: T w o RTT values are available—R TT_NOM and RTT_WR: –T h e v a l u e f o r RTT_NOM is preselected via MR1[9, 6, 2] –T h e v a l u e f o r RTT_WR is preselected via MR2[10, 9]  During DRAM operation without READ or WRITE commands, the termination is controlled as follows: – Nominal termination strength R TT_NOM is used – Termination on/off timing is controlled via the ODT ball and latencies ODTL on and ODTL off  When a WRITE command (WR, WRAP , WRS4, WRS8, WRAPS4, WRAPS8) is registered, and if dynamic ODT is enabled, the ODT termination is controlled as follows: –A l a t e n c y o f O D T LCNW after the WRITE command: termination strength RTT_NOM switches to RTT_WR –A l a t e n c y o f O D T LCWN8 (for BL8, fixed or OTF) or ODTLCWN4 (for BC4, fixed or OTF) after the WRITE command: termination strength RTT_WR switches back to RTT_NOM – On/off termination timing is controlled via the ODT ball and determined by ODTL on, ODTL off, ODTH4, and ODTH8 –D u r i n g t h e tADC transition window, the value of RTT is undefined ODT is constrained during writes and when dynamic ODT is enabled (see Table 77). ODT timings listed in Table 76 on page 161 also apply to dynamic ODT mode. Table 77: Dynamic ODT Specific Parameters Symbol Description Begins at Defined to Definition for All DDR3 Speed Bins Units ODTLCNW Change from RTT_NOM to RTT_WR Write registration R TT switched from RTT_NOM to RTT_WR WL - 2 tCK ODTLCWN4 Change from R TT_WR to RTT_NOM (BC4) Write registration R TT switched from RTT_WR to RTT_NOM 4tCK + ODTL off tCK ODTLCWN8 Change from R TT_WR to RTT_NOM (BL8) Write registration R TT switched from RTT_WR to RTT_NOM 6tCK + ODTL off tCK tADC R TT change skew ODTL CNW completed R TT transition complete 0.5 tCK ± 0.2tCK tCK

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_5.fm - Rev. D 8/1/08 EN 163 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Notes: 1. RZQ = 240 Ω. If RTT_NOM is used during WRITEs, only RZQ/2, RZQ/4, RZQ/6 are allowed. Table 78: Mode Registers for R TT_NOM MR1 (RTT_NOM) RTT_NOM (RZQ) RTT_NOM (Ohms) RTT_NOM Mode RestrictionM9 M6 M2

000 O f f O f f n/a

0 0 1 RZQ/4 60 Self refresh 0 1 0 RZQ/2 120 0 1 1 RZQ/6 40

100 R Z Q / 1 2 2 0

Self refresh, write 1 0 1 RZQ/8 30 1 1 0 Reserved Reserved n/a 1 1 1 Reserved Reserved n/a Table 79: Mode Registers for R TT_WR MR2 (RTT_WR) RTT_WR (RZQ) RTT_WR (Ohms)M10 M9 0 0 Dynamic ODT off: WRIT E does not affect RTT_NOM

01 R Z Q / 4 6 0

10 R Z Q / 2 1 2 0

Table 80: Timing Diagrams for Dynamic ODT Figure and Page Title Figure 111 on page 164 Dynamic ODT: ODT As serted Before and After the WRITE, BC4 Figure 112 on page 164 Dynamic ODT: Without WRITE Command Figure 113 on page 165 Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 Figure 114 on page 166 Dynamic ODT: ODT Pin Assert ed with WRITE Command for 6 Clock Cycles, BC4 Figure 115 on page 166 Dynamic ODT: ODT Pin Assert ed with WRITE Command for 4 Clock Cycles, BC4

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_5.fm - Rev. D 8/1/08 EN 165 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Figure 113: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 Notes: 1. Via MRS or OTF; AL = 0, CWL = 5. If R TT_NOM can be either enabled or disabled, ODT can be HIGH. RTT_WR is enabled. 2. In this example, ODTH8 = 6 is satisfied exactly. T0 T1 T2 T3 T4 T5 T 6 T7 T8 T9 ODTLCWN8 ODTLON ODTLCNW WL tAOF (MAX) T10 T11 CK CK# Address RTT ODT DQ DQS, DQS# DI b + 3DI b + 2DI b + 1DI b DI b + 7DI b + 6DI b + 5DI b + 4 Valid Don’t CareTransitioning Command WRS8NOP NOPNOP NOP NOP NOP NOP NOP NOP NOP NOP RTT_WR ODTH8 ODTLOFF tADC (MAX) tAON (MIN) tAOF (MIN)

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_5.fm - Rev. D 8/1/08 EN 167 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Synchronous ODT Mode Synchronous ODT mode is selected whenever the DLL is turned on and locked and when either RTT_NOM or RTT_WR is enabled. Based on the power-down definition, these modes are:  Any bank active with CKE HIGH R e f r e s h m o d e w i t h C K E H I G H  Idle mode with CKE HIGH  Active power-down mode (regardless of MR0[12])  Precharge power-down mode if DLL is enabled during precharge power-down by MR0[12] ODT Latency and Posted ODT In synchronous ODT mode, R TT turns on ODTL on clock cycles after ODT is sampled HIGH by a rising clock edge and turns off ODTL off clock cycles after ODT is registered LOW by a rising clock edge. The actual on/off times varies by tAON and tAOF around each clock edge (see Table 81 on page 168). The ODT latency is tied to the WRITE latency (WL) by ODTL on = WL - 2 and ODTL off = WL - 2. Since write latency is made up of CAS WRITE latency (CWL) and ADDITIVE latency (AL), the AL programmed into the mode register (MR1[4, 3]) also applies to the ODT signal. The DRAM’ s internal ODT signal is delayed a number of clock cycles defined by the AL relative to the external ODT signal. Thus ODTL on = CWL + AL - 2 and ODTL off = CWL + AL - 2. Timing Parameters Synchronous ODT mode uses the following timing parameters: ODTL on, ODTL off, ODTH4, ODTH8 , tAON, and tAOF (see Table 81 and Figure 116 on page 168). The minimum RTT turn-on time (tAON [MIN]) is the point at which the device leaves High-Z and ODT resistance begins to turn on. Maximum RTT turn-on time (tAON [MAX]) is the point at which ODT resistance is fully on. Both are measured relative to ODTL on. The minimum RTT turn-off time (tAOF [MIN]) is the point at which the device starts to turn off ODT resistance. Maximum RTT turn off time (tAOF [MAX]) is the point at which ODT has reached High-Z. Both are measured from ODTL off. When ODT is asserted, it must remain HIGH until ODTH4 is satisfied. If a WRITE command is registered by the DRAM with ODT HIGH, then ODT must remain HIGH until ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (see Figure 117 on page 169). ODTH4 and ODTH8 are measured from ODT registered HIGH to ODT regis- tered LOW or from the registration of a WRITE command until ODT is registered LOW.

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_5.fm - Rev. D 8/1/08 EN 168 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Figure 116: Synchronous ODT Notes: 1. AL = 3; CWL = 5; ODTL on = WL = 6.0; ODTL off = WL - 2 = 6. RTT_NOM is enabled. Table 81: Synchronous ODT Parameters Symbol Description Begins at Defined to Definition for All DDR3 Speed Bins Units ODTL on ODT synchronous turn-o n delay ODT registered HIGH R TT_ON ±tA O N C W L+A L-2 tCK ODTL off ODT synchronous turn-off delay ODT registered HIGH R TT_OFF ±tA O F C W L+A L-2 tCK ODTH4 ODT minimum HIGH time after ODT assertion or WRITE (BC4) ODT registered HIGH, or write registration with ODT HIGH ODT registered LOW 4 tCK tCK ODTH8 ODT minimum HIGH time after WRITE (BL8) Write registration with ODT HIGH ODT registered LOW 6 tCK tCK tAON ODT turn-on relative to ODTL on completion Completion of ODTL on R TT_ON See Table 53 on page 67 ps tAOF ODT turn-off relative to ODTL off completion Completion of ODTL off R TT_OFF 0.5tCK ± 0.2tCK tCK T0 T1 T2 T3 T4 T5 T 6 T7 T8 T9 CWL - 2AL = 3AL = 3 tAON (MAX) tAOF (MAX) T10 T11 T12 T13 T14 T15 CK CK# RTT ODT Don’t CareTransitioning RTT_NOM CKE tAOF (MIN) ODTL off = CWL + AL - 2 ODTL on = CWL + AL - 2 ODTH4 (MIN) tAON (MIN)

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_5.fm - Rev. D 8/1/08 EN 169 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Figure 117: Synchronous ODT (BC4) Notes: 1. WL = 7. R TT_NOM is enabled. RTT_WR is disabled. 2. ODT must be held HIGH for at least ODTH4 after assertion (T1). 3. ODT must be kept HIGH ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (T7). 4. ODTH is measured from ODT first registered HIGH to OD T first registered LOW or from the registration of the WRITE command with ODT HIGH to ODT registered LOW. 5. Although ODTH4 is satisfied from ODT registered HIGH at T6, ODT must not go LOW before T11 as ODTH4 must also be satisfied from the registration of the WRITE command at T7. T0 T1 T2 T3 T4 T5 T 6 T7 T8 T9 tAOF (MAX) tAOF (MIN) tAON (MAX) tAOF (MAX) T10 T11 T12 T13 T14 T15 T17 T16 CK CK# RTT CKE NOP WRS4NOP NOP NOP NOP NOPNOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOPCommand Don’t CareTransitioning tAON (MIN) RTT_NOM ODTLoff = WL - 2 ODTH4 (MIN) ODTH4 ODTL off = WL - 2 ODTL on = WL - 2 tAON (MIN) tAON (MAX) ODTH4 ODTL on = WL - 2 tAOF (MIN) ODT RTT_NOM

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_5.fm - Rev. D 8/1/08 EN 170 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) ODT Off During READs As the DDR3 SDRAM cannot terminate and drive at the same time, RTT must be disabled at least one-half clock cycle before the READ preamble by driving the ODT ball LOW (if either R TT_NOM or RTT_WR is enabled). RTT may not be enabled until the end of the post- amble as shown in the example in Figure 118 on page 171. Note: ODT may be disabled earlier and enabled later than shown in Figure 118 on page 171.

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_5.fm - Rev. D 8/1/08 EN 171 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Figure 118: ODT During READs Notes: 1. ODT must be disabled ex ternally during READs by driving ODT LOW. For example, CL = 6; AL = CL - 1 = 5; RL = AL + CL = 11; CWL = 5; ODTL on = CWL + AL - 2 = 8; ODTL off = CWL + AL - 2 = 8. RTT_NOM is enabled. RTT_WR is a “Don’t Care.” T0 T1 T2 T3 T4 T5 T 6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T17T16 CK CK# ValidAddress DI b + 3 DI b + 2 DI b + 1 DI b DI b + 7 DI b + 6 DI b + 5 DI b + 4 DQ DQS, DQS# Don’t CareTransitioning Command NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOPNOPREAD ODTL on = CWL + AL - 2 ODT tAON (MAX)RL = AL + CL ODTL off = CWL + AL - 2 tAOF (MIN) RTT RTT_NOMRTT_NOM tAOF (MAX)

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_5.fm - Rev. D 8/1/08 EN 172 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Asynchronous ODT Mode Asynchronous ODT mode is available when the DRAM runs in DLL on mode and when either RTT_NOM or RTT_WR is enabled; however, the DLL is temporarily turned off in precharged power-down standby (via MR0[12]). Additionally, ODT operates asynchro- nously when the DLL is synchronizing after being reset. See "Power-Down Mode" on page 151 for definition and guidance over power-down details. In asynchronous ODT timing mode, the internal ODT command is not delayed by AL relative to the external ODT command. In asynchronous ODT mode, ODT controls R TT by analog time. The timing parameters tAONPD and tAOFPD (see Table 82 on page 173) replace ODTL on/tAON and ODTL off/tAOF , respectively, when ODT operates asyn- chronously (see Figure 119 on page 173). The minimum RTT turn-on time (tAONPD [MIN]) is the point at which the device termi- nation circuit leaves High-Z and ODT resistance begins to turn on. Maximum RTT turn- on time (tAONPD [MAX]) is the point at which ODT resistance is fully on. tAONPD (MIN) and tAONPD (MAX) are measured from ODT being sampled HIGH. The minimum RTT turn-off time (tAOFPD [MIN]) is the point at which the device termi- nation circuit starts to turn off ODT resistance. Maximum RTT turn-off time (tAOFPD [MAX]) is the point at which ODT has reached High-Z. tAOFPD (MIN) and tAOFPD (MAX) are measured from ODT being sampled LOW.

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_5.fm - Rev. D 8/1/08 EN 173 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Figure 119: Asynchronous ODT Timing with Fast ODT Transition Notes: 1. AL is ignored. Table 82: Asynchronous ODT Timing Parameters for All Speed Bins Symbol Description Min Max Units tAONPD Asynchronous R TT turn-on delay (power-down with DLL off) 1 9 ns tAOFPD Asynchronous R TT turn-off delay (power-down with DLL off) 1 9 ns T0 T1 T2 T3 T4 T5 T 6 T7 T8 T9 tAONPD (MAX) tAOFPD (MAX) T10 T11 T12 T13 T14 T15 T17T16 CK CK# RTT ODT RTT_NOM Don’t CareTransitioning CKE tIH tIS tIH tIS tAOFPD (MIN)tAONPD (MIN)

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_5.fm - Rev. D 8/1/08 EN 174 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) There is a transition period around power-down entry (PDE) where the DRAM’ s ODT may exhibit either synchronous or asynchronous behavior. This transition period occurs if the DLL is selected to be off when in precharge power-down mode by the setting MR0[12] = 0. Power-down entry begins tANPD prior to CKE first being registered LOW, and it ends when CKE is first registered LOW. tANPD is equal to the greater of ODTL off + 1tCK or ODTL on + 1tCK. If a REFRESH command has been issued, and it is in progress when CKE goes LOW, power-down entry will end tRFC after the REFRESH command rather than when CKE is first registered LOW. Power-down entry will then become the greater of tANPD and tRFC - REFRESH command to CKE registered LOW. ODT assertion during power-down entry results in an RTT change as early as the lesser of tAONPD (MIN) and ODTL on × tCK + tAON (MIN) or as late as the greater of tAONPD (MAX) and ODTL on × tCK + tAON (MAX). ODT de-assertion during power-down entry may result in an RTT change as early as the lesser of tAOFPD (MIN) and ODTL off × tCK + tAOF (MIN) or as late as the greater of tAOFPD (MAX) and ODTL off × tCK + tAOF (MAX). Table 83 on page 175 summarizes these parameters. If the AL has a large value, the uncertainty of the state of RTT becomes quite large. This is because ODTL on and ODTL off are derived from the WL and WL is equal to CWL + AL. Figure 120 on page 175 shows three different cases:  ODT_A: Synchronous behavior before tANPD  ODT_B: ODT state changes during the transition period with tAONPD (MIN) less than ODTL on × tCK + tAON (MIN) and tAONPD (MAX) greater than ODTL on × tCK + tAON (MAX)  ODT_C: ODT state changes after the transi tion period with asynchronous behavior

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_5.fm - Rev. D 8/1/08 EN 175 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Figure 120: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry Notes: 1. AL = 0; CWL = 5; ODTL off = WL - 2 = 3. Table 83: ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period Description Min Max Power-down entry transition period (power-down entry) Greater of: tANPD or tRFC - refresh to CKE LOW Power-down exit transition period (power-down exit) tANPD + tXPDLL ODT to RTT turn-on delay (ODTL on = WL - 2) Lesser of: tAONPD (MIN) (1ns) or ODTL on × tCK + tAON (MIN) Greater of: tAONPD (MAX) (9ns) or ODTL on × tCK + tAON (MAX) ODT to RTT turn-off delay (ODTL off = WL - 2) Lesser of: tAOFPD (MIN) (1ns) or ODTL off × tCK + tAOF (MIN) Greater of: tAOFPD (MAX) (9ns) or ODTL off × tCK + tAOF (MAX) tANPD WL - 1 (greater of ODTL off + 1 or ODTL on + 1) T0 T1 T2 T3 T4 T5 T 6 T7 T8 T9 tAOFPD (MAX) ODTL off T10 T11 T12 T13 Ta0 Ta1 Ta3 Ta2 CK CK# DRAM RTT B asynchronous or synchronous RTT_NOM DRAM RTT C asynchronous RTT_NOM Don’t CareTransitioning CKE NOP NOP NOPNOP NOPCommand NOPREF NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP PDE transition period Indicates A Break In Time Scale ODTL off + tAOFPD (MIN) tAOFPD (MAX) tAOFPD (MIN) ODTL off + tAOFPD (MAX) tAOFPD (MIN) tANPD tAOF (MIN) tAOF (MAX) DRAM RTT A synchronous RTT_NOM ODT A synchronous ODT C asynchronous ODT B asynchronous or synchronous tRFC (MIN)

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_5.fm - Rev. D 8/1/08 EN 176 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) The DRAM’ s ODT may exhibit either asynchronous or synchronous behavior during power-down exit (PDX). This transition period occurs if the DLL is selected to be off when in precharge power-down mode by setting MR0[12] to “0.” Power-down exit begins tANPD prior to CKE first being registered HIGH, and it ends tXPDLL after CKE is first registered HIGH. tANPD is equal to the greater of ODTL off + 1tCK or ODTL on + 1tCK. The transition period is tANPD plus tXPDLL. ODT assertion during power-down exit results in an RTT change as early as the lesser of tAONPD (MIN) and ODTL on × tCK + tAON (MIN) or as late as the greater of tAONPD (MAX) and ODTL on × tCK + tAON (MAX). ODT de-assertion during power- down exit may result in an RTT change as early as the lesser of tAOFPD (MIN) and ODTL off × tCK + tAOF (MIN) or as late as the greater of tAOFPD (MAX) and ODTL off × tCK + tAOF (MAX). Table 83 on page 175 summarizes these parameters. If the AL has a large value, the uncertainty of the RTT state becomes quite large. This is because ODTL on and ODTL off are derived from the WL, and WL is equal to CWL + AL. Figure 121 on page 177 shows three different cases:  ODT C: asynchronous behavior before tANPD  ODT B: ODT state changes during the transition period, with tAOFPD (MIN) less than ODTL off × tCK + tAOF (MIN) and ODTL off × tCK + tAOF (MAX) greater than tAOFPD (MAX)  ODT A: ODT state changes after the transition period with synchronous response

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_5.fm - Rev. D 8/1/08 EN 177 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Figure 121: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit Notes: 1. CL = 6; AL = CL - 1; CWL = 5; ODTL off = WL - 2 = 8. T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta 6 T b0 T b1 T b2 T c0 T c1 Td0 Td1 Tc2 CK CK# Don’t Care Transitioning ODT C synchronous NOP NOP NOP COMMAND NOP NOP NOP NOP NOP NOP NOP NOP NOP RTT B asynchronous or synchronous DRAM RTT A asynchronous DRAM RTT C synchronous RTT_NOM NOP NOP ODT B asynchronous or synchronous CKE tAOF (MIN) RTT_NOM Indicates A Break in Time Scale ODTL off + tAOF (MIN) tAOFPD (MAX) ODTL off + tAOF (MAX) tXPDLL tAOF (MAX) ODTL off ODT A asynchronous PDX transition period tAOFPD (MIN) tAOFPD (MAX) tANPD tAOFPD (MIN) RTT_NOM

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_5.fm - Rev. D 8/1/08 EN 178 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) If the time in the precharge power down or idle states is very short (short CKE LOW pulse), the power-down entry and power-down exit transition periods will overlap. When overlap occurs, the response of the DRAM’ s R TT to a change in the ODT state may be synchronous or asynchronous from the start of the power-down entry transition period to the end of the power-down exit transition period even if the entry period ends later than the exit period (see Figure 122 on page 179). If the time in the idle state is very short (short CKE HIGH pulse), the power-down exit and power-down entry transition periods overlap. When this overlap occurs, the response of the DRAM’ s R TT to a change in the ODT state may be synchronous or asyn- chronous from the start of power-down exit transition period to the end of the power- down entry transition period (see Figure 122 on page 179).

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_5.fm - Rev. D 8/1/08 EN 179 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Figure 122: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping Notes: 1. AL = 0, WL = 5, tANPD = 4. T0 T1 T2 T3 T4 T5 T 6 T7 T8 T9 Ta0 Ta1 Ta2 Ta3 Ta4 CK CK# CKE Command Don’t Care Transitioning tXPDLL tRFC (MIN) NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP REF NOP NOP NOP NOP PDE transition period PDX transition period Indicates A Break in Time Scale tANPD Short CKE LOW transition period (RTT change asynchronous or synchronous) tANPD

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb_DDR3_5.fm - Rev. D 8/1/08 EN 180 ©2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Figure 123: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping Notes: 1. AL = 0, WL = 5, tANPD = 4. T0 T1 T2 T3 T4 T5 T 6 T7 T8 T9 CK CK# Command Don’t Care Transitioning NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP tANPD tXPDLL Indicates A Break in Time Scale Ta0 Ta1 Ta2 Ta3 Ta4 CKE Short CKE HIGH transition period (RTT change asynchronous or synchonous) tANPD

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respec- tive owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice. DDR3_5.fm - Rev D 8/1/08 EN 181 ©2006 Micron Technology, Inc. All rights reserved.