MT3170B MITEL | Alldatasheet
Document overview
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Technical content
Features
- Wide dynamic range (50dB) DTMF Receiver
- Call progress (CP) detection via cadence indication
- 4-bit synchronous serial data output
- Software controlled guard time for MT3x70B
- Internal guard time circuitry for MT3x71B
- Powerdown option (MT317xB & MT337xB)
- 4.194304MHz crystal or ceramic resonator (MT337xB and MT327xB)
- External clock input (MT317xB)
- Guarantees non-detection of spurious tones
Applications
- Integrated telephone answering machine
- End-to-end signalling
- Fax Machines
Description
The MT3x7xB is a family of high performance DTMF receivers which decode all 16 tone pairs into a 4-bit binary code. These devices incorporate an AGC for wide dynamic range and are suitable for end-to-end signalling. The MT3x70B provides an early steering (ESt) logic output to indicate the detection of a DTMF signal and requires external software guard time to validate the DTMF digit. The MT3x71B, with preset internal guard times, uses a delay steering (DStD) logic output to indicate the detection of a valid DTMF digit. The 4-bit DTMF binary digit can be clocked out synchronously at the serial data (SD) output. The SD pin is multiplexed with call progress detector output. In the presence of supervisory tones, the call progress detector circuit indicates the cadence (i.e., envelope) of the tone burst. The cadence information can then be processed by an external microcontroller to identify specific call progress signals. The MT327xB and MT337xB can be used with a crystal or a ceramic resonator without additional components. A power-down option is provided for the MT317xB and MT337xB.
Ordering Information
MT3170/71BE 8 Pin Plastic DIP MT3270/71BE 8 Pin Plastic DIP MT3370/71BS 18 Pin SOIC MT3370/71BN 20 Pin SSOP -40 °C to +85 °C Figure 1 - Functional Block Diagram PWDN VDD VSS INPUT OSC2 OSC1 (CLK) ➀ MT3170B/71B and MT337xB only. ➁ MT3270B/71B and MT337xB only. Voltage Bias Circuit AGC Anti- alias Filter High Group Filter Low Group Filter Steering Circuit Digital Detector Algorithm Code Converter and Latch Digital Guard Time➂ Parallel to Serial Converter & Latch Mux Energy Detection Oscillator and Clock Circuit To All Chip Clocks Dial Tone Filter ESt DStD ACK SD or ➂ MT3x71B only. ISSUE 2 May 1995 MT3170B/71B, MT3270B/71B, MT3370B/71B Wide Dynamic Range DTMF Receiver
MT3170B/71B, MT3270B/71B, MT3370B/71B 4-4 Figure 2 - Pin Connections Pin Description Pin # Name Description 337xB 327xB 317xB 2 1 1 INPUT DTMF/CP Input. Input signal must be AC coupled via capacitor. 42 - O S C 2 Oscillator Output. 63 3 O S C 1 (CLK) Oscillator/Clock Input. This pin can either be driven by: 1) an external digital clock with defined input logic levels. OSC2 should be left open. 2) connecting a crystal or ceramic resonator between OSC1 and OSC2 pins. 94 4 V SS Ground. (0V) 11 5 5 SD Serial Data/Call Progress Output. This pin serves the dual function of being the serial data output when clock pulses are applied after validation of DTMF signal, and also indicates the cadence of call progress input. As DTMF signal lies in the same frequency band as call progress signal, this pin may toggle for DTMF input. The SD pin is at logic low in powerdown state. 13 6 6 ACK Acknowledge Pulse Input. After ESt or DStD is high, applying a sequence of four pulses on this pin will then shift out four bits on the SD pin, representing the decoded DTMF digit. The rising edge of the first clock is used to latch the 4-bit data prior to shifting. This pin is pulled down internally. The idle state of the ACK signal should be low. 15 7 7 ESt (MT3x70B) DStD (MT3x71B) Early Steering Output. A logic high on ESt indicates that a DTMF signal is present. ESt is at logic low in powerdown state. Delayed Steering Output. A logic high on DStD indicates that a valid DTMF digit has been detected. DStD is at logic low in powerdown state. 18 8 8 V DD Positive Power Supply (5V Typ.) Performance of the device can be optimized by minimizing noise on the supply rails. Decoupling capacitors across V DD and VSS are therefore recommended. 1,5,7,8, 10, 12, 14,16, -- N C No Connection. Pin is unconnected internally. 3- 2 P W D N Power Down Input. A logic high on this pin will power down the device to reduce power consumption. This pin is pulled down internally and can be left open if not used. ACK pin should be at logic ’0’ to power down device. VDD NC NC ESt/DStD NC ACK NC SD NC NC INPUT PWDN OSC2 NC OSC1 NC NC VSS INPUT PWDN CLK VSS VDD ACK SD INPUT OSC2 OSC1 VSS VDD ESt/ ACK SD MT3170B/71B MT3270B/71B MT3370B/71B
8 PIN PLASTIC DIP
18 PIN PLASTIC SOIC
20 PIN SSOP
MT3170B/71B, MT3270B/71B, MT3370B/71B 4-5 Summary of MT3x70/71B Product Family Device Type 8 Pin 18 Pin 20 Pin PWDN 2 Pin OSC Ext CLK ESt DStD MT3170B ✔✔ ✔ ✔ MT3171B ✔✔ ✔ ✔ MT3270B ✔✔ ✔ ✔ MT3271B ✔✔ ✔ ✔ Functional Description The MT3x7xBs are high performance and low power consumption DTMF receivers. These devices provide wide dynamic range DTMF detection and a serial decoded data output. These devices also incorporate an energy detection circuit. An input voiceband signal is applied to the devices via a series decoupling capacitor. Following the unity gain buffering, the signal enters the AGC circuit followed by an anti-aliasing filter. The bandlimited output is routed to a dial tone filter stage and to the input of the energy detection circuit. A bandsplit filter is then used to separate the input DTMF signal into high and low group tones. The high group and low group tones are then verified and decoded by the internal frequency counting and DTMF detection circuitry. Following the detection stage, the valid DTMF digit is translated to a 4-bit binary code (via an internal look- up ROM). Data bits can then be shifted out serially by applying external clock pulses. Automatic Gain Control (AGC) Circuit As the device operates on a single power supply, the input signal is biased internally at approximately VDD/2. With large input signal amplitude (between 0 and approximately -30dBm for each tone of the composite signal), the AGC is activated to prevent the input signal from being clipped. At low input level, the AGC remains inactive and the input signal is passed directly to the hardware DTMF detection algorithm and to the energy detection circuit. Filter and Decoder Section The signal entering the DTMF detection circuitry is filtered by a notch filter at 350 and 440 Hz for dial tone rejection. The composite dual-tone signal is further split into its individual high and low frequency components by two 6 th order switched capacitor bandpass filters. The high group and low group tones are then smoothed by separate output filters and squared by high gain limiting comparators. The resulting squarewave signals are applied to a digital detection circuit where an averaging algorithm is employed to determine the valid DTMF signal. For MT3x70B, upon recognition of a valid frequency from each tone group, the early steering (ESt) output will go high, indicating that a DTMF tone has been detected. Any subsequent loss of DTMF signal condition will cause the ESt pin to go low. For MT3x71B, an internal delayed steering counter validates the early steering signal after a predetermined guard time which requires no external components. The delayed steering (DStD) will go high only when the validation period has elapsed. Once the DStD output is high, the subsequent loss of early steering signal due to DTMF signal dropout will activate the internal counter for a validation of tone absent guard time. The DStD output will go low only after this validation period. Energy Detection The output signal from the AGC circuit is also applied to the energy detection circuit. The detection circuit consists of a threshold comparator and an active integrator. When the signal level is above the threshold of the internal comparator (-35dBm), the energy detector produces an energy present indication on the SD output. The integrator ensures the SD output will remain at high even though the input signal is changing. When the input signal is removed, the SD output will go low following the integrator decay time. Short decay time enables the signal envelope (or cadence) to be generated at the SD output. An external microcontroller can monitor this output for specific call progress signals. Since presence of speech and DTMF signals (above the threshold limit) can cause the SD output to toggle, both ESt (DStD) and SD outputs should be monitored to ensure correct signal identification. As the energy detector is multiplexed with the digital serial data output at the SD pin, the detector output is selected at all times except during the time between the rising edge of the first pulse and the falling edge of the fourth pulse applied at the ACK pin.
significant bit of the decoded digit on the SD pin. Table 1. Serial Decode Bit Table Note: b0=LSB of decoded DTMF digit and shifted out first. Table 2. Powerdown Mode + =enters powerdown mode on the rising edge. Table 3. Call Progress Tones
MT3170B/71B, MT3270B/71B, MT3370B/71B 4-7 Table 4. Recommended Resonator and Crystal Note: Qm=quality factor of RLC model, i.e., 1/2Πƒ R1C1. resonator across OSC1 and OSC2 pins. C0 = Capacitance between electrode. on pin OSC 1. The OSC2 pin should be left open. directly by an 4.194304 MHz external digital clock. The circuit shown in Figure 3 illustrates the use of a MT327xB in a typical receiver application. It requires only a coupling capacitor (C1) and a crystal or ceramic resonator (X1) to complete the circuit. The MT3x70B is designed for user who wishes to tailor the guard time for specific applications. When a DTMF signal is present, the ESt pin will go high. An external microcontroller monitors ESt in real time for a period of time set by the user. A guard time algorithm must be implemented such that DTMF signals not meeting the timing requirements are rejected. The MT3x71B uses an internal counter to provide a preset DTMF validation period. It requires no external components. The DStD output high indicates that a valid DTMF digit has been detected. The 4.194304 MHz frequency has a secondary advantage in some applications where a real time clock is required. A 22-bit counter will count 4,194,304 cycles to provide a one second time base. Figure 3 - Application Circuit for MT327xB DTMF/CP Input INPUT OSC2 OSC1 VSS VDD ESt/DStD ACK SD VDD COMPONENTS LIST: C 1 = 0.1 µF ± 10 % X1 = Crystal or Resonator (4.194304 MHz) To microprocessor or microcontroller MT327xB
MT3170B/71B, MT3270B/71B, MT3370B/71B 4-8 † Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing Absolute Maximum Ratings† - Voltages are with respect to VSS =0V unless otherwise stated. Parameter Symbol Min Max Units
1 DC Power Supply Voltage V DD -VSS 6V
2 Voltage on any pin (other than supply) V I/O -0.3 6.3 V
3 Current at any pin (other than supply) I I/O 10 mA
4 Storage temperature T S -65 150 °C
5 Package power dissipation P D 500 mW
Recommended Operating Conditions - Voltages are with respect to VSS =0V unless otherwise stated Parameter Sym Min Typ ‡ Max Units Test Conditions 1 Positive Power Supply V DD 4.75 5.0 5.25 V 2 Oscillator Clock Frequency f OSC 4.194304 MHz 3 Oscillator Frequency Tolerance ΔfOSC ±0.1 %
4 Operating Temperature T d -40 25 85 °C
otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions
1 Operating supply current I DD 38 m A
2 Standby supply current I DDQ 30 100 µA PWDN=5V, ACK=0V
ESt/DStD = SD = 0V 3a Input logic 1 V IH 4.0 V 3b Input logic 1 (for OSC1 input only) VIH 3.5 V MT327xB/MT337xB 4a Input logic 0 V IL 1.0 V 4b Input logic 0 (for OSC1 input only) VIL 1.5 V MT327xB/MT337xB
5 Input impedance (pin 1) R IN 50 k Ω
6 Pull-down Current
(PWDN, ACK pins) IPD 25 µA with internal pull-down resistor of approx. 200kΩ . PWDN/ACK = 5V 7 Output high (source) current I OH 0.4 4.0 mA V OUT =V DD -0.4V 8 Output low (sink) current I OL 1.0 9.0 mA V OUT =V SS +0.4V
MT3170B/71B, MT3270B/71B, MT3370B/71B 4-9 ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing * Test Conditions 1. dBm refers to a reference power of 1 mW delivered into a 600 ohms load. 2. Data sequence consists of all DTMF digits. 3. Tone on = 40 ms, tone off = 40 ms. 4. Signal condition consists of nominal DTMF frequencies. 5. Both tones in composite signal have an equal amplitude. 6. T one pair is deviated by ±1.5%± 2 Hz. 7. Bandwidth limited (0-3 kHz) Gaussian noise. 8. Precise dial tone frequencies are 350 Hz and 440 Hz (± 2%). 9. Referenced to lowest level frequency component in DTMF signal. 10. Referenced to the minimum valid accept level. 11. Both tones must be within valid input signal range. 12. External guard time for MT3x70B = 20ms. 13. Timing parameters are measured with 70pF load at SD output. 14. Time duration between PWDN pin changes from ‘1‘ to ‘0‘ and ESt/DStD becomes active. 15. Guaranteed by design and characterization. Not subject to production testing. 16. Value measured with an applied tone of 450 Hz. otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions*
1 Valid input signal level
(each tone of composite signal) -50 2.45 775 dBm mV RMS 1,2,3,5,6,12
2 Positive twist accept 8 dB 1, 2,3,4,11,12,15
3 Negative twist accept 8 dB 1,2,3,4,11,12,15
4 Frequency deviation accept ±1.5%± 2Hz 1,2,3,5,12 5 Frequency deviation reject ±3.5% 1,2,3,5,12,15
6 Third tone tolerance -16 dB 1, 2,3,4,5,12
7 Noise tolerance -12 dB 7,9,12
8 Dial tone tolerance +15 dB 8,10,12
9 Supervisory tones detect level
(Total power) -35 dBm 16
10 Supervisory tones reject level -50 dBm 16
11 Energy detector attack time t
SA 1.0 6.5 ms 16
12 Energy detector decay time t SD 32 5 m s 1 6
≤ 100µA MT3170B/3370B MT3171B/3371B Note 14
14 Tone present detect time (ESt
logic output) t DP 3 13 20 ms MT3x70B
15 Tone absent detect time (ESt
logic output) tDA 3 15 ms MT3x70B
16 Tone duration accept
(DStD logic output) tREC 40 ms MT3x71B
17 Tone duration reject
(DStD logic output) tREC 20 ms MT3x71B
18 Interdigit pause accept (DStD
logic output) tID 40 ms MT3x71B
19 Interdigit pause reject (DStD
logic output) tDO 20 ms MT3x71B 20 Data shift rate 40-60% duty cycle fACK 1.0 3.0 MHz 13,15
21 Propagation delay
(ACK to Data Bit) tPAD 100 140 ns 1MHz f ACK , 13,15