MSX532

MSX532 FAIRCHILD | Alldatasheet

Document overview

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Technical content

Features

I SRAM-based, in-system programmable I Configurable I/O Ports

• Individually programmable as input, output, bi-directional, or Bus Repeater mode  Control Signals per I/O port: 2 input enables, 2 output enables, 2 Global Clock inputs and Next Neighbor Clock option  Output data inversion: capable of inverting output signals in flow through mode I Non-blocking switch matrix  One-to-One and One-to-Many connections Double-buffered configuration RAM cells for simultaneous global updates I Registered and flow-through data modes  Up to 75 MHz clock frequency in registered mode  Up to 150 Mb/s in flow-through mode I 20 ns propagation delay in flow-through mode I 8 mA output current I Dedicated RapidConfigure parallel interface or JTAG serial interface available for configuration and readback of MSX devices I 3.3V operation, LVTTL I/O's (5V tolerant) I MSX532 is offered in a 792 TBGA package

Applications

 Telecom and datacom switching  Video switches and servers  Test equipment Ordering Code: MSX  , Bus Repeater , and RapidConfigure are trademarks of Fairchild Semiconductor Corporation. Order Number Package Number Package Description MSX532TB792 BGA792A 792-Ball Thermally-Enhanced Ball Grid Array (TBGA), JEDEC MO-149, 1.0mm pitch, 40mm Square

registered). The signal can also be inverted at the output. explained in more detail in the following section. FIGURE 3. MSX I/O Buffer Block Diagram

www.fairchildsemi.com 4 MSX532 Introduction (Continued) Option 1: Registered Input with Next-Neighbor Clock as Input Option 2: Registered Output with Next-Neighbor Clock as Input

5 www.fairchildsemi.com MSX532 Introduction (Continued) Option 3: Registered Input with Next-Neighbor Clock as Output Option 4: Registered Output with Next-Neighbor Clock as Output

TABLE 1. Summary for Programmable I/O Attributes for MSX Devices corresponding Switch Matrix line. to invert the output signal.

7 www.fairchildsemi.com MSX532 Introduction (Continued) Array Side Force 1 In this input mode, the Switch Matrix line is forced HIGH (logic 1), regardless of the signal on the corresponding I/O Port. In this mode an optional input enable (IE) can be selected. Bidirectional Transceiver with Register Input This mode combines Registered Input and buffered Output (OP). This mode requires a clock source (CLK), and input enable (IE) and output enable (OE BT & RI Bidirectional Transceiver with Register Output This mode combines Registered Output (RO) and buffered Input (IE). This mode requires a clock source (CLK), and input enable (IE) and output enable (OE BT & RO The output data inversion mode is NOT available to invert the output signal. Bidirectional Transceiver with Register I/O This mode combines Registered Input (RI) and Registered Output (RO). This mode requires a clock source (CLK), and input enable (IE) and output enable (OE BT, RI & RO The output data inversion mode is NOT available to invert the output signal. DQ IE AxPx CLK OE DQ IE Ax Px CLK OE D 1 Q 1 IE AxPx CLK_IN OE CLK_OP Q 0 D 0

TABLE 2. MSX Global Control Signals enable reading back of configuration data from the device. FIGURE 4. MSX Switch Configuration Signals determine the type of operation being performed.

TABLE 3. RapidConfigure Input When RCI[1:0] are equal to 11 a Read or Reset command is executed (see Table 4: Reset Commands). TABLE 4. Reset Commands (Continued) RCC[0], RCB[9:0], and RCA[9:0] have no function during a reset command and must be written as zeroes. crosspoint array. These commands are generally only used for diagnostic testing. connection information. It can also be used to reset all of the I/O buffers and the crosspoint array. 00 Reserved. This is not a valid command. 01 Reserved. This is not a valid command.

TABLE 5. I/O Buffer Read Commands

0 I/O buffer not set to input

1 I/O buffer set to input (default)

device is not connected to the crosspoint array. RCA[1] will read as a zero at reset.

0 I/O buffer not set to output (default)

1 I/O buffer set to output

Repeater Mode. Bus Repeater Mode will be disabled by default at reset, so RCA[2] will read as a zero.

0 I/O buffer not set to Bus Repeater Mode (default)

1 I/O buffer set to Bus Repeater Mode

RCA[3] RCA[3] is set to a one if the I/O buffer is configured as a registered input and is assigned to use its Input Clock 1. quadrant of the device in which it resides. RCA[3] will read as a zero at reset.

0 I/O buffer not set to registered input mode (default)

1 I/O buffer set to registered input mode

RCA[4] RCA[4] is set to a one if the I/O buffer is configured as a registered input and is assigned to use its Input Clock 2. quadrant of the device in which the I/O buffer resides. RCA[4] will read as a zero at reset.

0 I/O buffer not using Input Clock Source 2 in RI mode (default)

1 I/O buffer using Input Clock Source 2 in RI mode

Neighbor Clocking will be disabled by default at reset, so RCA[5] will read as a zero.

0 I/O buffer not using Next Neighbor Clock in RI mode (default)

1 I/O buffer using Next Neighbor Clock in RI mode

1. It is zero if the I/O buffer is not using Output Clock 1. As with Input Clock 1 and 2, the Output Clocks will vary

Clock 2 do as well. RCA[6] will read as a zero at reset.

0 I/O buffer not using Output Clock Source 1 in RO mode (default)

1 I/O buffer using Output Clock Source 1 in RO mode

1. It is zero if the I/O buffer is not using Output Clock 2. As with Output Clock 1, the source changes depending

upon the quadrant of the device in which the I/O buffer resides. RCA[7] will read as a zero at reset.

0 I/O buffer not using Output Clock Source 2 in RO mode (default)

1 I/O buffer using Output Clock Source 2 in RO mode

11 www.fairchildsemi.com MSX532 Introduction (Continued) Signal Description RCA[8] RCA[8] is set to a one if the I/O buffer is configured as a registered output and is assigned to use Next Neighbor Clocking. It is zero if Next Neighbor Clocking is disabled. Next Neighbor Clocking allows the I/O buffer to be regis- tered using the next higher numbered Port number signal as its output clock source. Port 100 on the MSX devices can use the signal from Port 101 for its output clock if this mode is enabled. Port 531’s Next Neighbor is Port 0. Next Neighbor Clocking will be disabled by default at reset, so RCA[8] will read as a zero. RCA[8] Function

0 I/O buffer not using Next Neighbor Clock in RO mode (default)

1 I/O buffer using Next Neighbor Clock in RO mode

RCA[9] RCA[9] is set to a one if the I/O buffer is assigned to use Input Enable 1. It is zero if the I/O buffer is not using Input Enable 1. All bi-directional I/O buffers must use one of the dedicated input enable pins (IE_0, IE_1, IE_2, or IE_3) to enable the I/O buffer to drive data into the crosspoint array. As with the dedicated clock pins, each I/O buffer can access two input enable signals, which will vary depending upon the quadrant of this chip in which the I/O buffer resides. RCA[9] will read as a zero at reset. RCA[9] Function

0 I/O buffer not using Input Enable Source 1 (default)

1 I/O buffer using Input Enable Source 1

RCB[0] RCB[0] is set to a one if the I/O buffer is assigned to use Input Enable 2. It is zero if the I/O buffer is not using Input Enable 2. RCB[0] will read as a zero at reset. RCB[0] Function

0 I/O buffer not using Input Enable Source 2 (default)

1 I/O buffer using Input Enable Source 2

RCB[1] RCB[1] is set to a one if the I/O buffer is assigned to use Output Enable 1. It is zero if the I/O buffer is not using Output Enable 1. All bi-directional I/O buffers must use one of the dedicated output enable pins (OE _0, OE_1, OE _2, or OE_3) to enable the I/O buffer to drive the pin of the device. As with the dedicated clock pins, each I/O buffer can access two output enable signals, which will vary depending upon the quadrant of the chip in which the I/O buffer resides. RCB[1] will read as a zero at reset. RCB[1] Function

0 I/O buffer not using Output Enable Source 1 (default)

1 I/O buffer using Output Enable Source 1

RCB[2] RCB[2] is set to a one if the I/O buffer is assigned to use Output Enable 2. It is zero if the I/O buffer is not using Output Enable 2. RCB[2] will read as a zero at reset. RCB[2] Function

0 I/O buffer not using Output Enable Source 2 (default)

1 I/O buffer using Output Enable Source 2

RCB[6:3] RCB[6:3] are reserved. RCB[7] RCB[7] is set to a one if the I/O buffer is configured as an inverted output. It is zero if the I/O buffer is not config- ured as an inverted output. The output of any I/O buffer may be inverted so long as it is not a registered output or running in Bus Repeater Mode. RCB[7] will read as a zero at reset. RCB[7] Function

0 I/O buffer not configured as inverted output (default)

1 I/O buffer configured as inverted output

RCB[8] RCB[8] is set to a one if the I/O buffer is configured as a registered input and is using an inverted input clock source. It is zero if it is not using an inverted input clock. Inputs can use any of the three clock sources described above and may invert that clock if desired. RCB[8] will read as a zero at reset. RCB[8] Function

0 I/O buffer not using inverted clock source in RI mode (default)

1 I/O buffer using inverted clock source in RI mode

RCB[9] RCB[9] is set to a one if the I/O buffer is configured as a registered output and is using an inverted output clock source. It is zero if it is not using an inverted output clock. Outputs can use any of the three clock sources described above and may invert that clock if desired. RCB[9] will read as a zero at reset. RCB[9] Function

0 I/O buffer not using inverted clock source in RO mode (default)

1 I/O buffer using inverted clock source in RO mode

www.fairchildsemi.com 12 MSX532 Introduction (Continued) Crosspoint Programming Connections between ports through the crosspoint array can be quickly made or broken using the RC interface. The two ports to be connected or disconnected are addressed using RCA[9:0] and RCB[9:0]. RCC[1] controls whether a connection is made or broken. The two ports are con- nected when RCC[1] is set to zero, and disconnected when RCC[1] is set to one Unlike I/O buffer programming commands, which take effect immediately upon execution of the command, cross- point connections will only be made if the UPDATE signal is asserted HIGH. The crosspoint programming command loads the Loading SRAM cell in the selected crosspoint array location with a one (in the case of a new connection) or a zero (to break an existing connection). If the UPDATE signal is asserted, the Loading SRAM cells contents are immediately transferred to the Active SRAM cell and the connection is made or broken. However, if the UPDATE signal is held LOW, the new connection will not be made. The UPDATE signal can be used to control when the switch matrix connections are reconfigured. I/O Buffer Configuration Programming Each port can be fully configured in a single RapidConfig- ure cycle. The figure below shows how an I/O buffer is pro- grammed using all of the signals on the RC interface. The following table shows how each control bits (RCC[3:0] and RCB[9:0]) are used. During an I/O buffer programming command the RCA[9:0] signals address the port to be pro- grammed (see Table 6: I/O buffer Programming Com- mands) 1 00 1 0 RCI[1:0] RCC[3:0] RCB[9:0] RCA[9:0] Connect/Disconnect (0-Connect, 1-Disconnect) 1234567890123456789012301 Crosspoint Program Port #1 Port #2 0 1 RCI[1:0] RCC[3:0] RCB[9:0] RCA[9:0] 1234567890123456789012301 I/O Buffer Configuration I/O Buffer Address Bus Repeater Enable Input/Output Select Output Enable Select Input Enable Select Output Clock Source Input Clock Source Invert Output Inverted Input Clock Inverted Output Clock

TABLE 6. I/O Buffer Programming Commands bi-directional mode. When zero the I/O buffer will not operate in Bus Repeater Mode. When programming an I/O buffer to use Bus Repeater Mode, all of the other control bits must be set to zeroes. Attempting to combine other I/O buffer options with Bus Repeater Mode may lead to unpredictable results. input and output enables so that it can be 3-STATED appropriately to avoid contention.

00 No Connect

01 Input

10 Output

11 Input / Output for Bi-Directional Mode

able active LOW output enable signals are AND’ed together to form the port’s combined output enable signal.

00 No Output Enable Selected

01 Output Enable 1

10 Output Enable 2

11 Both Output Enables

00 No Input Enable Selected

01 Input Enable 1

10 Input Enable 2

11 Both Input Enables

will operate in flow-through mode.

00 No Output Clock Source Selected

01 Output Clock Source 1

10 Output Clock Source 2

11 Next Neighbor Output Clock Source

operate in flow-through mode.

00 No Input Clock Source Selected

01 Input Clock Source 1

10 Input Clock Source 2

11 Next Neighbor Input Clock Source

Mode or in registered output mode. inverted. When zero the input clock source will not be inverted.

Table 7 lists the bits and their function in JTAG mode. register for I/O buffer programming. TABLE 7. I/O Buffer Programming Bit Functions Note 1: If both IE_1 and IE_2 are selected, the two are assigned an OR function to form the IE. Either can be “1” to enable the input. inverted. When zero the output clock source will not be inverted.

0 Input (IN) Input Pin Data to Drive Array

1 Output (OP) Output Array Data to Pin

2 Bus Repeater (BR) Low Array Signal, Drive Pin LOW

9 Input Enable 1 (IE_1) Select Input Enable 1 (Note 1)

10 Input Enable 2 (IE_2) Select Input Enable 2 (Note 1)

11 Output Enable 1 (OE_1) Select Output Enable 1 (Note 2)

12 Output Enable 2 (OE_2) Select Output Enable 2 (Note 2)

13 Force 1 Force I/O Buffer Output Pin to a 1

14 Force 0 Force I/O Buffer Output Pin to a 0

15 Array 1 Force I/O Buffer Array to a 1

16 Array 0 Force I/O Buffer Array to a 0

17 Invert Output Output data is inverted.

18 Invert Input Clock Invert the Clock to the Input Register

19 Invert Output Clock Invert the Clock to the Output Register

TABLE 8. JTAG Input Format TABLE 9. JTAG Instructions Resets I/O buffers for the Ports to Input and clear all Ports to Disconnect. become the ’B’ Address for Crosspoint Access. (B Address). Read data is shifted out on TDO. C1 C0 = 0 0 Read Switch with A and B Address. Increment ’B’ address with each ShiftDR. C1 C0 = 0 1 Connect switch at location Addressed with A and B. Increment ’B’ address with each ShiftDR. Activate with UpdateDR. C1 C0 = 1 0 Disconnect switch at location Addressed with A and B. Increment ’B’ address with each ShiftDR. Activate with UpdateDR. C1 C0 = 1 1 Force update of Switch Array Shadow register. grammed state of the I/O buffer is not changed. 1 0 0 0 Clear the Crosspoint Array Clear the crosspoint array at no-connect. Leave the I/O buffers unchanged. Instruction. Read data is placed in the twenty-bit I/O buffer Copy Register. Write Data for the I/O buffer is from the I/O buffer Data Register. C1 C0 = 0 0 Read an I/O buffer date into the Copy Register. C1 C0 = 0 1 Write an I/O buffer with data in I/O buffer Data Register. Fairchild only - internal test mode to test RapidConfigure through JTAG. Instruction Address = Lower Limit = A, Address Register = Upper Limit = B. 0 0 0 0 Sample/Preload EXTEST External scan tests for interconnect testing. 0 0 0 1 Sample/Preload EXTEST External scan tests for interconnect testing.

17 www.fairchildsemi.com MSX532 Introduction (Continued) Device Reset Options At power-on, all MSX532 I/O buffers are set as flow- through inputs (IN) with input enable ON, and the switch matrix set to all No Connects (NC). The RapidConfigure reset, hardware reset, and JTAG reset functions will program the I/O buffers to flow-through input (IN) mode with input enable ON, and each Loading SRAM cell in the Switch Matrix is set to No Connect. An UPDATE signal is required to complete the operation and set the Active SRAM cells to No Connect. The JTAG interface can be reset via the TRST pin or by clocking five consecutive one to the TMS pin. The hard- ware reset pin can be done accomplished through the HW_RST pin (Active LOW). RC reset can be accomplished by applying the RC Instruction 1101 to the RCI[3:0] pins. Device Reset Options Note 3: NC = No Connect. Each Loading SRAM cell in the Switch Matrix is updated to No Connect. An UPDATE signal is required to complete the operation and set the Active SRAM cells to No Connect. Note 4: TLR = T est Logic Reset State. Programming Reset I/O Switch RCE Mode JTAG Interface Method Port Matrix Control TAP Hardware Reset Power-on Reset IN NC 1 (RC Enabled) TLR (Note 3) HW_RST (Low Pulse) IN NC (Note 4) 1 (RC Enabled) TLR JTAG Reset 1. Low Pulse on TRST Unchanged Unchanged Unchanged TLR 2. TMS High for 5 SCLK Cycles Unchanged Unchanged Unchanged TLR 3. Device Reset (Instruction 1101) IN NC (Note 3) 1 (RC Enabled) TLR 4. Reset Crosspoint Array (Instruction 1101) Unchanged NC (Note 3) Unchanged Unchanged RapidConfigure Reset 1. Device Reset (Instruction 1101) IN NC (Note 3) 1 (RC Enabled) Unchanged 2. Reset Crosspoint Array (Instruction 0010) Unchanged NC (Note 3) Unchanged Unchanged

www.fairchildsemi.com 18 MSX532 Pin Description Pin Name Type Description P[531:000] Bi-directional Input/Output Signals. OE[3:0] Input Global Output Enables. Each output enable can control two of the four I/O banks. Signal MSX532 Connected I/O ’s OE _0 P399-P531, P000-P132 OE _1 P000-P132, P133-P265 OE _2 P133-P265, P266-P398 OE _3 P266-P398, P399-P531 IE[3:0] Input Global Input Enables. Each input enable can control two of the four I/O banks. Signal MSX532 Connected I/O ’s IE_0 P399-P531, P000-P132 IE_1 P000-P132, P133-P265 IE_2 P133-P265, P266-P398 IE_3 P266-P398, P399-P531 UPDATE Input Global Update CLK[3:0] Input Global Clocks. Each clock can control two of the four I/O banks. Signal MSX532 Connected I/O ’s CLK_0 P399-P531, P000-P132 CLK_1 P000-P132, P133-P265 CLK_2 P133-P265, P266-P398 CLK_3 P266-P398, P399-P531 HW_RST Input Hardware Reset. RCE Input RapidConfigure Mode Select Programing mode is determined at power up or HW_RST 0 = JTAG Mode (RapidConfigure Disabled) 1 = RapidConfigure Mode (JTAG, I/O buffer, Crosspoint Programming Disabled) Note: Device can be reconfigured from JTAG to RC or from RC to JTAG in the JTAG mode without HW_RST or power up. In RapidConfigure mode the programming of the I/O buffers and crosspoint array through JTAG is disabled, but the JTAG port can still be used for boundary scan testing. RC Pins RC_CLK Input RapidConfigure Clock. RC_EN Input RapidConfigure Cycle Enable. RCA[9:0] Bi-directional RapidConfigure Address A. RCB[9:0] Bi-directional RapidConfigure Address B. RCC[0] Bi-directional RapidConfigure Program Variable C. RCC[3:1] Input RapidConfigure Program Variable C. RCI[1:0] Input RapidConfigure Instruction Bits. RC_RDY Output Read Out I/O Buffer and Connect/Disconnect Status. JTAG Pins TCK Input JTAG Test Clock. TDI Input JTAG Test Data In. TDI Output JTAG Test Data Out. TMS Input JTAG Test Mode Select. TRST Input JTAG Test and JTAG Scan Reset. Power and Ground Pins VDD Power +3.3V power for the chip. VSS Ground Ground for the chip. Tie these pins to system ground.

19 www.fairchildsemi.com MSX532 Absolute Maximum Ratings(Note 5) Recommended Operating Conditions Note 5: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Rat- ings. The “Recommended Operating Conditions” table will define the condi- tions for actual device operation. Note 6: A maximum undershoot of 2V for a maximum duration of 20 ns is acceptable. Overshoot to 5.5V is acceptable. Note 7: All inputs are 5V tolerant with the V DD pin at 3.3V. Note 8: Measured using Human Body Model. Pin Capacitance (Note 9) Note 9: Capacitance measured at 25°C. Sample tested only. Note 10: See Power Consumption section for dynamic power consumption calculation. Supply Voltage VDD -0.3V to +3.6 V Supply Voltage (Inputs) VIN (Note 6)(Note 7) -0.3V to +5.5V Junction Temperature TJ +150°C Storage Temperature TSTG -65°C to +150°C Maximum Power Dissipation PMAX 10.5W Electrostatic Discharge ESD (Note 8) 1500V Supply Voltage VDD +3.0V to +3.6V Operating Temperature TA 0°C to +70°C Symbol Parameter Limits Units C CLK Input Capacitance 10.0 pF C PORT I/O Signal Port Capacitance 8.0 pF Symbol Parameter Conditions Min Max Units VIH HIGH Level Input Ports are 5V Tolerant 2.1 5.25 V VIL LOW Level Input Ports are 5V Tolerant -0.3 0.8 V VOH HIGH Level Output V DD = Min 2.4 V DD + 0.3 VVDD = 3.00 IOH = -4 mA VOL LOW Level Output V DD = Min 0.4 VVDD = 3.00 IOL = 8 mA ILIH, ILIL Input Leakage V DD = Max +5.0 µA for Non-programmable I/O pins 0.0 < I n < VDD -600 ILOZ 3-STATE Leakage Output OFF State V DD = Max +5.0 µA 0.0 < In < VDD -100 IOSH Short Circuit Current, V DD = Max -80.0 mA Out = HIGH V 0 = GND IOSL Short Circuit Current, V DD = Max 80.0 mA Out = LOW V 0 = VDD Supply Current IDDQ Quiescent Supply Current V DD = Max 96.0 mA Q DDD Dynamic Supply Current V DD = Max. No Load, 0.375 mA/MHz (Note 10) One Input Cycling @ 50% Duty Cycle

www.fairchildsemi.com 20 MSX532 Refer to Figure 7 for AC test conditions. Symbol Parameter Min Max Units R DATA NRZ Data Rate 150 Mb/s fRIO Registered Input/Output Clock Frequency 75.0 MHz tW_RIO Registered Clock Pulse Width, HIGH or LOW 3.0 ns tS_RI Registered Input Setup Time to Clock 5.0 ns tS_RO Registered Output Setup Time to Clock 9.5 ns tH_RI Registered Input Clock to Hold Data 0.0 ns tH_RO Registered Output Clock to Hold Data 0.0 ns tCO_RO Registered Output Clock to Data Out Valid 11.0 ns tCO_RI Registered Input Clock to Data Out Valid 24.0 ns tPHL , tPLH One Way Signal Propagation Delay, Fanout = 1 20.0 ns tMC Delta Additional Delay Per Output Multicast (MC) Mode 2.0 ns tW+ Input Flow-through Positive Pulse Width 6.0 tW- Input Flow-through Negative Pulse Width 6.0 tSK Skew 4.0 ns tPZH_IT, Input Enable to Valid Data 20.0 ns tPZL_IT tPZH_OT , Output Enable to Valid Data 7.5 ns tPZL_OT tPZH_OT , Output Enable to High Z State 7.5 ns tPZL_OT tRC RapidConfigure Clock Period 20.0 ns tW+_RC RapidConfigure Clock Pulse Width 8.0 ns tW-_RC tS_RC RapidConfigure Address Setup to RC Clock 1.0 ns tH_RC RapidConfigure Address Hold Time to RC Clock 4.0 ns tP_RC Read Back Access Time 9.0 ns tP_RD RC_RDY to Readback Data 4.0 ns tP_UD Update of Crosspoint to Data Out 10.0 ns fJTAG JTAG Clock Frequency (TCK) 8.0 MHz tW_JTAG JTAG Clock Pulse Width (TCK) at 8 MHz Cycle 48.0 72.0 ns tS_JTAG JTAG Setup Time 4.0 ns tH_JTAG JTAG Hold Time 0.0 ns tP_JTAG JTAG Clock to Output Data Valid (TDO) 10.0 ns

FIGURE 15. RapidConfigure I/O Buffer or Crosspoint Read and Write Cycles

FIGURE 16. RapidConfigure Reset Command Cycle

25 www.fairchildsemi.com MSX532 Package and Pinout MSX532 [792 TBGA Package] Pinout 37 38 39 Vss Vss C D E F G H J K L M N P R T U V W Y AA AB AC AD AP AR AT AU RCA1 Vss Vss IE_1 P135 P145P068 Vdd P019 Vdd Vss RCC3 P510 Vdd Vdd Vdd Vss Vss OE_3 #Vss P373 Vdd P265 P279 Vss Vss Vss P166 P191 Vss Vdd P027 Vdd P078 P404 P380 Vdd P331 P469 Vdd P520 Vdd Vss P198 Vss P151 RCA9 RCA7 RCB1 RCA8 RCA2 RCA6 RCA3 Vss Vss IE_0 RCB3 Vss Vdd RCB6 OE_0 TDO P521 P523 P525 P527 UPDAT E P526 P528 P530 RCE RC_E RCI0 Vss RCC2 RCB9 RCB8 RCB7 P499 Vss Vdd Vdd P504 P502 P511 P506 Vss Vdd Vdd P513 P512 P518 P517 Vss P489 P500 P494 P503 P488 VddP495 P471 P473 P475 Vdd Vdd P476 P479 P480 P481 P482 Vss Vdd P484 P485 P493 P492 P468 P466 P422 Vdd P424 Vdd P421 Vdd Vss Vss Vss P417 P416 IE_3 P414 P409 P408 C D E F G H J K L M N P R T U V W Y AA AB AC AD AP AR AT AU 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 TCK P00 P00 Vdd RC_R DY TMS P03 P03 P00 TDI P02 P02 P03 Vdd Vdd P02 P02 P01 P00 P01 Vdd Vdd P02 P02 1P011 P008 P015 P01 P399 P396 P397 Vdd P395 P393 P391 P389 Vdd Vdd P385 P384 P381 P378 P379 Vdd P364 P363 P361 P360 P358 Vdd P357 P356 P352 P350 P351 Vdd P346 P347 P341 P340 P369P386 P376 P370 P374 P411 P371 Vdd Vdd P398 P402 P353 P367 Vdd P388 P403 P405 P413 P041 Vss Vss OE_1# P189 P188 P130 P142 P083 P079 P132 Vdd Vdd Vdd Vss P082 P169 Vdd P170 Vdd Vdd P073 P072 P069 P077 P076P067 Vdd P062 P063 P057 P056 Vdd P048 P059 P053 P052 P046 P047 P049 Vdd P058 P066 P042 P036 P038 Vdd Vdd P043 Vdd P039 P158 P185 P184 P180 P187 P160 Vss P150 P155 P154 Vdd P149 Vdd P181P179 P178 P172 P174 P176 P148 P146 P138 P143 P144 Vdd CLK_1 P139 P171 P163 P164 P167 P161 P157 Vdd Vdd P343 P342 P337 P336 P330 P332 P333 Vdd Vdd P327 Vss P277 P275 P280 P281 P215 P219 P218 P223 P213 P214 P216 Vdd P224 P225 Vdd P222 P200 Vss P204 P207 Vss Vss P266 P326 P270 P272 Vdd P273 P196 Vdd P205 P202 P194 P195 P190 P199 Vdd P208 P209 P211 MSX532 in 792 TBGA Top View P134 AV Vss Vss VssVss P415 P412 P406 AV P394 P392 P382 P377 P365 P359 P354 P348 P349 P368Vss P375P401 P344 P339 P335 OE_2# Vss P328 AW Vss Vss VssVss P410 P407 Vss AW Vss P390 P383 Vss P362 Vss P355 Vss P345 P366P387 P372P400 Vss P338 P334 P284 Vss P329 Vss Vss B Vss HW_RS T# BP00 P00 P03 P00 P03 P02 P02 P017 P01

3 P040 Vss Vss

A Vss TRST # AP00 P00 P03 Vss P03 3P02 Vss P016 P01

2 Vss Vss Vss

RC_CLK RCC1 P505 P509 P515 P516 P498 P496 P472 P477 P478 P486 P491 P467 P420 Vss Vss Vss Vss Vss Vss Vss Vss P137 Vdd Vss P162 Vdd P212 P220 Vdd P173 Vdd P133 Vss Vss Vss P186 Vss P168 Vdd P182 P183 P152 P153 P147 P177 Vdd P175 P141 P140 P136 P165 P156 P159 P192 Vss Vss Vdd P221 P210 P217 P227 Vdd P203 P201 P276 Vss Vss P274 P197 P193 P206 Vdd Vss P278 Vss CLK_2 P128 P131 Vss Vss P296Vdd IE_2 P319 P310 P312 P313 P315 Vdd P306 P309 P302 P304 P305 P297 P299 P298 P290 P293 Vdd Vdd P303 P316 Vdd Vdd P292 P295 P289 P286 P283 P282 P285 P318 P314 P308 P307 P301 P294 P288 P287 P320 P317 P311 Vss P300 Vss P291 Vss P321 P323 P322 P325 P324 Vss P109P098 Vss P093 P092 P095 P094 P096 P100 P101 P103 P102 P104 P105 P108 P111 P110 P112 P113 P089 P091 Vss P090 P118 P119 P115 P114 P121 P120 P123 P122 P124 Vdd P097 Vdd P107 Vdd P117 Vdd P127 Vdd P099 Vdd P106 Vdd P116 Vdd P129 Vss P085 P084 P087 P086 P088 AE AF AG AH AJ AK AL AM AN Vss Vss P251 Vdd Vss P261 Vss P459 P458 P461 P460 P464 Vss P449 Vdd P454 Vdd P451 P453P450 Vdd P430 P432 Vss P435 P436 P433 Vdd Vdd P440 P441 P442 P447 P443 Vdd Vdd Vss P429 P423 P425 AE AF AG AH AJ AK AL AM AN P229 P226P230 P232 P255 P260 P263 Vdd Vdd P254 P256 P258 P264 P267 P271 Vss Vdd P241 P244 P247 P236 P240 P243 P242 P233 P235 Vdd P237 P249 Vss P250 P252 P462 P457 P455 P431 P437 P438 P444 P448 P426 P231 Vdd Vdd P238 P228 Vdd P259 P262 P253 P257 P269 P268 P245 Vdd P239 P234 P246 P248 27 28 29 30 31 32 33 34 35 36 37 38 39123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 Vss CLK_ Vss Vss RCA4 RCB0 RCB4 P524 P531 RCI1 RCC0 P507 P508 P514 P519 P501 P490 P497 P470 P474 P483 P487 P465 P456 P463 Vss P419 Vss Vss P446 P452 P428 P434 P439 P445 P427 CLK_ Vss

TABLE 10. MSX532 Pinout By Ball Sequence

27 www.fairchildsemi.com MSX532 Package and Pinout (Continued) Ball Ball Name Ball Ball Name Ball Ball Name Ball Ball Name Ball Ball Name Ball Ball Name G1 V SS H1 RCB7 J1 V SS K1 RCE L1 P526 M1 P521 G2 RCB3 H2 RCB6 J2 RCC2 K2 RC_EN L2 P528 M2 P523 G3 RCB2 H3 RCB5 J3 RCC1 K3 RC_CLK L3 P529 M3 P522 G4 RCB0 H4 RCB4 J4 RCC0 K4 RCI1 L4 P531 M4 P524 G5 RCA9 H5 V DD J5 RCB9 K5 RCI0 L5 P530 M5 P525 G6 RCA7 H6 V DD J6 RCB8 K6 RCC3 L6 UPDATE M6 P527 G34 P138 H34 V DD J34 P150 K34 P157 L34 P163 M34 V DD G35 P141 H35 V DD J35 P152 K35 P156 L35 P162 M35 V DD G36 P140 H36 P147 J36 P153 K36 P159 L36 P165 M36 P168 G37 P143 H37 P149 J37 P155 K37 P158 L37 P164 M37 P169 G38 P144 H38 P148 J38 P154 K38 P160 L38 P167 M38 P171 G39 P146 H39 P151 J39 V SS K39 P161 L39 P166 M39 P170 N1 V SS P1 P512 R1 V SS T1 P502 U1 V SS V1 P495 N2 P517 P2 P513 R2 P506 T2 P504 U2 P499 V2 P494 N3 P516 P3 P515 R3 P509 T3 P505 U3 P498 V3 P496 N4 P519 P4 P514 R4 P508 T4 P507 U4 P501 V4 P497 N5 P518 P5 V DD R5 P511 T5 V DD U5 P500 V5 V DD N6 P520 P6 V DD R6 P510 T6 V DD U6 P503 V6 V DD N34 P172 P34 V DD R34 P180 T34 V DD U34 P190 V34 V DD N35 P173 P35 V DD R35 P183 T35 V DD U35 P192 V35 V DD N36 P175 P36 P177 R36 P182 T36 P186 U36 P193 V36 P197 N37 P174 P37 P179 R37 P184 T37 P189 U37 P195 V37 P196 N38 P176 P38 P178 R38 P185 T38 P188 U38 P194 V38 P199 N39 V SS P39 P181 R39 P187 T39 P191 U39 V SS V39 P198 W1 P488 Y1 P485 AA1 V SS AB1 P479 AC1 P475 AD1 P468 W2 P489 Y2 P484 AA2 P482 AB2 P476 AC2 P473 AD2 P466 W3 P491 Y3 P486 AA3 P478 AB3 P477 AC3 P472 AD3 P467 W4 P490 Y4 P487 AA4 P483 AB4 P474 AC4 P470 AD4 P465 W5 P492 Y5 V DD A A 5P 4 8 1A B 5 V DD A C 5P 4 7 1A D 5 V DD W6 P493 Y6 V DD A A 6P 4 8 0A B 6 V DD A C 6P 4 6 9A D 6 V DD W34 P200 Y34 V DD AA34 P213 AB34 V DD AC34 P223 AD34 V DD W35 P201 Y35 V DD AA35 P212 AB35 V DD AC35 P220 AD35 V DD W36 P203 Y36 P206 AA36 P210 AB36 P217 AC36 P221 AD36 P227 W37 P202 Y37 P207 AA37 P211 AB37 P216 AC37 P218 AD37 P225 W38 P205 Y38 P204 AA38 P209 AB38 P214 AC38 P219 AD38 P224 W39 V SS Y39 P208 AA39 V SS AB39 P215 AC39 V SS AD39 P222

www.fairchildsemi.com 28 MSX532 Package and Pinout (Continued) Ball Ball Name Ball Ball Name Ball Ball Name Ball Ball Name Ball Ball Name Ball Ball Name AE1 V SS AF1 P458 AG1 P450 AH1 P451 AJ P443 AK1 P441 AE2 P464 AF2 P459 AG2 P454 AH2 P449 AJ2 P447 AK2 P440 AE3 P462 AF3 P457 AG3 P455 AH3 P448 AJ3 P444 AK3 P438 AE4 P463 AF4 P456 AG4 P452 AH4 P446 AJ4 P445 AK4 P439 A E 5P 4 6 0A F 5 V DD AG5 P453 AH5 V DD AJ5 P442 AK5 V DD A E 6P 4 6 1A F 6 V DD AG6 V SS AH6 V DD AJ6 V SS AK6 V DD AE34 P230 AF34 V DD AG34 P240 AH34 V DD AJ34 P249 AK34 V DD AE35 P231 AF35 V DD AG35 P238 AH35 V DD AJ35 P248 AK35 V DD AE36 P228 AF36 P234 AG36 P239 AH36 P245 AJ36 P246 AK36 P253 AE37 P229 AF37 P235 AG37 P236 AH37 P242 AJ37 P247 AK37 P252 AE38 P226 AF38 P233 AG38 P237 AH38 P243 AJ38 P244 AK38 P250 AE39 V SS AF39 P232 AG39 V SS AH39 P241 AJ39 V SS AK39 P251 AL1 P433 AM1 P432 AN1 V SS AL2 P436 AM2 P430 AN2 P429 AL3 P437 AM3 P431 AN3 P426 AL4 P434 AM4 P428 AN4 P427 AL5 P435 AM5 V DD AN5 P425 AL6 V SS AM6 V DD AN6 P423 AL34 P258 AM34 V DD AN34 P271 AL35 P259 AM35 V DD AN35 P268 AL36 P257 AM36 P262 AN36 P269 AL37 P256 AM37 P263 AN37 P267 AL38 P254 AM38 P260 AN38 P264 AL39 P255 AM39 P261 AN39 V SS

29 www.fairchildsemi.com MSX532 Package and Pinout (Continued) Ball Ball Name Ball Ball Name Ball Ball Name Ball Ball Name Ball Ball Name Ball Ball Name AP1 P424 AR1 V SS AT1 V SS AU1 V SS AV1 V SS AW1 V SS AP2 P422 AR2 P421 AT2 OE _3 AU2 V SS AV2 V SS AW2 V SS AP3 P420 AR3 P418 AT3 V SS AU3 V SS AV3 V SS AW3 V SS AP4 P419 AR4 V SS AT4 V SS AU4 V SS AV4 CLK_3 AW4 V SS AP5 V DD AR5 V SS AT5 V SS AU5 P417 AV5 P415 AW5 P410 AP6 V DD AR6 IE_3 AT6 P416 AU6 P414 AV6 P412 AW6 P407 AP7 P413 AR7 P411 AT7 P409 AU7 P408 AV7 P406 AW7 V SS AP8 P404 AR8 P405 AT8 P402 AU8 P403 AV8 P401 AW8 P400 AP9 P398 AR9 P399 AT9 P396 AU9 P397 AV9 P394 AW9 V SS AP10 V DD AR10 V DD AT10 P395 AU10 P393 AV10 P392 AW10 P390 AP11 P391 AR11 P389 AT11 P388 AU11 P386 AV11 V SS AW11 P387 AP12 V DD AR12 V DD AT12 P385 AU12 P384 AV12 P382 AW12 P383 AP13 P380 AR13 P381 AT13 P378 AU13 P379 AV13 P377 AW13 V SS AP14 V DD AR14 V DD AT14 P376 AU14 P374 AV14 P375 AW14 P372 AP15 P373 AR15 P370 AT15 P371 AU15 P369 AV15 P368 AW15 P366 AP16 V DD AR16 V DD AT16 P367 AU16 P364 AV16 P365 AW16 P362 AP17 P363 AR17 P361 AT17 P360 AU17 P358 AV17 P359 AW17 V SS AP18 V DD AR18 V DD AT18 P357 AU18 P356 AV18 P354 AW18 P355 AP19 P353 AR19 P352 AT19 P350 AU19 P351 AV19 P348 AW19 V SS AP20 V DD AR20 V DD AT20 P346 AU20 P347 AV20 P349 AW20 P345 AP21 P341 AR21 P340 AT21 P343 AU21 P342 AV21 P344 AW21 V SS AP22 V DD AR22 V DD AT22 P336 AU22 P337 AV22 P339 AW22 P338 AP23 P331 AR23 P330 AT23 P332 AU23 P333 AV23 P335 AW23 P334 AP24 V DD AR24 V DD AT24 P327 AU24 P326 AV24 P328 AW24 P329 AP25 P321 AR25 P323 AT25 P322 AU25 P325 AV25 P324 AW25 V SS AP26 V DD AR26 V DD AT26 P316 AU26 P319 AV26 P318 AW26 P320 AP27 P310 AR27 P312 AT27 P313 AU27 P315 AV27 P314 AW27 P317 AP28 V DD AR28 V DD AT28 P306 AU28 P309 AV28 P308 AW28 P311 AP29 P303 AR29 P302 AT29 P304 AU29 P305 AV29 P307 AW29 V SS AP30 P296 AR30 P297 AT30 P299 AU30 P298 AV30 P301 AW30 P300 AP31 P290 AR31 P293 AT31 P292 AU31 P295 AV31 P294 AW31 V SS AP32 V DD AR32 V DD AT32 P286 AU32 P289 AV32 P288 AW32 P291 AP33 IE_2 AR33 P283 AT33 P282 AU33 P285 AV33 P287 AW33 V SS AP34 V DD AR34 P279 AT34 P281 AU34 P280 AV34 OE _2 AW34 P284 AP35 V DD AR35 V SS AT35 V SS AU35 P276 AV35 P278 AW35 CLK_2 AP36 P274 AR36 V SS AT36 V SS AU36 V SS AV36 V SS AW36 V SS AP37 P272 AR37 P277 AT37 V SS AU37 V SS AV37 V SS AW37 V SS AP38 P270 AR38 P273 AT38 P275 AU38 V SS AV38 V SS AW38 V SS AP39 P265 AR39 P266 AT39 V SS AU39 V SS AV39 V SS AW39 V SS

TABLE 11. MSX532 Pinout By Ball Name (alphabetically)

31 www.fairchildsemi.com MSX532 Ball Name Ball Ball Name Ball Ball Name Ball Ball Name Ball Ball Name Ball P187 R39 P227 AD36 P267 AN37 P307 AV29 P347 AU20 P188 T38 P228 AE36 P268 AN35 P308 AV28 P348 AV19 P189 T37 P229 AE37 P269 AN36 P309 AU28 P349 AV20 P 1 9 0 U 3 4 P 2 3 0A E 3 4P 2 7 0A P 3 8P 3 1 0A P 2 7P 3 5 0A T 1 9 P191 T39 P231 AE35 P271 AN34 P311 AW28 P351 AU19 P192 U35 P232 AF39 P272 AP37 P312 AR27 P352 AR19 P193 U36 P233 AF38 P273 AR38 P313 AT27 P353 AP19 P194 U38 P234 AF36 P274 AP36 P314 AV27 P354 AV18 P195 U37 P235 AF37 P275 AT38 P315 AU27 P355 AW18 P196 V37 P236 AG37 P276 AU35 P316 AT26 P356 AU18 P197 V36 P237 AG38 P277 AR37 P317 AW27 P357 AT18 P198 V39 P238 AG35 P278 AV35 P318 AV26 P358 AU17 P199 V38 P239 AG36 P279 AR34 P319 AU26 P359 AV17 P200 W34 P240 AG34 P280 AU34 P320 AW26 P360 AT17 P201 W35 P241 AH39 P281 AT34 P321 AP25 P361 AR17 P202 W37 P242 AH37 P282 AT33 P322 AT25 P362 AW16 P203 W36 P243 AH38 P283 AR33 P323 AR25 P363 AP17 P204 Y38 P244 AJ38 P284 AW34 P324 AV25 P364 AU16 P205 W38 P245 AH36 P285 AU33 P325 AU25 P365 AV16 P206 Y36 P246 AJ36 P286 AT32 P326 AU24 P366 AW15 P207 Y37 P247 AJ37 P287 AV33 P327 AT24 P367 AT16 P208 Y39 P248 AJ35 P288 AV32 P328 AV24 P368 AV15 P209 AA38 P249 AJ34 P289 AU32 P329 AW24 P369 AU15 P210 AA36 P250 AK38 P290 AP31 P330 AR23 P370 AR15 P211 AA37 P251 AK39 P291 AW32 P331 AP23 P371 AT15 P212 AA35 P252 AK37 P292 AT31 P332 AT23 P372 AW14 P213 AA34 P253 AK36 P293 AR31 P333 AU23 P373 AP15 P214 AB38 P254 AL38 P294 AV31 P334 AW23 P374 AU14 P215 AB39 P255 AL39 P295 AU31 P335 AV23 P375 AV14 P216 AB37 P256 AL37 P296 AP30 P336 AT22 P376 AT14 P217 AB36 P257 AL36 P297 AR30 P337 AU22 P377 AV13 P218 AC37 P258 AL34 P298 AU30 P338 AW22 P378 AT13 P219 AC38 P259 AL35 P299 AT30 P339 AV22 P379 AU13 P220 AC35 P260 AM38 P300 AW30 P340 AR21 P380 AP13 P221 AC36 P261 AM39 P301 AV30 P341 AP21 P381 AR13 P222 AD39 P262 AM36 P302 AR29 P342 AU21 P382 AV12 P223 AC34 P263 AM37 P303 AP29 P343 AT21 P383 AW12 P224 AD38 P264 AN38 P304 AT29 P344 AV21 P384 AU12 P225 AD37 P265 AP39 P305 AU29 P345 AW20 P385 AT12 P226 AE38 P266 AR39 P306 AT28 P346 AT20 P386 AU11

www.fairchildsemi.com 32 MSX532 Ball Name Ball Ball Name Ball Ball Name Ball Ball Name Ball Ball Name Ball P387 AW11 P427 AN4 P467 AD3 P507 T4 RCB3 G2 P388 AT11 P428 AM4 P468 AD1 P508 R4 RCB4 H4 P389 AR11 P429 AN2 P469 AC6 P509 R3 RCB5 H3 P390 AW10 P430 AM2 P470 AC4 P510 R6 RCB6 H2 P391 AP11 P431 AM3 P471 AC5 P511 R5 RCB7 H1 P392 AV10 P432 AM1 P472 AC3 P512 P1 RCB8 J6 P393 AU10 P433 AL1 P473 AC2 P513 P2 RCB9 J5 P394 AV9 P434 AL4 P474 AB4 P514 P4 RCC0 J4 P395 AT10 P435 AL5 P475 AC1 P515 P3 RCC1 J3 P396 AT9 P436 AL2 P476 AB2 P516 N3 RCC2 J2 P397 AU9 P437 AL3 P477 AB3 P517 N2 RCC3 K6 P398 AP9 P438 AK3 P478 AA3 P518 N5 RCE K1 P399 AR9 P439 AK4 P479 AB1 P519 N4 RCI0 K5 P400 AW8 P440 AK2 P480 AA6 P520 N6 RCI1 K4 P401 AV8 P441 AK1 P481 AA5 P521 M1 RC_RDY D6 P402 AT8 P442 AJ5 P482 AA2 P522 M3 TCK D7 P403 AU8 P443 AJ1 P483 AA4 P523 M2 TDI F7 P404 AP8 P444 AJ3 P484 Y2 P524 M4 TDO E7 P405 AR8 P445 AJ4 P485 Y1 P525 M5 TMS C6 P406 AV7 P446 AH4 P486 Y3 P526 L1 TRST P407 AW6 P447 AJ2 P487 Y4 P527 M6 UPDATE L6 P408 AU7 P448 AH3 P488 W1 P528 L2 V DD E8 P409 AT7 P449 AH2 P489 W2 P529 L3 V DD E10 P410 AW5 P450 AG1 P490 W4 P530 L5 V DD E12 P411 AR7 P451 AH1 P491 W3 P531 L4 V DD E14 P412 AV6 P452 AG4 P492 W5 RC_CLK K3 V DD E16 P413 AP7 P453 AG5 P493 W6 RC_EN K2 V DD E18 P414 AU6 P454 AG2 P494 V2 RCA0 E3 V DD E20 P415 AV5 P455 AG3 P495 V1 RCA1 D2 V DD E22 P416 AT6 P456 AF4 P496 V3 RCA2 F5 V DD E24 P417 AU5 P457 AF3 P497 V4 RCA3 E2 V DD E26 P418 AR3 P458 AF1 P498 U3 RCA4 F4 V DD E28 P419 AP4 P459 AF2 P499 U2 RCA5 F3 V DD E30 P420 AP3 P460 AE5 P500 U5 RCA6 E1 V DD E32 P421 AR2 P461 AE6 P501 U4 RCA7 G6 V DD F6 P422 AP2 P462 AE3 P502 T1 RCA8 F2 V DD F8 P423 AN6 P463 AE4 P503 U6 RCA9 G5 V DD F10 P424 AP1 P464 AE2 P504 T2 RCB0 G4 V DD F12 P425 AN5 P465 AD4 P505 T3 RCB1 F1 V DD F14 P426 AN3 P466 AD2 P506 R2 RCB2 G3 V DD F16

33 www.fairchildsemi.com MSX532 Ball Name Ball Ball Name Ball Ball Name Ball Ball Name Ball Ball Name Ball VDD F18 V DD AF6 V DD AR32 V SS E4 V SS AU3 VDD F20 V DD AF34 V SS A1 V SS E5 V SS AU4 VDD F22 V DD AF35 V SS A2 V SS E35 V SS AU36 VDD F24 V DD AH5 V SS A3 V SS E36 V SS AU37 VDD F26 V DD AH6 V SS A4 V SS G1 V SS AU38 VDD F28 V DD AH34 V SS A7 V SS J1 V SS AU39 VDD F30 V DD AH35 V SS A11 V SS J39 V SS AV1 VDD F32 V DD AK5 V SS A15 V SS N1 V SS AV2 VDD F34 V DD AK6 V SS A19 V SS N39 V SS AV3 VDD H5 V DD AK34 V SS A21 V SS R1 V SS AV11 VDD H6 V DD AK35 V SS A25 V SS U1 V SS AV36 VDD H34 V DD AM5 V SS A29 V SS U39 V SS AV37 VDD H35 V DD AM6 V SS A33 V SS W39 V SS AV38 VDD M34 V DD AM34 V SS A35 V SS AA1 V SS AV39 VDD M35 V DD AM35 V SS A36 V SS AA39 V SS AW1 VDD P5 V DD AP5 V SS A37 V SS AC39 V SS AW2 VDD P6 V DD AP6 V SS A38 V SS AE1 V SS AW3 VDD P34 V DD AP10 V SS A39 V SS AE39 V SS AW4 VDD P35 V DD AP12 V SS B1 V SS AG6 V SS AW7 VDD T5 V DD AP14 V SS B2 V SS AG39 V SS AW9 VDD T6 V DD AP16 V SS B3 V SS AJ6 V SS AW13 VDD T34 V DD AP18 V SS B37 V SS AJ39 V SS AW17 VDD T35 V DD AP20 V SS B38 V SS AL6 V SS AW19 VDD V5 V DD AP22 V SS B39 V SS AN1 V SS AW21 VDD V6 V DD AP24 V SS C1 V SS AN39 V SS AW25 VDD V34 V DD AP26 V SS C2 V SS AR1 V SS AW29 VDD V35 V DD AP28 V SS C3 V SS AR4 V SS AW31 VDD Y5 V DD AP32 V SS C4 V SS AR5 V SS AW33 VDD Y6 V DD AP34 V SS C36 V SS AR35 V SS AW36 VDD Y34 V DD AP35 V SS C37 V SS AR36 V SS AW37 VDD Y35 V DD AR10 V SS C38 V SS AT1 V SS AW38 VDD AB5 V DD AR12 V SS C39 V SS AT3 V SS AW39 VDD AB6 V DD AR14 V SS D1 V SS AT4 VDD AB34 V DD AR16 V SS D3 V SS AT5 VDD AB35 V DD AR18 V SS D4 V SS AT35 VDD AD5 V DD AR20 V SS D5 V SS AT36 VDD AD6 V DD AR22 V SS D35 V SS AT37 VDD AD34 V DD AR24 V SS D36 V SS AT39 VDD AD35 V DD AR26 V SS D37 V SS AU1 VDD AF5 V DD AR28 V SS D39 V SS AU2

TABLE 12. Package Thermal Characteristics This element equals 0.006 mW x Mb/s x connections. This element equals 0.013 mW x number of outputs x Mb/s x capacitive load (pF). spoint Array and the I/O Buffer. tings. All Bits programmed in the JTAG Mode. the RCE pin during a reset of the circuits. gramming and changing program information all at once. any port to any other port or any combination of other ports. array has a diagonal line where the cells are rotated. before a read and one is pulled LOW for a write. Power Consumption = Steady State Component + Connection Component + Output Drive Component.

35 www.fairchildsemi.com MSX532 Glossary (Continued) Extest: A JTAG instruction that samples I/O pin states and loads new I/O buffer states for testing device pin connec- tions. The MSX devices use a special test mode in Extext to observe the buffer data on the pin side and the array side. A bit in the Control Register controls this mode. I/O Buffer: The circuit that controls the driving of its associ- ated pin and its port into and out of the Crosspoint Array. The buffer contains all the circuits to make it independent of the other I/O Buffers. Each Buffer contains registers for input and output, driving circuits for input and output, sense for Crosspoint Array input, and RAM bits to hold pro- grammed data controlling the function of the buffer. Input or Output Path: The signal flow from pin to array and array to pin. Each path has a register with selectable clocks, drivers for the loaded outputs with selectable enables, and sense circuits to detect changes on either side of the I/O Buffer. JTAG: The Joint Test Action group is a committee to stan- dardize scan testing of devices. The JTAG interface is referred to as IEEE 1149.1. This is a five bit serial program- ming and testing method. JTAG Sequence: The ordering of all the pins in a serial chain for driving and sensing signals on pins during Extest and Sample/Preload. All pins except power and ground and the five JTAG pins are in the serial string. Next Neighbor: Input can be selected as the clock for the I/O buffer registers for data and clock pairing. The next higher port is the selected neighbor except for Port 531, which uses Port 0. Pin Side Driver: The I/O Buffer circuit that drives the device pin associated with that buffer. Port: A name followed by a number to identify a pin on the device. Ports are numbered from 531 to 0 on the MSX device. In shifting sequence, Port P000 is shifted in first and shifted out first. RapidConfigure: A parallel programming method for the MSX devices. The RC mode uses 29 dedicated pins to pro- gram the Crosspoint Array and the I/O Buffers. The 29 pins consist of an enable, a strobe, two instruction bits, four variable bits, and two ten-bit address fields. RCE: A control pin of the MSX device that is sampled dur- ing reset to determine if the device becomes active in the JTAG or the RapidConfigure mode. This pin places the Control Register bit in the state to allow RC operations or not based on the voltage level of the RCE pin. The JTAG mode is always enabled and can set or clear the RC bit in the Control Register. Trickle Current: A very low current (~15 microamperes) used to pull unused or non-driven circuits to a stable HIGH level. Prevents signals from drifting between CMOS thresh- olds and drawing currents from the power supply. In the case of Bus Repeater, the small trickle current provides a known high level on the pin and array side inputs.

www.fairchildsemi.com 36 MSX532 532 Port Digital Crosspoint Switch with LVTTL I/O’s Physical Dimensions inches (millimeters) unless otherwise noted 792-Ball Thermally-Enhanced Ball Grid Array (TBGA), JEDEC MO-149, 1.0mm pitch, 40mm Square Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com