ADP2164 AD | Alldatasheet
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Technical content
6.5 V, 4 A, High Efficiency,
Step-Down DC-to-DC Regulator Data Sheet ADP2164 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.
FEATURES
4 A continuous output current
43 mΩ and 29 mΩ integrated FET ±1.5% output accuracy Input voltage range: 2.7 V to 6.5 V Output voltage: 0.6 V to V IN Switching frequency Fixed frequency: 600 kHz or 1.2 MHz Adjustable frequency: 500 kHz to 1.4 MHz Synchronizable from 500 kHz to 1.4 MHz Selectable synchronize phase shift: 0° or 180° Current mode architecture Precision enable input Power-good output Voltage tracking input Integrated soft start Internal compensation Starts up into a precharged output UVLO, OVP , OCP , and thermal shutdown Available in 16-lead, 4 mm × 4 mm LFCSP package
APPLICATIONS
Communications and networking equipment Industrial and instrumentation Consumer electronics TYPICAL APPLICATIONS CIRCUIT 09944-001 ADP2164 PGOOD EN COUT C1R2 RT CIN VOUT VIN SYNC TRK RT SW FB PGND GND VIN L PVIN Figure 1. 100 OUTPUT CURRENT (A) EFFICIENCY (%) 09944-002 VIN = 5V fS = 600kHz VOUT = 1.2V VOUT = 3.3V Figure 2. Efficiency vs. Output Current control scheme for excellent stability and transient response. operation allows low dropout voltage at 4 A output current.
Rev. 0 | Page 2 of 20 TABLE OF CONTENTS
REVISION HISTORY
12/11—Revision 0: Initial Version
Rev. 0 | Page 3 of 20 SPECIFICATIONS VIN = PVIN = 3.3 V , EN high, SYNC high, TJ = −40°C to +125°C, unless otherwise noted. Typical values are at TJ = 25°C. Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit VIN AND PVIN PINS VIN Voltage Range VIN 2.7 6.5 V PVIN Voltage Range PVIN 2.7 6.5 V Quiescent Current IVIN No switching 895 1100 μA Shutdown Current ISHDN VIN = PVIN = 6.5 V, EN = GND 9 12 μA VIN Undervoltage Lockout Threshold UVLO VIN rising 2.6 2.7 V VIN falling 2.4 2.5 V OUTPUT CHARACTERISTICS Specified by the circuit in Figure 42 Load Regulation IO = 0 A to 4 A 0.05 %/A Line Regulation IO = 2 A 0.05 %/V FB PIN FB Regulation Voltage VFB T J = −40°C to +125°C 0.591 0.6 0.609 V FB Bias Current IFB 0.01 0.1 μA SW PIN High-Side On Resistance1 VIN = PVIN = 3.3 V, ISW = 500 mA 35 52 70 mΩ VIN = PVIN = 5 V, ISW = 500 mA 30 43 55 mΩ Low-Side On Resistance1 VIN = PVIN = 3.3 V, ISW = 500 mA 24 32 40 mΩ VIN = PVIN = 5 V, ISW = 500 mA 20 29 35 mΩ SW Peak Current Limit High-side switch, PVIN = 3.3 V 5 6.2 7.4 A SW Maximum Duty Cycle Full frequency 100 % SW Minimum On Time2 Full frequency 100 ns TRK PIN TRK Input Voltage Range 0 600 mV TRK to FB Offset Voltage TRK = 0 mV to 500 mV −15 +15 mV TRK Input Bias Current 100 nA FREQUENCY Switching Frequency fS RT = VIN 1.08 1.2 1.32 MHz RT = GND 540 600 660 kHz RT = 91 kΩ 480 600 720 kHz Switching Frequency Range 500 1400 kHz RT Pin Input High Voltage 1.2 V RT Pin Input Low Voltage 0.45 V SYNC PIN Synchronization Range 0.5 1.4 MHz Minimum Pulse Width 100 ns Minimum Off Time 100 ns Input High Voltage 1.2 V Input Low Voltage 0.4 V PGOOD PIN Power-Good Range FB rising threshold 105 110 115 % FB rising hysteresis 2.5 % FB falling threshold 85 90 95 % FB falling hysteresis 2.5 % Power-Good Deglitch Time From FB to PGOOD 16 Clock cycles Power-Good Leakage Current VPGOOD = 5 V 0.1 1 μA Power-Good Output Low Voltage IPGOOD = 1 mA 170 220 mV
Rev. 0 | Page 4 of 20 Parameter Symbol Test Conditions/Comments Min Typ Max Unit INTEGRATED SOFT START Soft Start Time All switching frequencies 2048 Clock cycles EN PIN EN Input Rising Threshold 1.12 1.2 1.28 V EN Input Hysteresis 100 mV EN Pull-Down Resistor 1 MΩ THERMAL SHUTDOWN Thermal Shutdown Threshold TJ increasing 140 °C Thermal Shutdown Hysteresis 15 °C 1 Pin-to-pin measurements. 2 Guaranteed by design.
Table 3. Thermal Resistance
- THE EXPOSED PAD SHOULD BE SOLDERED
THE IC FOR THERMAL DISSIPATION. Figure 3. Pin Configuration Table 4. Pin Function Descriptions resistor from this pin to GND (see the Oscillator and Synchronization section for more information). connect this pin directly to VOUT. 5 GND Analog Ground. Connect to the ground plane. 6, 7, 8 PGND Power Ground. Connect to the ground plane and to the output return side of the output capacitor. 9, 10, 11 SW Switch Node Output. Connect to the output inductor. part automatically, connect the EN pin to VIN. This pin has a 1 MΩ pull-down resistor to GND. 16 PGOOD Power-Good Output (Open Drain). Connect this pin to a resistor from any pull-up voltage lower than 6.5 V. 17 (EPAD) Exposed Pad The exposed pad should be soldered to an external ground plane under the IC for thermal dissipation.
Figure 10. Feedback Voltage vs. Temperature, VIN = 3.3 V Figure 11. PFET Resistor vs. VIN (Pin-to-Pin Measurements)
1125 FREQUENCY (kHz)
Figure 12. Switching Frequency vs. VIN, fS = 1.2 MHz (RT = VIN) Figure 13. EN Threshold vs. Temperature Figure 14. NFET Resistor vs. VIN (Pin-to-Pin Measurements)
560 FREQUENCY (kHz)
Figure 15. Switching Frequency vs. VIN, fS = 600 kHz (RT = GND)
550 FREQUENCY (kHz)
Figure 16. Switching Frequency vs. VIN, fS = 600 kHz (RT = 91 kΩ) Figure 17. Peak Current Limit vs. Temperature, VIN = 3.3 V Figure 18. Soft Start with Full Load, VIN = 5 V, VOUT = 1.2 V, fS = 1.2 MHz Figure 19. UVLO Threshold vs. Temperature, VIN = 3.3 V Figure 20. Peak Current Limit vs. VIN, TJ = 25°C Figure 21. Soft Start with Precharged Output Voltage, VIN = 5 V, fS = 1.2 MHz
Figure 36. Functional Block Diagram
Rev. 0 | Page 15 of 20 POWER GOOD PGOOD is an active high, open-drain output and requires a resistor to pull it up to the logic supply voltage. PGOOD high indicates that the voltage on the FB pin (and, therefore, the output voltage) is within 10% of the desired value. PGOOD low indicates the opposite. There is a 16-cycle waiting period after the FB voltage is detected as being out of bounds. If FB returns to within the ±10% range, it is ignored by the PGOOD circuitry. CURRENT LIMIT AND SHORT-CIRCUIT PROTECTION The ADP2164 has a peak current limit protection circuit to prevent current runaway. The peak current limit is 6.2 A. When the inductor current reaches the peak current limit, the high-side MOSFET turns off and the low-side MOSFET turns on until the next cycle begins. The overcurrent counter is incremented by 1 at each peak current limit event. If the overcurrent counter exceeds 10, the part enters hiccup mode, and the high-side FET and low-side FET are both turned off. The part remains in this mode for 4096 clock cycles and then attempts to restart using soft start. If the current limit fault has cleared, the part resumes normal operation. If the current limit fault has not cleared, the part reenters hiccup mode after first counting 10 current limit violations. OVERVOLTAGE PROTECTION (OVP) Overvoltage protection (OVP) circuitry is integrated in the ADP2164. The output voltage is continuously monitored by a comparator through the FB pin, which is at 0.6 V (typical) under normal operation. The comparator is activated when the FB voltage exceeds 0.66 V (typical), thus indicating an output overvoltage condition. If the voltage remains above the OVP threshold for 16 clock cycles, the high-side MOSFET turns off and the low-side MOSFET turns on until the current through it reaches the −1.3 A current limit. Both MOSFETs remain in the off state until FB falls below 0.54 V (typical), after which the part restarts. The behavior of PGOOD under this condition is described in the Power Good section. UNDERVOLTAGE LOCKOUT (UVLO) Undervoltage lockout (UVLO) circuitry is integrated in the ADP2164. If the input voltage falls below 2.5 V , the ADP2164 shuts down, and both the power switch and the synchronous rectifier turn off. When the voltage rises above 2.6 V again, the soft start is initiated, and the part is enabled. THERMAL SHUTDOWN If the ADP2164 junction temperature rises above 140°C, the thermal shutdown circuit turns off the regulator. Extreme junc- tion temperatures can be the result of high current operation, poor circuit board design, and/or high ambient temperature. When thermal shutdown occurs, a 15°C hysteresis ensures that the ADP2164 does not return to operation until the on-chip temperature falls below 125°C. Soft start is initiated when the part comes out of thermal shutdown.
COMPLIANT TOJEDEC STANDARDS MO-220-WGGC.
0.05 MAX
0.02 NOM
0.20 REF
Figure 48. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Rev. 0 | Page 20 of 20 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D09944-0-12/11(0)