MSP58C20DW

MSP58C20 TI | Alldatasheet

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Technical content

SPSS015B – DECEMBER 1993 – REVISED JULY 1996 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Analog Portion of ADC and DAC for Audio-Band Signal-Processing

Applications

/C00685-V Supply Voltage /C0068Oversampling Second-Order Sigma-Delta Modulator /C00681.024-MHz Master Clock Frequency /C0068On-Chip Continuous-Time Antialiasing and Smoothing Filters /C0068High-Performance Fully Differential and Symmetrical Analog Data Paths /C0068Internal Reference Voltage and Common-Mode Bias Voltage Generation /C0068Very Low Power Consumption Mode

description

The MSP58C20 is the analog portion of an audio-band sigma-delta analog-to-digital and digital-to-analog converter and is a companion part to the MSP58C80. The MSP58C20 is designed to operate only with the MSP58C80, which contains the digital portion of the audio-band converter. The circuit consists of three main blocks: the analog-to-digital converter (ADC), the digital-to-analog converter (DAC), and internal reference and bias voltages. The analog-to-digital conversion chain consists of a continuous-time antialiasing stage, an analog oversampled modulator, and the modulator bias voltage. The antialiasing stage is a second-order low-pass filter with a cutoff frequency of typically 190 kHz. The modulator is a sigma-delta feedback loop, which oversamples the signal at 1.024 MHz and provides second-order noise shaping. It performs the conversion of the differential analog input signal to a pulse-density-modulated single-bit digital output (ADOUT). When a maximum positive differential input voltage (i.e., a maximum positive voltage difference of AIP – AIM) is applied at the AIP and AIM inputs, the resulting code at the ADOUT output is all ones. The digital-to-analog conversion chain consists of a fast DAC, an analog low-pass filter, and the filter’s bias voltage. The two input bits (DIGS and DIGL), sampled at 0.512 MHz from a digital modulator on the MSP58C80, are the inputs of the DAC conversion chain. Based on the values for DIGS (the sign bit) and DIGL (the level bit), the following table shows the DAC voltage steps that are produced. DIGS DIGL DAC VOLTAGE STEPS L L –1 × Vref L H –2 × Vref H L +1 × Vref H H +2 × Vref When DIGS = L, the AOM analog output has a more positive voltage than AOP. When DIGL = H, the absolute value of the voltage difference between AOP and AOM is greater than when DIGL = L. A band-gap voltage source is used to produce the DAC and ADC reference voltages. These two references are different to avoid crosstalk between the two converters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  1996, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. VSUB NC VSS AIP AIM PWAD PWDA ADOUT NC NC NC NC AOP AOM DIGS DIGL ADCLK V DD NC NC DW PACKAGE (TOP VIEW) NC – No internal connection

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1.024 MHz

SPSS015B – DECEMBER 1993 – REVISED JULY 1996 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL A/D I/O DESCRIPTIONNAME NO. A/D I/O DESCRIPTION ADCLK 14 D I ADCLK is a 1.024-MHz clock input. ADOUT 8 D O ADOUT is the 1-bit output of the ADC modulator and is sampled at 1.024 MHz. AIM 5 A I AIM is a negative differential input for the ADC. AIP and AIM together form a balanced differential input. The biasing of this terminal is fixed through resistors by the internal common-mode voltage source. This terminal can be ac coupled or dc coupled. If the terminal is dc coupled, external common-mode bias should satisfy recommended operating conditions. AIP 4 A I AIP is a positive differential input for the ADC. AIP and AIM together form a balanced differential input. The biasing of this terminal is fixed through resistors by the internal common-mode voltage source. This terminal can be ac coupled or dc coupled. If the terminal is dc coupled, external common-mode bias should satisfy recommended operating conditions. AOM 17 A O AOM is a negative differential DAC output. AOP and AOM together form a balanced differential output. The common-mode voltage at this terminal is fixed by the internal common-mode circuitry. AOP 18 A O AOP is a positive differential DAC output. AOP and AOM together form a balanced differential output. The common-mode voltage at this terminal is fixed by the internal common-mode circuitry. DIGL 15 D I DIGL is the input level bit of the DAC and is sampled at 0.512 MHz. DIGS 16 D I DIGS is the input sign bit of the DAC and is sampled at 0.512 MHz. PWAD 6 D I When PWAD is high, it puts the ADC part of the circuit into a power-down mode. When both PWAD and PWDA are high, the MSP58C20 is in a stable low-power-consumption state. PWDA 7 D I When PWDA is high, it puts the DAC part of the circuit in a power-down mode. When both PWAD and PWDA are high, the MSP58C20 is in a stable low-power-consumption state. VSUB 1 n/a n/a VSUB and VSS must be connected together to minimize substrate currents during power up, power down, and normal operation. VDD 13 n/a n/a VDD is the 5-V power supply. VSS 3 n/a n/a VSS is ground. The internal band-gap voltage and the common-mode bias voltages are referenced to VSS . absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS unless otherwise noted.

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recommended operating conditions MIN NOM MAX UNIT Supply voltage, VDD (see Note 1) 4.75 5 5.25 V High-level input voltage, digital inputs, VIH (see Note 1) 2 V Low-level input voltage, digital inputs, VIL (see Note 1) 0.8 V Maximum differential input voltage between AIP and AIM (ac or dc peak-to-peak voltage), VID –3 3 V Common-mode input voltage at AIP and AIM, VIC (see Note 1) 0.45 × VDD 0.5 × VDD 0.55 × VDD V Input clock frequency, ADCLK 1.024 MHz Resistive load between AOP and AOM 15 kW Capacitive load at AOP and AOM (at each output versus VSS ) 50 pF Operating free-air temperature, TA 0 70 °C NOTE 1: All voltage values are with respect to VSS unless otherwise noted.

SPSS015B – DECEMBER 1993 – REVISED JULY 1996 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature, ADCLK input frequency = 1.024 MHz, PWDA = L and PWAD = L (power-up mode) (unless otherwise noted) supply current characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PWAD =H, PWDA = H, I Supply current Digital inputs = VDD or VSS , 50 mA IDD Supply current Digital output = no load m PWAD = L, PWDA = L 6.5 9 16 mA analog input characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Transmit dynamic range, maximum differential input voltage (between AIP and AIM) dc or ac voltage ± 2.22 ± 2.36 ± 2.5 V VIO Transmit differential input offset voltageSee Note 2 –150 150 mV VIC Internal common-mode voltage at AIP and AIM 0.4 × VDD 0.5 × VDD 0.6 × VDD V zi Input impedance AIP Between AIP and internal common-mode voltage source (AIM = VDD /2) 15 25 35 kWzi Input impedance AIM Between AIM and internal common-mode voltage source (AIP = VDD /2) 15 25 35 kW Input capacitance AIP Measured at 5 MHz between AIP and VSS (AIM = VDD /2) 50 pFInput capacitance AIM Measured at 5 MHz between AIM and VSS (AIP = VDD /2) 50 pF NOTE 2: Calculated by linear regression based on five dc measurements between –1 V and 1 V digital output characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH Digital high-level output voltage versus VSS IOH = 300 mA 2.4 V VOL Digital low-level output voltage versus VSS IOL = 1 mA 0.4 V analog output characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOD Differential output voltage, dynamic range, AOP to AOMBalanced loads, dc measurement ± 2.82 ± 3 ± 3.18 V VOO Differential output offset voltage dc measurement –150 150 mV VOC Common-mode output voltage at AOP and AOM 0.4 × VDD 0.5 × VDD 0.6 × VDD V

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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature, ADCLK input frequency = 1.024 MHz, PWDA = L and PWAD = L (power-up mode) (unless otherwise noted) (continued) ADC transmit characteristics† PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Transmit absolute gain tolerance VDD = 5 V, T A = 25°C, Input = 1-kHz sine wave at –13 dBrl ± 0.5 dB Ti t i Input = 1-kHz sine wave, Gi f l l i Input level = –1 dBrl to –43 dBrl ± 0.25 Transmit gain versus input level Gain reference level = gain measured at input level of Input level = –43 dBrl to –53 dBrl ± 0.5 dBin ut level measured at in ut level of –13 dBrl, See Note 3Input level = –53 dBrl to –58 dBrl ± 1 Transmit gain versus VDD =47 5Vt o52 5V I n put = 1 kHz at 13 dBrl ± 01 5 dBg supply voltage VDD = 4.75 V to 5.25 V, Input = 1 kHz at –13 dBrl ± 0.15 dB Transmit idle channel in-band noise Psophometrically-weighted output noise, Transmit channel idle –76 dBrlp f = 50 Hz –80 f = 300 Hz –82 Transmit idle channel TA = 25°C, f = 3.4 kHz –82Transmit idle channel single-frequency noise TA = 25 C , FFT rectangular window bandwidth = 125 Hz, f = 4 kHz –80 dBrl spectrum (see Note 4) Transmit channel idle, See Figure 5 f = 7 kHz –72 f = 12 kHz –65 f = 20 kHz –64 Transmit single- frequency distortion Input = one frequency in 0.7-kHz to 1.1-kHz band at –4 dBrl, Measured first two harmonics –50 dB Transmit intermodulation distortion (see Note 4) Input = two frequencies in 0.3-kHz to 3.4-kHz band, Input levels = –7 dBrl and –24 dBrl, Measured second and third intermodulation products –40 dBrl Transmit signal to total VDD = 5.25 V, TA = 25°C, Input level = –70 dBrl –13 Transmit-signal-to-total- noise-plus-distortion ratio (see Note 5) A , Input = 1-kHz sine wave, Measured psophometrically- Input level = –20 dBrl 50 dB (see Note 5) y weighted total noise plus distortion, See Figure 6 Input level = –1 dBrl 50 Transmit gain variations versus input frequency (see Notes 4 and 6) f = 0.1 kHz to 4 kHz, Input level = –13 dBrl ± 0.6 dB Transmit power supply rejection See Note 7 30 dB Ilk Leakage current Voltage applied to terminal is between VSS and VDD , AIP –10 10 mAIlkg Leakage current g SS DD , PWDA = H (power-down mode) AIM –10 10 mA Receive-to-transmit crosstalk Receive input = one frequency in 0.3-kHz to 3.4-kHz band at –3 dBrl, Crosstalk measured at transmit digital output, Transmit channel idle –70 dB † This table contains specifications in which the power levels are expressed in dBrl; dBrl stands for dB above reference level. 0 dBrl is the ADC theoretical overload point. This overload point corresponds to a sine wave at the input of the modulator with peak amplitude equal to 2.25 V dBrlp is a psophometrically-weighted value being compared against a psophometrically-weighted reference. NOTES: 3. Input satisfies CCITT G.714 15.3, Method 2. 4. This parameter is characterized but not tested. 5. Input satisfies CCITT G.714 14.3, Method 2. 6. Gain is relative to gain at 1 kHz. 7. The power-supply rejection measurement is made with a 50-mVrms, 0- to 20-kHz signal applied to VDD and with the transmit channel idle.

SPSS015B – DECEMBER 1993 – REVISED JULY 1996 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature, ADCLK input frequency = 1.024 MHz, PWDA = L and PWAD = L (power-up mode) (unless otherwise noted) (continued) DAC receive characteristics† PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Receive gain tolerance VDD = 5 V, T A = 25°C, Input = 1-kHz sine wave at –28 dBrl ± 0.5 dB Input = 1-kHz sine wave, Gi f l l i Input level = –1 dBrl to –43 dBrl ± 0.25 Receive gain versus input levelGain reference level = gain measured at input level of–28dBrl, Input level = –43 dBrl to –53 dBrl ± 0.5 dBmeasured at in ut level of –28dBrl, See Note 8 Input level = –53 dBrl to –58 dBrl ± 1 Receive gain versus supply voltage VDD = 4.75 V to 5.25 V, Digital input = 1-kHz sine wave at –28 dBrl ± 0.15 dB Receive idle channel in-band noise Receive channel idle, Psophometrically-weighted output noise –75 dBrlp TA =2 5°C f = 100 Hz –82 Receive idle channel single frequency noise TA = 25°C , Receive channel idle, f = 3 kHz –82 dBrlsingle-frequency noise spectrum (see Note 4) Measurement bandwidth = 125 Hz, SF i 6 f = 10 kHz –64 dBrl s ectrum (see Note 4) See Figure 6 f = 100 kHz –64 Receive single-frequency distortion Input = one frequency in 0.7-kHz to 1.1-kHz band at –6 dBrl, Measured first two harmonics –50 dB Receive intermodulation distortion (see Note 4) Input = two frequencies in 0.3-kHz to 3.4-kHz band, Input levels = –7 dBrl and –24 dBrl, Measured second and third intermodulation products –40 dBrl Receive signal-to-total-noise- VDD = 5.25 V, TA = 25°C, Inpu t=1-kHz sine wave Input level = –70 dBrl 0 Receive signal-to-total-noise- plus-distortion ratio (see Note 9) In ut = 1-kHz sine wave, Measured psophometrically- weighted total noiseplus Input level = –20 dBrl 50 dB (see N ote 9) we ighted total noise plus distortion, See Figure 7 Input level = –1 dBrl 50 f = 156 Hz to 4 kHz –0.6‡ 0.6 f = 4.6875 kHz –0.7 –0.4 Receive gain variations versus input sine wave frequency VDD = 4.75 V, TA = 25°C, Input level = –13 dBrl f = 7.8125 kHz –3.35 –2.9 dBin ut sine wave frequency (see Note 6) In ut level = –13 dBrl, See Figure 9 f = 9.375 kHz –5.25 –4.8 dB (see Note 6) See Figure 9 f = 10.9375 kHz –7.25 –6.8 f = 15.625 kHz –12.8 –12.2 Receive power supply rejectionSee Note 10 30 dB † This table contains specifications in which the power levels are expressed in dBrl; dBrl stands for dB above reference level. 0 dBrl is the DAC overload point. Overload levels of the digital modulator (see parameter measurement information) are 32767 and –32767 peak values. The 0-dBrl level is related to maximum differential output voltage, which is typically 2.25 V. ‡ The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for receive gain variations versus input sine-wave frequency. NOTES: 4. This parameter is characterized but not tested. 6. Gain is relative to gain at 1 kHz. 8. Input satisfies CCITT G.714 15.4 Method 2. 9. Input satisfies CCITT G.714 14.4 Method 2. 10. The power supply rejection measurement is made with a 50-mVrms, 0-kHz to 20-kHz signal applied to VDD and with the receive channel idle.

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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature, ADCLK input frequency = 1.024 MHz, PWDA = L and PWAD = L (power-up mode) (unless otherwise noted) (continued) DAC receive characteristics (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Ilk Leakage current AOP –10 10 mAIlkg Leakage current AOM –10 10 mA Output impedance, differential, between AOP and AOM (see Note 4) 30 kW Transmit-to-receive crosstalk Transmit input = one frequency in 0.3-kHz to 3.4-kHz band at –3 dBrl, Receive channel idle, Crosstalk measured at receive analog output –70 dB NOTE 4. This parameter is characterized but not tested. timing requirements over recommended ranges of supply voltage and operating free-air temperature PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tsu1 Transmit setup time at power up (PWAD transition from H to L) ADCLK input frequency = 1.024 MHz, See Note 11 20 ms tsu2 Receive setup time at power up (PWDA transition from H to L) ADCLK input frequency = 1.024 MHz, See Note 12 20 ms tsu3 Receive setup time, DIGS or DIGL setup before ADCLK↑ See Figure 4 50 ns th Receive hold time, DIGS or DIGL hold after ADCLK↑ See Figure 4 50 ns tc Cycle time, ADCLK 1 ms tw1 Pulse duration, ADCLK high 470 ns tw2 Pulse duration, ADCLK low 470 ns tf Fall time, ADCLK 20 ns tr Rise time, ADCLK 20 ns NOTES: 11. After the setup time, the transmit channel displays normal operating characteristics. 12. After the setup time, the receive channel displays normal operating characteristics. switching characteristic over recommended ranges of supply voltage and operating free-air temperature PARAMETER TEST CONDITION MIN TYP MAX UNIT ta Transmit access time, ADOUT after ADCLK↑ (see Note 4) See Figure 3 100 ns NOTE 4. This parameter is characterized but not tested.

connected in series. The output of the decoder (see Figure 2) is shown in Table 1.

13 MSBs

3 LSBs

Figure 1. 16- to 13-Bit Modulator at 512-kHz Sampling Rate

4 MSBs

Figure 2. Sigma-Delta-2 Modulator at 512-kHz Sampling Rate Table 1. Dx Decoder

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Figure 3. Transmit Access Timing Waveforms Figure 4. Receive Setup and Hold Time Waveforms

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A (–70,8) B (–58, 20) C (–53, 24) D (–43, 32) E (–35, 40) F (–28, 48) G (–13, 65) H (–5, 69) I (–1, 69) Figure 8 Transmit Signal-to-Total-Noise-Plus-Distortion Ratio – dB Analog Input Signal Magnitude – dBrl TRANSMIT SIGNAL-TO-TOTAL-NOISE- PLUS-DISTORTION RATIO vs ANALOG INPUT SIGNAL MAGNITUDE –20 –10 (–70, –13) (–20,50) (–1,50) TA = 25°C See Note A VDD = 5.25 V NOTE A. The three points on the dashed line are minimum qualification standards, which every MSP58C20 must pass. The curve shows empirical data from a representative lot. A B C D E F G H I

Receive Gain Variations – dB Input Sine-Wave Frequency – kHz RECEIVE GAIN VARIATIONS vs INPUT SINE-WAVE FREQUENCY 12 14 16 18 –14 –12 –10 02468 1 0 RECEIVE GAIN VARIATIONS vs INPUT SINE-WAVE FREQUENCY 12 14 16 18 –14 –12 –10 Minimum Maximum VDD = 4.75 V TA = 25°C G A B C D E F H I MSP58C20 AUDIO-BAND CONVERTER SPSS015B – DECEMBER 1993 – REVISED JULY 1996 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAXIMUM AND MINIMUM CHARACTERISTICS SET OF POINTS MIN MAX Figure 9

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DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

16 PIN SHOWN

0.400 (10,15) 0.419 (10,65) 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) A 0.020 (0,51) 0.014 (0,35) 0.293 (7,45) 0.299 (7,59) 0.010 (0,25) 0.050 (1,27) 0.016 (0,40) (15,24) (15,49) PINS ** 0.010 (0,25) NOM A MAX DIM A MIN Gage Plane 0.500 (12,70) (12,95) 0.510 (10,16) (10,41) 0.400 0.410 0.600 0.610 (17,78) 0.700 (18,03) 0.710 0.004 (0,10) M0.010 (0,25) 0.050 (1,27) 0°–8° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MS-013

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) MSP58C20DW OBSOLETE SOIC DW 20 TBD Call TI Call TI MSP58C20DWR OBSOLETE SOIC DW 20 TBD Call TI Call TI MSP58C20S1DW OBSOLETE SOIC DW 20 TBD Call TI Call TI MSP58C20S2DW OBSOLETE SOIC DW 20 TBD Call TI Call TI SP58C20DW OBSOLETE SOIC DW 20 TBD Call TI Call TI SP58C20DWR OBSOLETE SOIC DW 20 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 Addendum-Page 1

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