MSP50P34N16E1A

MSP50C32 TI | Alldatasheet

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MSP50C32, MSP50C33, MSP50C34 MSP50P34, MSP50C37, MSP50P37 MIXED-SIGNAL PROCESSORS SPSS019A – MAY 1997 – REVISED OCTOBER 1998 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Dual Programmable LPC-12 Speech Synthesizers /C0068Simultaneous LPC and PCM Waveforms /C00688-Bit Microprocessor with 61 instructions /C006832 Twelve-Bit Words and 224 Bytes of RAM /C00683.3V to 6.5V CMOS Technology for Low Power Dissipation /C0068Direct Speaker Drive Capability /C0068Mask Selectable Internal or External Clock /C0068Internal Clock Generator that Requires No External Components /C0068Two Software-Selectable Clock Speeds /C006810-kHz or 8-kHz Speech Sample Rate

description

The MSP50x3x family uses a revolutionary architecture to combine an 8-bit microprocessor, two speech synthesizers, ROM, RAM, and I/O in a low-cost single-chip system. The architecture uses the same arithmetic logic unit (ALU) for the two synthesizers and the microprocessor, thus reducing chip area and cost and enabling the microprocessor to do a multiply operation in 0.8 ms. The MSP50x3x family features two independent channels of linear predictive coding (LPC), which synthesize high-quality speech at a low data rate. Pulse-code modulation (PCM) can produce music or sound effects. LPC and PCM can be added together to produce a composite result. For more information, see the MSP50x3x User’s Guide (literature number SPSU006). Table 1. MSP50x3x Family Copyright  1998, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

MSP50C32, MSP50C33, MSP50C34 MSP50P34, MSP50C37, MSP50P37 MIXED-SIGNAL PROCESSORS SPSS019A – MAY 1997 – REVISED OCTOBER 1998

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absolute maximum ratings over operating free-air temperature range† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground. 2. The total supply current includes the current out of all the I/O terminals and DAC terminals as well as the operating current of the device. recommended operating conditions (MSP50C32, MSP50C33, MSP50x34) MAX MAX UNIT VDD Supply voltage† 3.3 6.5 V VDD = 3.3 V 2.5 3.3 VIH High-level input voltage VDD = 5 V 3.8 5 V VDD = 6 V 4.5 6 VDD = 3.3 V 0 0.65 VIL Low-level input voltage VDD = 5 V 0 1 V VDD = 6 V 0 1.3 TA Operating free-air temperature Device functionality 0 70 °C Rspeaker Minimum speaker impedance Direct speaker drive using 2 pin push-pull DAC option32 W † Unless otherwise noted, all voltages are with respect to VSS . recommended operating conditions (MSP50x37) MIN MAX UNIT VDD Supply voltage† 4 6.5 V VDD = 4 V 3 4 VIH High-level input voltage VDD = 5 V 3.8 5 V VDD = 6 V 4.5 6 VDD = 4 V 0 1 VIL Low-level input voltage VDD = 5 V 0 1.2 V VDD = 6 V 0 1.5 MUX input voltage Reference voltage = 6.5 V 0 6.5 V TA Operating free-air temperature Device functionality –10 70 °C Rspeaker Minimum speaker impedance Direct speaker drive using power amp 8 W

MSP50C32, MSP50C33, MSP50C34 MSP50P34, MSP50C37, MSP50P37 MIXED-SIGNAL PROCESSORS SPSS019A – MAY 1997 – REVISED OCTOBER 1998 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP50C32, MSP50C33, MSP50x34 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VT Positive going threshold voltage (INIT) VDD = 3.5 V 2 VVT+ Positive-going threshold voltage (INIT) VDD = 6 V 3.4 V VT Negative going threshold voltage (INIT) VDD = 3.5 V 1.6 VVT– Negative-going threshold voltage (INIT) VDD = 6 V 2.3 V Vh Hysteresis (VT VT ) (INIT) VDD = 3.5 V 0.4 VVhys H ysteresis (VT+ – VT– ) (INIT) VDD = 6 V 1.1 V IIkg Input leakage current (except for OSC IN) 2 mA Istandby Standby current (INIT low, SETOFF) 10 mA VDD = 3.3 V, VOH = 2.75 V 2.1 IDD † Supply current VDD = 5 V, VOH = 4.5 V 3.1 mADD VDD = 6 V, VOH = 5.5 V 4.5 VDD = 3.3 V, VOH = 2.75 V –4 –12 VDD = 5 V, VOH = 4.5 V –5 –14 mA IOH High level output current (PA PB) VDD = 6 V, VOH = 5.5 V –6 –15 IOH High-level output current (PA, PB) VDD = 3.3 V, VOH = 2.2 V –8 –20 VDD = 5 V, VOH = 3.33 V –14 –40 mA VDD = 6 V, VOH = 4 V –20 –51 VDD = 3.3 V, VOL = 0.5 V 5 9 VDD = 5 V, VOL = 0.5 V 5 9 mA IOL Low level output current (PA PB) VDD = 6 V, VOL = 0.5 V 5 9 IOL Low-level output current (PA, PB) VDD = 3.3 V, VOL = 1.1 V 10 19 VDD = 5 V, VOL = 1.67 V 20 29 mA VDD = 6 V, VOL = 2 V 25 35 VDD = 3.3 V, VOH = 2.75 V –30 –50 VDD = 5 V, VOH = 4.5 V –35 –60 mA IOH High level output current (D/A) VDD = 6 V, VOH = 5.5 V –40 –65 IOH High-level output current (D/A) VDD = 3.3 V, VOH = 2.3 V –50 –90 VDD = 5 V, VOH = 4 V –90 –140 mA VDD = 6 V, VOH = 5 V –100 –150 VDD = 3.3 V, VOL = 0.5 V 50 80 VDD = 5 V, VOL = 0.5 V 70 90 mA IOL Low level output current (D/A) VDD = 6 V, VOL = 0.5 V 80 110 IOL Low-level output current (D/A) VDD = 3.3 V, VOL = 1 V 100 140 VDD = 5 V, VOL = 1 V 140 mA VDD = 6 V, VOL = 1 V 150 Pullup resistance Resistors selected by software and connected between terminal and VDD 10 20 50 kW f (l ) Oscillator freq enc‡ VDD = 5 V, TA = 25°C, 14 89 15 36 15 86 MHzfosc(low) O scillator frequency‡ Target frequency = 15.36 MHz 14.89 15.36 15.86 MH z f (hi h) Oscillator freq enc‡ VDD = 5 V, TA = 25°C, 18 62 19 2 19 7 MHzfosc(high) O scillator frequency‡ Target frequency = 19.2 MHz 18.62 19.2 19.7 MH z † Operating current assumes all inputs are tied to either VSS or VDD with no input currents due to programmed pullup resistors. The DAC output and other outputs are open circuited. ‡ The frequency of the internal clock has a temperature coefficient of approximately –0.2 %/°C and a VDD coefficient of approximately ±1%/V.

MSP50C32, MSP50C33, MSP50C34 MSP50P34, MSP50C37, MSP50P37 MIXED-SIGNAL PROCESSORS SPSS019A – MAY 1997 – REVISED OCTOBER 1998

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MSP50x37 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VT Positive going threshold voltage (INIT) VDD = 4.5 V 2.7 VVT+ Positive-going threshold voltage (INIT) VDD = 6 V 3.65 V VT Negative going threshold voltage (INIT) VDD = 4.5 V 2.3 VVT– Negative-going threshold voltage (INIT) VDD = 6 V 3.15 V Vh Hysteresis (VT VT ) (INIT) VDD = 4.5 V 0.4 VVhys H ysteresis (VT+ – VT– ) (INIT) VDD = 6 V 0.5 V IIkg Input leakage current (except for OSC IN) 1 mA Istandby Standby current (INIT low, SETOFF) 10 mA I † Supply current Power amplifier is on 25 mAIDD † Supply current Power amplifier is off 10 mA VDD = 4 V, VOH = 3.5 V –4 –6 VDD = 5 V, VOH = 4.5 V –5 –7.5 mA IOH High level output current (PA PB PD) VDD = 6 V, VOH = 5.5 V –6 –9.2 IOH High-level output current (PA, PB , PD) VDD = 4 V, VOH = 2.65 V –8 –13 VDD = 5 V, VOH = 3.33 V –14 –20 mA VDD = 6 V, VOH = 4 V –20 –29 VDD = 4 V, VOL = 0.5 V 20 28 VDD = 5 V, VOL = 0.5 V 26 34 mA IOL Low level output current (PA4 PA7) VDD = 6 V, VOL = 0.5 V 30 39 IOL Low-level output current (PA4 – PA7) VDD = 4 V, VOL = 1.33 V 40 54 VDD = 5 V, VOL = 1.67 V 60 74 mA VDD = 6 V, VOL = 2 V 82 103 VDD = 4 V, VOL = 0.5 V 10 17 VDD = 5 V, VOL = 0.5 V 13 20 mA IOL Low level output current (PA0 PA3 PB PD)) VDD = 6 V, VOL = 0.5 V 15 25 IOL Low-level output current (PA0 – PA3 , PB , PD)) VDD = 4 V, VOL = 1.33 V 20 32 VDD = 5 V, VOL = 1.67 V 30 52 mA VDD = 6 V, VOL = 2 V 41 71 Pullup resistance Resistors selected by software and connected between terminal and VDD 15 30 60 kW f (l ) Oscillator freq enc‡ VDD = 5 V, TA = 25°C, 14 89 15 36 15 82 MHzfosc(low) O scillator frequency‡ Target frequency = 15.36 MHz 14.89 15.36 15.82 MH z f (hi h) Oscillator freq enc‡ VDD = 5 V, TA = 25°C, 18 62 19 2 19 77 MHzfosc(high) O scillator frequency‡ Target frequency = 19.2 MHz 18.62 19.2 19.77 MH z † Operating current assumes all inputs are tied to either VSS or VDD with no input currents due to programmed pullup resistors. The DAC output and other outputs are open circuited. ‡ The frequency of the internal clock has a temperature coefficient of approximately –0.2 %/°C and a VDD coefficient of approximately ±1.4%/V.

MSP50C32, MSP50C33, MSP50C34 MSP50P34, MSP50C37, MSP50P37 MIXED-SIGNAL PROCESSORS SPSS019A – MAY 1997 – REVISED OCTOBER 1998 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP50x37 Power Amplifier Electrical Characteristics Over Recommended Operating Free-Air Temperature Range PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Differential output power VDD = 5 V,f = 1 kHz, R L = 8 W 500 mW Bandwidth 3.5 kHz MSP50x37 ADC Electrical Characteristics, VCC = 5 V, TA = 25°C PARAMETER MIN TYP MAX UNIT Linearity ± 0.5 LSB Offset ± 1.5 LSB Full scale error ± 1.5 LSB Conversion time 40 Instructions switching characteristics (MSP50C32, MSP50C33, MSP50x34) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT tr Rise time, PA, PB, D/A VDD = 3.3 V, C L = 100 pF, 10% to 90% 50 ns tf Fall time, PA, PB, D/A VDD = 3.3 V, C L = 100 pF, 10% to 90% 50 ns switching characteristics (MSP50x37) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT tr Rise time, PA, PB, PD VDD = 4 V, C L = 100 pF, 10% to 90% 22 ns tf Fall time, PA, PB, PD VDD = 4 V, C L = 100 pF, 10% to 90% 10 ns

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Figure 1. Initialization Timing Diagram Figure 2. Wakeup Terminal Setup Timing Diagram

MSP50C32, MSP50C33, MSP50C34 MSP50P34, MSP50C37, MSP50P37 MIXED-SIGNAL PROCESSORS SPSS019A – MAY 1997 – REVISED OCTOBER 1998

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N (R-PDIP-T) PLASTIC DUAL-IN-LINE PACKAGE 0.975 (24,77) 0.940 (23,88) 0.920 0.850 0.775 0.745 (19,69) (18,92) 0.775 (19,69) (18,92) 0.745A MIN DIM A MAX PINS 0.310 (7,87) 0.290 (7,37) (23.37) (21.59) Seating Plane 0.010 (0,25) NOM 14/18 PIN ONLY 4040049/C 08/95 0.070 (1,78) MAX A 0.035 (0,89) MAX 0.020 (0,51) MIN 0.015 (0,38) 0.021 (0,53) 0.200 (5,08) MAX 0.125 (3,18) MIN 0.240 (6,10) 0.260 (6,60) M0.010 (0,25)

16 PIN SHOWN

NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)

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