MSP50C30

MSP50C30 TI | Alldatasheet

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1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Interface to External ROM/EPROM (Up to 8 MBytes) /C00688-Bit Microprocessor with 61 instructions /C006832 Twelve-Bit Words and 992 Bytes of RAM /C00684K Internal ROM /C00683.3V to 6.5V CMOS Technology for Low Power Dissipation /C006828 Software-Configurable I/O Lines /C006810-kHz or 8-kHz Speech Sample Rate

description

The MSP50C30 combines an 8-bit microprocessor, two speech synthesizers, ROM, RAM, and I/O in a low-cost single-chip system. The architecture uses the same arithmetic logic unit (ALU) for the two synthesizers and the microprocessor, thus reducing chip area and cost and enabling the microprocessor to do a multiply operation in 0.8 µs. The MSP50C30 features two independent channels of linear predictive coding (LPC), which synthesize high-quality speech at a low data rate. Pulse-code modulation (PCM) can produce music or sound effects. For more information, see the MSP50C30 User’s Guide (literature number SPSU012). 100 80 56 50 NC NC NC NC OA0 PD3 PD2 PD1 PD0 DAC– DAC+ PC6 PC7 PC3 PC2 PC1 PC0 OSC OUT NC NC NC NC NC NC OA17 OA18 OA19 OA21 OA22 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 PA0 NC OA16 OA14 OA13 OA12 OA11 OA10 OA7 OA3 OA2 OA1 NC NC NC PA1 PA2 PA3 PA4 PA5 PA6 NC PA7 PB1 PB2 PB3 PB4 PB5 PB7 OSC IN PB6 PJM PACKAGE (TOP VIEW) NC OA5 OA9 OA8 NC PC4 PB0 OA20 VSS INIT NC NC NC NC NC NC NC NC NC NC OA4 OA15 VDD NC NC NC PC5 VSS VDD NC OA6 NC Copyright  1998, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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absolute maximum ratings over operating free-air temperature range† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground. 2. The total supply current includes the current out of all the I/O terminals and DAC terminals as well as the operating current of the device. recommended operating conditions (MSP50C32, MSP50C33, MSP50x34) MAX MAX UNIT VDD Supply voltage† 3.3 6.5 V VDD = 3.3 V 2.5 3.3 VIH High-level input voltage VDD = 5 V 3.8 5 V VDD = 6 V 4.5 6 VDD = 3.3 V 0 0.65 VIL Low-level input voltage VDD = 5 V 0 1 V VDD = 6 V 0 1.3 TA Operating free-air temperature Device functionality 0 70 °C Rspeaker Minimum speaker impedance Direct speaker drive using 2 pin push-pull DAC option32 Ω † Unless otherwise noted, all voltages are with respect to VSS .

3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VT Positive going threshold voltage (INIT) VDD = 3.5 V 2 VVT+ Positive-going threshold voltage (INIT) VDD = 6 V 3.4 V VT Negative going threshold voltage (INIT) VDD = 3.5 V 1.6 VVT– Negative-going threshold voltage (INIT) VDD = 6 V 2.3 V Vh Hysteresis (VT VT ) (INIT) VDD = 3.5 V 0.4 VVhys H ysteresis (VT+ – VT– ) (INIT) VDD = 6 V 1.1 V IIkg Input leakage current (except for OSC IN) 2 µA Istandby Standby current (INIT low, SETOFF) 10 µA VDD = 3.3 V, 2.1 IDD † Supply current VDD = 5 V, 3.1 mADD VDD = 6 V, 4.5 VDD = 3.3 V, VOH = 2.75 V –4 –12 VDD = 5 V, VOH = 4.5 V –5 –14 mA IOH High level output current (PA PB) VDD = 6 V, VOH = 5.5 V –6 –15 IOH High-level output current (PA, PB) VDD = 3.3 V, VOH = 2.2 V –8 –20 VDD = 5 V, VOH = 3.33 V –14 –40 mA VDD = 6 V, VOH = 4 V –20 –51 VDD = 3.3 V, VOL = 0.5 V 5 9 VDD = 5 V, VOL = 0.5 V 5 9 mA IOL Low level output current (PA PB) VDD = 6 V, VOL = 0.5 V 5 9 IOL Low-level output current (PA, PB) VDD = 3.3 V, VOL = 1.1 V 10 19 VDD = 5 V, VOL = 1.67 V 20 29 mA VDD = 6 V, VOL = 2 V 25 35 VDD = 3.3 V, VOH = 2.75 V –30 –50 VDD = 5 V, VOH = 4.5 V –35 –60 mA IOH High level output current (D/A) VDD = 6 V, VOH = 5.5 V –40 –65 IOH High-level output current (D/A) VDD = 3.3 V, VOH = 2.3 V –50 –90 VDD = 5 V, VOH = 4 V –90 –140 mA VDD = 6 V, VOH = 5 V –100 –150 VDD = 3.3 V, VOL = 0.5 V 50 80 VDD = 5 V, VOL = 0.5 V 70 90 mA IOL Low level output current (D/A) VDD = 6 V, VOL = 0.5 V 80 110 IOL Low-level output current (D/A) VDD = 3.3 V, VOL = 1 V 100 140 VDD = 5 V, VOL = 1 V 140 mA VDD = 6 V, VOL = 1 V 150 Pullup resistance Resistors selected by software and connected between terminal and VDD 10 20 50 kΩ f (l ) Oscillator freq enc‡ VDD = 5 V, TA = 25°C, 14 89 15 36 15 86 MHzfosc(low) O scillator frequency‡ Target frequency = 15.36 MHz 14.89 15.36 15.86 MH z f (hi h) Oscillator freq enc‡ VDD = 5 V, TA = 25°C, 18 62 19 2 19 7 MHzfosc(high) O scillator frequency‡ Target frequency = 19.2 MHz 18.62 19.2 19.7 MH z † Operating current assumes all inputs are tied to either VSS or VDD with no input currents due to programmed pullup resistors. The DAC output and other outputs are open circuited. ‡ The frequency of the internal clock has a temperature coefficient of approximately –0.2 %/°C and a VDD coefficient of approximately ±1%/V.

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PARAMETER TEST CONDITIONS MIN NOM MAX UNIT tr Rise time PA, PB, PC, PD, D/A VDD = 3.3 V, C L = 100 pF, 10% to 90% 50 nstr Rise time OA VDD = 3.3 V, C L = 50 pF, 10% to 90% 50 ns tf Fall time PA, PB, PC, PD, D/A VDD = 3.3 V, C L = 100 pF, 10% to 90% 50 nstf Fall time OA VDD = 3.3 V, C L = 50 pF, 10% to 90% 50 ns timing requirements MIN MAX UNIT Initialization tINIT INIT pulsed low while the MSP50x3x has power applied (see Figure 1) 1 µs Wakeup tsu(wakeup) Setup time prior to wakeup terminal negative transition (see Figure 2) 1 µs External Interrupt t (i t t) Setup time prior to B1 terminal negative transition (see Figure 3) fclock = 15.36 MHz 1 µstsu(interrupt)Setup time prior to B1 terminal negative transition (see Figure 3) fclock = 19.2 MHz 1.5 µs Writing (Slave Mode) tsu1(B1) Setup time, B1 low before B0 goes low (see Figure 4) 20 ns tsu(d) Setup time, data valid before B0 goes high (see Figure 4) 100 ns th1(B1) Hold time, B1 low after B0 goes high (see Figure 4) 20 ns th(d) Hold time, data valid after B0 goes high (see Figure 4) 30 ns tw Pulse duration, B0 low (see Figure 4) 100 ns tr Rise time, B0 (see Figure 4) 50 ns tf Fall time, B0 (see Figure 4) 50 ns Reading (Slave Mode) tsu2(B1) Setup time, B1 before B0 goes low (see Figure 5) 20 ns th2(B1) Hold time, B1 after B0 goes high (see Figure 5) 20 ns tdis Output disable time, data valid after B0 goes high (see Figure 5) 0 30 ns tw Pulse duration, B0 low (see Figure 5) 100 ns tr Rise time, B0 (see Figure 5) 50 ns tf Fall time, B0 (see Figure 5) 50 ns td Delay time for B0 low to data valid (see Figure 5) 50 ns External ROM ta(ROM) ROM access time 400 ns

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Figure 5. Read Timing Diagram (Slave Mode)

7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA PJM (R-PQFP-G100) PLASTIC QUAD FLATPACK 4040022/B 03/95 0,16 NOM 14,20 17,45 13,80 16,95 12,35 TYP 1,03 0,73 0,25 Seating Plane 0,25 MIN Gage Plane 0,38 0,22 100 22,95 23,45 20,20 19,80 2,50 2,90 3,40 MAX 18,85 TYP 0°–7° M0,130,65 0,10 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-022

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