MSP340F11X

MSP340F11X TI1 | Alldatasheet

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Technical content

/C0077/C0083/C0080/C0052/C0051/C0048/C0070/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Low Supply Voltage Range 1.8 V to 3.6 V /C0068Ultralow-Power Consumption: − Active Mode: 200 µA at 1 MHz, 2.2 V − Standby Mode: 0.8 µA − Off Mode (RAM Retention): 0.1 µA /C0068Wake-Up From Standby Mode in less than 6 µs /C006816-Bit RISC Architecture, 125 ns Instruction Cycle Time /C0068Basic Clock Module Configurations: − Various Internal Resistors − Single External Resistor − 32 kHz Crystal − High Frequency Crystal − Resonator − External Clock Source /C006816-Bit Timer_A With Three Capture/Compare Registers /C0068Serial Onboard Programming, No External Programming Voltage Needed /C0068Family Members Include: MSP430F110: 1KB + 128B Flash Memory 128B RAM MSP430F112: 4KB + 256B Flash Memory 256B RAM /C0068Available in a 20-Pin Plastic Small-Outline Wide Body (SOWB) Package and 20-Pin Plastic Thin Shrink Small-Outline Package (TSSOP) /C0068For Complete Module Descriptions, Refer to the MSP430x1xx Family User’s Guide, Literature Number SLAU049

description

The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6µs. The MSP430F11x series is an ultralow-power mixed signal microcontroller with a built in 16-bit timer and fourteen I/O pins. Typical applications include sensor systems that capture analog signals, convert them to digital values, and then process the data and display them or transmit them to a host system. Stand alone RF sensor front-end is another area of application. Copyright  1999 − 2004, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 TEST VCC P2.5/Rosc VSS XOUT/TCLK XIN RST /NMI P2.0/ACLK P2.1/INCLK P2.2/TA0 P1.7/TA2/TDO/TDI P1.6/TA1/TDI P1.5/TA0/TMS P1.4/SMCLK/TCK P1.3/TA2 P1.2/TA1 P1.1/TA0 P1.0/TACLK P2.4/TA2 P2.3/TA1 DW OR PW PACKAGE (TOP VIEW) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

/C0077/C0083/C0080/C0052/C0051/C0048/C0070/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(DW) PLASTIC 20-PIN TSSOP (PW) −40°C to 85°C MSP430F110IDW MSP430F112IDW MSP430F110IPW MSP430F112IPW functional block diagram Oscillator ACLK SMCLK CPU Incl. 16 Reg. Bus Conv MCB XIN XOUT P2 MDB, 16 Bit MAB, 16 Bit MCLK MAB,

4 Bit

Timer_A3

3 CC Reg

8 I/Os, with

6 I/Os, with

MDB, 16-Bit MAB, 16-Bit JTAG TEST Test JTAG Emulation Module 8 6 MDB, 8 Bit † A pulldown resistor of 30 kΩ is needed on F11x devices.

/C0077/C0083/C0080/C0052/C0051/C0048/C0070/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINALTERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION P1.0/TACLK 13 I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input P1.1/TA0 14 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit P1.2/TA1 15 I/O General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output P1.3/TA2 16 I/O General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output P1.4/SMCLK/TCK 17 I/O General-purpose digital I/O pin/SMCLK signal output/test clock, input terminal for device programming and test P1.5/TA0/TMS 18 I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output/test mode select, input terminal for device programming and test P1.6/TA1/TDI 19 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/test data input terminal P1.7/TA2/TDO/TDI† 20 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/test data output terminal or data input during programming P2.0/ACLK 8 I/O General-purpose digital I/O pin/ACLK output P2.1/INCLK 9 I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK P2.2/TA0 10 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0B input, compare: Out0 output/BSL receive P2.3/TA1 11 I/O General-purpose digital I/O pin/Timer_A, capture: CCI1B input, compare: Out1 output P2.4/TA2 12 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output P2.5/ROSC 3 I/O General-purpose digital I/O pin/Input for external resistor that defines the DCO nominal frequency RST /NMI 7 I Reset or nonmaskable interrupt input TEST 1 I Selects test mode for JTAG pins on Port1. Must be tied low with less than 30 kΩ. VCC 2 Supply voltage VSS 4 Ground reference XIN 6 I Input terminal of crystal oscillator XOUT/TCLK 5 I/O Output terminal of crystal oscillator or test clock input † TDO or TDI is selected via JTAG instruction.

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

instruction can operate on word and byte data. Table 1. Instruction Word Formats Table 2. Address Mode Descriptions

/C0077/C0083/C0080/C0052/C0051/C0048/C0070/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operating modes The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: /C0068Active mode AM; − All clocks are active /C0068Low-power mode 0 (LPM0); − CPU is disabled ACLK and SMCLK remain active. MCLK is disabled /C0068Low-power mode 1 (LPM1); − CPU is disabled ACLK and SMCLK remain active. MCLK is disabled DCO’s dc-generator is disabled if DCO not used in active mode /C0068Low-power mode 2 (LPM2); − CPU is disabled MCLK and SMCLK are disabled DCO’s dc-generator remains enabled ACLK remains active /C0068Low-power mode 3 (LPM3); − CPU is disabled MCLK and SMCLK are disabled DCO’s dc-generator is disabled ACLK remains active /C0068Low-power mode 4 (LPM4); − CPU is disabled ACLK is disabled MCLK and SMCLK are disabled DCO’s dc-generator is disabled Crystal oscillator is stopped

/C0077/C0083/C0080/C0052/C0051/C0048/C0070/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

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interrupt vector addresses The interrupt vectors and the power-up starting address are located in the memory with an address range of 0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power-up External reset Watchdog WDTIFG (Note1) KEYV (Note 1) Reset 0FFFEh 15, highest NMI Oscillator fault Flash memory access violation NMIIFG (Notes 1 and 5) OFIFG (Notes 1 and 5) ACCVIFG (Notes 1 and 5) (non)-maskable, (non)-maskable, (non)-maskable 0FFFCh 14 0FFFAh 13 0FFF8h 12 0FFF6h 11 Watchdog timer WDTIFG maskable 0FFF4h 10 Timer_A3 TACCR0 CCIFG (Note 2) maskable 0FFF2h 9 Timer_A3 TACCR1 and TACCR2 CCIFGs, TAIFG (Notes 1 and 2) maskable 0FFF0h 8 0FFEEh 7 0FFECh 6 0FFEAh 5 0FFE8h 4 I/O Port P2 (eight flags − see Note 3) P2IFG.0 to P2IFG.7 (Notes 1 and 2) maskable 0FFE6h 3 I/O Port P1 (eight flags) P1IFG.0 to P1IFG.7 (Notes 1 and 2) maskable 0FFE4h 2 0FFE2h 1 0FFE0h 0, lowest NOTES: 1. Multiple source flags 2. Interrupt flags are located in the module 3. There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2.0−5) are implemented on the ’11x devices. 4. Nonmaskable: neither the individual nor the general interrupt enable bit will disable an interrupt event. 5. (non)-maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot.

/C0077/C0083/C0080/C0052/C0051/C0048/C0070/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 special function registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits that are not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. interrupt enable 1 and 2 76 54 0 OFIE WDTIE 32 1 rw-0 rw-0 rw-0 Address 0h NMIIEACCVIE rw-0 WDTIE: Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in interval timer mode. OFIE: Oscillator fault enable NMIIE: Nonmaskable interrupt enable ACCVIE: Flash access violation interrupt enable 76 54 0 32 1Address 01h interrupt flag register 1 and 2 76 54 0 OFIFG WDTIFG 32 1 rw-0 rw-1 rw-(0) Address 02h NMIIFG WDTIFG: Set on Watchdog Timer overflow (in watchdog mode) or security key violation. Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode. OFIFG: Flag set on oscillator fault NMIIFG: Set via RST /NMI-pin 76 54 0 32 1Address 03h Legend rw: rw-0,1: Bit can be read and written. Bit can be read and written. It is Reset or Set by PUC. SFR bit is not present in device. rw-(0,1): Bit can be read and written. It is Reset or Set by POR.

/C0077/C0083/C0080/C0052/C0051/C0048/C0070/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

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Int. Vector

1 KB Flash

Segment0,1 128B RAM 16b Per. 8b Per. SFR FFDFh FC00h 027Fh 0200h 0100h 00FFh 0010h 000Fh 0000h MSP430F110 1 KB Boot ROM 128B Flash SegmentA 10FFh 1080h 0C00h 0FFFh FFFFh FFE0h Int. Vector 4 KB Flash Segment0−7 256B RAM 16b Per. 8b Per. SFR FFFFh FFE0h FFDFh 02FFh 0200h 0100h 00FFh 0010h 000Fh 0000h F000h Main Memory 10FFh 2 × 128B Flash SegmentA,B Information Memory 1000h 1 KB Boot ROM 0FFFh 0C00h 01FFh bootstrap loader (BSL) The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the Application report Features of the MSP430 Bootstrap Loader, Literature Number SLAA089. BSL Function DW & PW Package Pins Data Transmit 14 - P1.1 Data Receive 10 - P2.2 flash memory The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: /C0068Flash memory has n segments of main memory and two segments of information memory (A and B) of 128 bytes each. Each segment in main memory is 512 bytes in size. /C0068Segments 0 to n may be erased in one step, or each segment may be individually erased. /C0068Segments A and B can be erased individually, or as a group with segments 0−n. Segments A and B are also called information memory. /C0068New devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory prior to the first use.

/C0077/C0083/C0080/C0052/C0051/C0048/C0070/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 flash memory (continued) Segment0 w/ Interrupt Vectors 0FFFFh 0FE00h Information Memory Flash Main Memory Segment1 Segment2 Segment3 Segment4 Segment5 Segment6 Segment7 SegmentA SegmentB 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 0F800h 0F7FFh 0F600h 0F5FFh 0F400h 0F3FFh 0F200h 0F1FFh 0F000h 010FFh 01080h 0107Fh 01000h NOTE: All segments not implemented on all devices. peripherals Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, refer to the MSP430x1xx Family User’s Guide, literature number SLAU049. oscillator and system clock The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The basic clock module provides the following clock signals: /C0068Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal. /C0068Main clock (MCLK), the system clock used by the CPU. /C0068Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.

/C0077/C0083/C0080/C0052/C0051/C0048/C0070/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

There are two 8-bit I/O ports implemented—ports P1 and P2 (only six P2 I/O signals are available on external pins): /C0068All individual I/O bits are independently programmable. /C0068Any combination of input, output, and interrupt conditions is possible. /C0068Edge-selectable interrupt input capability for all the eight bits of port P1 and six bits of port P2. /C0068Read/write access to port-control registers is supported by all instructions. NOTE: Six bits of port P2, P2.0 to P2.5, are available on external pins − but all control and data bits for port P2 are implemented. watchdog timer The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Timer_A3 Signal Connections Input Pin Number Device Input SignalModule Input Name Module Block Module Output Signal Output Pin Number 13 - P1.0 TACLK TACLK ACLK ACLK Timer NASMCLK SMCLK Timer NA 9 - P2.1 INCLK INCLK 14 - P1.1 TA0 CCI0A 14 - P1.1 10 - P2.2 TA0 CCI0B CCR0 TA0 18 - P1.5 DV SS GND CCR0 TA0 10 - P2.2 DV CC VCC 15 - P1.2 TA1 CCI1A 15 - P1.2 11 - P2.3 TA1 CCI1B CCR1 TA1 19 - P1.6 DV SS GND CCR1 TA1 11 - P2.3 DV CC VCC 16 - P1.3 TA2 CCI2A 16 - P1.3 ACLK (internal) CCI2B CCR2 TA2 20 - P1.7 DV SS GND CCR2 TA2 12 - P2.4 DV CC VCC

/C0077/C0083/C0080/C0052/C0051/C0048/C0070/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 peripheral file map PERIPHERALS WITH WORD ACCESS Timer_A Reserved Reserved Reserved Reserved Capture/compare register Capture/compare register Capture/compare register Timer_A register Reserved Reserved Reserved Reserved Capture/compare control Capture/compare control Capture/compare control Timer_A control Timer_A interrupt vector TACCR2 TACCR1 TACCR0 TAR TACCTL2 TACCTL1 TACCTL0 TACTL TAIV 017Eh 017Ch 017Ah 0178h 0176h 0174h 0172h 0170h 016Eh 016Ch 016Ah 0168h 0166h 0164h 0162h 0160h 012Eh Flash Memory Flash control 3 Flash control 2 Flash control 1 FCTL3 FCTL2 FCTL1 012Ch 012Ah 0128h Watchdog Watchdog/timer control WDTCTL 0120h PERIPHERALS WITH BYTE ACCESS Basic Clock Basic clock sys. control2 Basic clock sys. control1 DCO clock freq. control BCSCTL2 BCSCTL1 DCOCTL 058h 057h 056h Port P2 Port P2 selection Port P2 interrupt enable Port P2 interrupt edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN 02Eh 02Dh 02Ch 02Bh 02Ah 029h 028h Port P1 Port P1 selection Port P1 interrupt enable Port P1 interrupt edge select Port P1 interrupt flag Port P1 direction Port P1 output Port P1 input P1SEL P1IE P1IES P1IFG P1DIR P1OUT P1IN 026h 025h 024h 023h 022h 021h 020h Special Function SFR interrupt flag2 SFR interrupt flag1 SFR interrupt enable2 SFR interrupt enable1 IFG2 IFG1 IE2 IE1 003h 002h 001h 000h

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: All voltages referenced to VSS . NOTES: 1. The LFXT1 oscillator in LF-mode requires a resistor of 5.1 MΩ from XOUT to VSS when VCC <2.5 V. The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or a crystal frequency of 4 MHz at VCC ≥ 2.2 V. The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or a crystal frequency of 8 MHz at VCC ≥ 2.8 V.

1. The LFXT1 oscillator in LF-mode requires a watch crystal. The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or crystal.

program or erase operations require a minimum VCC of 2.7 V.

5 MHz at

8 MHz at

2 MHz at

Figure 1. Frequency vs Supply Voltage

/C0077/C0083/C0080/C0052/C0051/C0048/C0070/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) supply current (into VCC ) excluding external current PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TA = −40°C +85°C, f(MCLK) = f(SMCLK) = 1 MHz, VCC = 2.2 V 200 250 µA I(AM) Active mode A f(MCLK) = f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz VCC = 3 V 300 350 µA I(AM) Active mode µATA = −40C +85 C, f(MCLK) = f(SMCLK) = f(ACLK) = 4096 Hz VCC = 3 V 3 4.3 µA I(CPUOff) Low-power mode, (LPM0) TA = −40°C +85°C, f(MCLK) = 0, f(SMCLK) = 1 MHz, VCC = 2.2 V 32 45 µAI(CPUOff) Low-power mode, (LPM0) A f(MCLK) = 0, f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz VCC = 3 V 55 70 µA I(LPM2) Low-power mode, (LPM2) TA = −40°C +85°C, f(MCLK) = f(SMCLK) = 0 MHz, VCC = 2.2 V 11 14 µAI(LPM2) Low-power mode, (LPM2) A f(MCLK) = f(SMCLK) = 0 MHz, f(ACLK) = 32,768 Hz, SCG0 = 0 VCC = 3 V 17 22 µA TA = −40°C 0.8 1.2 TA = 25°C VCC = 2.2 V 0.7 1 µA I(LPM3) Low-power mode, (LPM3) TA = 85°C VCC = 2.2 V 1.6 2.3 µA I(LPM3) Low-power mode, (LPM3) TA = −40°C 1.8 2.2 TA = 25°C VCC = 3 V 1.6 1.9 µA TA = 85°C VCC = 3 V 2.3 3.4 µA TA = −40°C f(MCLK) = 0 MHz 0.1 0.5 I(LPM4) Low-power mode, (LPM4) TA = 25°C f(MCLK) = 0 MHz f(SMCLK) = 0 MHz, f(ACLK) = 0 Hz, SCG0 = 1 VCC = 2.2 V/3 V 0.1 0.5 µAI(LPM4) Low-power mode, (LPM4) TA = 85°C f(SMCLK) = 0 MHz, f(ACLK) = 0 Hz, SCG0 = 1 VCC = 2.2 V/3 V 0.8 1.9 µA NOTE: All inputs are tied to 0 V or VCC . Outputs do not source or sink any current. current consumption of active mode versus system frequency, F version IAM = IAM[1 MHz] × fsystem [MHz] current consumption of active mode versus supply voltage, F version IAM = IAM[3 V] + 120 µA/V × (VCC −3 V)

/C0077/C0083/C0080/C0052/C0051/C0048/C0070/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) Schmitt-trigger inputs Port 1 to Port P2; P1.0 to P1.7, P2.0 to P2.5 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIT+ Positive-going input threshold voltage VCC = 2.2 V 1.1 1.3 VVIT+ Positive-going input threshold voltage VCC = 3 V 1.5 1.8 V VIT− Negative-going input threshold voltage VCC = 2.2 V 0.4 0.9 VVIT− Negative-going input threshold voltage VCC = 3 V .90 1.2 V Vhys Input voltage hysteresis, (VIT+ − VIT−) VCC = 2.2 V 0.3 1 VVhys Input voltage hysteresis, (VIT+ − VIT−) VCC = 3 V 0.5 1.4 V standard inputs − RST/NMI; TCK, TMS, TDI PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIL Low-level input voltage VCC = 2.2 V / 3 V VSS VSS +0.6 V VIH High-level input voltage VCC = 2.2 V / 3 V 0.8×VCC VCC V inputs Px.x, TAx PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Port P1, P2: P1.x to P2.x, External trigger signal 2.2 V/3 V 1.5 cycle t(int) External interrupt timing Port P1, P2: P1.x to P2.x, External trigger signal for the interrupt flag, (see Note 1) 2.2 V 62 ns t(int) External interrupt timing for the interrupt flag, (see Note 1)

3 V 50

2.2 V/3 V 1.5 cycle t(cap) Timer_A, capture timing TA0, TA1, TA2 (see Note 2) 2.2 V 62 ns t(cap) Timer_A, capture timing TA0, TA1, TA2 (see Note 2) f(TAext) Timer_A clock frequency TACLK, INCLK t(H) = t(L)

2.2 V 8

MHzf(TAext) Timer_A clock frequency externally applied to pin TACLK, INCLK t(H) = t(L) 3 V 10 MHz f(TAint) Timer_A clock frequency SMCLK or ACLK signal selected MHzf(TAint) Timer_A clock frequency SMCLK or ACLK signal selected

3 V 10

NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in MCLK cycles. 2. The external capture signal triggers the capture event every time the mimimum t(cap) cycle and time parameters are met. A capture may be triggered with capture signals even shorter than t(cap). Both the cycle and timing specifications must be met to ensure a correct capture of the 16-bit timer value and to ensure the flag is set. leakage current PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Ilkg(Px.x) High-impedance leakage current Port P1: P1.x, 0 ≤ ×≤ 7 (see Notes 1 and 2) VCC = 2.2 V/3 V, ±50 nAIlkg(Px.x) High-impedance leakage current Port P2: P2.x, 0 ≤ ×≤ 5 (see Notes 1 and 2) VCC = 2.2 V/3 V, ±50 nA NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. 2. The leakage of the digital port pins is measured individually. The port pin must be selected for input and there must be no optional pullup or pulldown resistor.

/C0077/C0083/C0080/C0052/C0051/C0048/C0070/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) outputs Port 1 to Port 2; P1.0 to P1.7, P2.0 to P2.5 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I(OHmax) = −1.5 mA VCC = 2.2 V See Note 1 VCC −0.25 VCC VOH High-level output voltageI(OHmax) = −6 mA VCC = 2.2 V See Note 2 VCC −0.6 VCC VVOH High-level output voltage Port 1 I(OHmax) = −1.5 mA VCC = 3 V See Note 1 VCC −0.25 VCC VPort 1 I(OHmax) = −6 mA VCC = 3 V See Note 2 VCC −0.6 VCC I(OHmax) = −1 mA VCC = 2.2 V See Note 3 VCC −0.25 VCC VOH High-level output voltageI(OHmax) = −3.4 mA VCC = 2.2 V See Note 3 VCC −0.6 VCC VVOH High-level output voltage Port 2 I(OHmax) = −1 mA VCC = 3 V See Note 3 VCC −0.25 VCC VPort 2 I(OHmax) = −3.4 mA VCC = 3 V See Note 3 VCC −0.6 VCC I(OLmax) = 1.5 mA VCC = 2.2 V See Note 1 VSS VSS +0.25 VOL Low-level output voltage I(OLmax) = 6 mA VCC = 2.2 V See Note 2 VSS VSS +0.6 VVOL Low-level output voltage Port 1 and Port 2 I(OLmax) = 1.5 mA VCC = 3 V See Note 1 VSS VSS +0.25 V I(OLmax) = 6 mA VCC = 3 V See Note 2 VSS VSS +0.6 NOTES: 1. The maximum total current, IOHmax and IOLmax , for all outputs combined, should not exceed ±12 mA to hold the maximum voltage drop specified. 2. The maximum total current, IOHmax and IOLmax , for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified. 3. One output loaded at a time. outputs P1.x, P2.x, TAx PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT f(P20) P2.0/ACLK, CL = 20 pF 2.2 V/3 V fSystem f(TAx) Output frequency TA0, TA1, TA2, CL = 20 pF Internal clock source, SMCLK signal applied (See Note 1)

2.2 V/3 V dc fSystem

fSMCLK = fLFXT1 = fXT1 40% 60% fSMCLK = fLFXT1 = fLF 2.2 V/3 V 35% 65% P1.4/SMCLK, CL = 20 pF fSMCLK = fLFXT1/n

2.2 V/3 V

50%− 15 ns 50% 50%+ 15 ns t(Xdc) Duty cycle of O/P frequency fSMCLK = fDCOCLK 2.2 V/3 V 50%− 15 ns 50% 50%+ 15 nsfrequency fP20 = fLFXT1 = fXT1 40% 60% P2.0/ACLK, CL = 20 pF fP20 = fLFXT1 = fLF 2.2 V/3 V 30% 70%P2.0/ACLK, CL = 20 pF fP20 = fLFXT1/n 50% t(TAdc) TA0, TA1, TA2, CL = 20 pF, Duty cycle = 50% 2.2 V/3 V 0 ±50 ns NOTE 1: The limits of the system clock MCLK have to be met. MCLK and SMCLK can have different frequencies.

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 2. Power-On Reset (POR) vs Supply Voltage Figure 3. VPOR vs Temperature

/C0077/C0083/C0080/C0052/C0051/C0048/C0070/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004 17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) wake-up from lower power modes (LPMx) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t(LPM0) VCC = 2.2 V/3 V 100 nst(LPM2) VCC = 2.2 V/3 V 100 ns f(MCLK) = 1 MHz, VCC = 2.2 V/3 V 6 t(LPM3) Delay time (see Note 1) f(MCLK) = 2 MHz, VCC = 2.2 V/3 V 6 µst(LPM3) Delay time (see Note 1) f(MCLK) = 3 MHz, VCC = 2.2 V/3 V 6 µs f(MCLK) = 1 MHz, VCC = 2.2 V/3 V 6 t(LPM4) f(MCLK) = 2 MHz, VCC = 2.2 V/3 V 6 µst(LPM4) f(MCLK) = 3 MHz, VCC = 2.2 V/3 V 6 µs NOTE 1: Parameter applicable only if DCOCLK is used for MCLK. RAM PARAMETER MIN TYP MAX UNIT V(RAMh) CPU halted (see Note 1) 1.6 V NOTE 1: This parameter defines the minimum supply voltage VCC when the data in the program memory RAM remains unchanged. No program execution should happen during this supply voltage condition.

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

NOTE 1: These parameters are not production tested.

2.2 V 3 V

Figure 4. DCO Characteristics

/C0077/C0083/C0080/C0052/C0051/C0048/C0070/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004 19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) main DCO characteristics /C0068Individual devices have a minimum and maximum operation frequency. The specified parameters for f(DCOx0) to f(DCOx7) are valid for all devices. /C0068All ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps Rsel1, ... Rsel6 overlaps Rsel7. /C0068DCO control bits DCO0, DCO1, and DCO2 have a step size as defined by parameter SDCO . /C0068Modulation control bits MOD0 to MOD4 select how often f(DCO+1) is used within the period of 32 DCOCLK cycles. The frequency f(DCO) is used for the remaining cycles. The frequency is an average equal to: /C0102/C0097/C0118/C0101/C0114/C0097/C0103/C0101/C0043 /C0051/C0050/C0032/C0102/C0040/C0068/C0067/C0079/C0041/C0032/C0102/C0040/C0068/C0067/C0079/C0041/C0049/C0041 /C0077/C0079/C0068/C0032/C0102/C0040/C0068/C0067/C0079/C0041/C0041/C0040/C0051/C0050/C0042/C0077/C0079/C0068/C0041/C0032/C0102/C0040/C0068/C0067/C0079/C0041/C0049/C0041 crystal oscillator, LFXT1 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT C XIN Input capacitance XTS=0; LF mode selected. VCC = 2.2 V / 3 V 12 pFC XIN Input capacitance XTS=1; XT1 mode selected. VCC = 2.2 V / 3 V (Note 1) 2 pF C XOUT Output capacitance XTS=0; LF mode selected. VCC = 2.2 V / 3 V 12 pFC XOUT Output capacitance XTS=1; XT1 mode selected. VCC = 2.2 V / 3 V (Note 1) 2 pF VIL Input levels at XIN VCC = 2.2 V/3 V (see Note 2) VSS 0.2×VCC V VIH Input levels at XIN VCC = 2.2 V/3 V (see Note 2) 0.8×VCC VCC V NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer. 2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.

/C0077/C0083/C0080/C0052/C0051/C0048/C0070/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) Flash Memory PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT VCC(PGM/ ERASE) Program and Erase supply voltage 2.7 3.6 V fFTG Flash Timing Generator frequency 257 476 kHz IPGM Supply current from DVCC during program 2.7 V/ 3.6 V 3 5 mA IERASE Supply current from DVCC during erase 2.7 V/ 3.6 V 3 5 mA tCPT Cumulative program time see Note 1 2.7 V/ 3.6 V 4 ms tCMErase Cumulative mass erase time see Note 2 2.7 V/ 3.6 V 200 ms Program/Erase endurance 104 105 cycles tRetention Data retention duration TJ = 25°C 100 years tWord Word or byte program time 35 tBlock, 0 Block program time for 1st byte or word 30 tBlock, 1-63 Block program time for each additional byte or word see Note 3 tFTGtBlock, End Block program end-sequence wait time see Note 3 6 tFTG tMass Erase Mass erase time 5297 tSeg Erase Segment erase time 4819 NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word/byte write and block write modes. 2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG ,max = 5297x1/476kHz). To achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met. (A worst case minimum of 19 cycles are required). 3. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG ). JTAG Interface PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT fTCK TCK input frequency see Note 1

2.2 V 0 5 MHz

fTCK TCK input frequency see Note 1 3 V 0 10 MHz R Internal Internal pull-up resistance on TMS, TCK, TDI/TCLKsee Note 2 2.2 V/ 3 V 25 60 90 kΩ NOTES: 1. f TCK may be restricted to meet the timing requirements of the module selected. 2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.

/C0077/C0083/C0080/C0052/C0051/C0048/C0070/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004 21POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

Port P1, P1.0 to P1.3, input/output with Schmitt-trigger EN D P1.0 − P1.3 Interrupt Edge Select EN Set Q P1IE.x P1IFG.x P1IRQ.x Interrupt Flag P1IES.x P1SEL.x Module X IN P1IN.x P1OUT.x Module X OUT Direction Control From Module P1DIR.x P1SEL.x Pad Logic NOTE: x = Bit/identifier, 0 to 3 for port P1 PnSel.x PnDIR.x Direction control from module † Signal from or to Timer_A

/C0077/C0083/C0080/C0052/C0051/C0048/C0070/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

input/output schematic (continued) Port P1, P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features EN D P1.4−P1.7 Interrupt Edge Select EN Set Q P1IE.x P1IFG.x P1IRQ.x Interrupt Flag P1IES.x P1SEL.x Module X IN P1IN.x P1OUT.x Module X OUT Direction Control From Module P1DIR.x P1SEL.x Pad Logic Bus Keeper TST Fuse 60 kΩ Fuse Blow Control Control By JTAG TDO Controlled By JTAG P1.x TDI P1.x TST TST TMS TST TCK TST Controlled by JTAG TST P1.x P1.x NOTE: The test pin should be protected from potential EMI and ESD voltage spikes. This may require a smaller external pulldown resistor in some applications. x = Bit identifier, 4 to 7 for port P1 During programming activity and during blowing the fuse, the pin TDO/TDI is used to apply the test input for JTAG circuitry. P1.7/TDI/TDO P1.6/TDI/TCLK P1.5/TMS P1.4/TCK Typical TEST GND NOTE: Fuse not implemented in F11x PnSel.x PnDIR.x Direction control from module † Signal from or to Timer_A

/C0077/C0083/C0080/C0052/C0051/C0048/C0070/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004 23POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 input/output schematic (continued) Port P2, P2.0 to P2.4, input/output with Schmitt-trigger EN D P2.0 − P2.4 Interrupt Edge Select EN Set Q P2IE.x P2IFG.x P2IRQ.x Interrupt Flag P2IES.x P2SEL.x Module X IN P2IN.x P2OUT.x Module X OUT Direction Control From Module P2DIR.x P2SEL.x Pad Logic NOTE: x = Bit Identifier, 0 to 4 For Port P2 0: Input 1: Output PnSel.x PnDIR.x Direction control from module PnOUT.x Module X OUT PnIN.x Module X IN PnIE.x PnIFG.x PnIES.x † Signal from or to Timer_A

/C0077/C0083/C0080/C0052/C0051/C0048/C0070/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

input/output schematic (continued) Port P2, P2.5, input/output with Schmitt-trigger and ROSC function for the Basic Clock module EN D P2.5 Interrupt Edge Select EN Set Q P2IE.5 P2IFG.5 P2IRQ.5 Interrupt Flag P2IES.5 P2SEL.5 Module X IN P2IN.5 P2OUT.5 Module X OUT Direction Control From Module P2DIR.5 P2SEL.5 Pad Logic NOTE: DCOR: Control bit from basic clock module if it is set, P2.5 Is disconnected from P2.5 pad Bus Keeper 0 1VCC Internal to Basic Clock Module DCOR DC Generator 0: Input 1: Output CAPD.5 PnSel.x PnDIR.x Direction control from module

/C0077/C0083/C0080/C0052/C0051/C0048/C0070/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004 25POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 input/output schematic (continued) Port P2, unbonded bits P2.6 and P2.7 EN D Interrupt Edge Select EN Set Q P2IE.x P2IFG.x P2IRQ.x Interrupt Flag P2IES.x P2SEL.x Module X IN P2IN.x P2OUT.x Module X OUT Direction Control From Module P2DIR.x P2SEL.x Bus Keeper 0: Input 1: Output Node Is Reset With PUC PUC NOTE: x = Bit/identifier, 6 to 7 for port P2 without external pins P2Sel.x P2DIR.x Direction control from module NOTE: A good use of the unbonded bits 6 and 7 of port P2 is to use the interrupt flags. The interrupt flags can not be influenced from any signal other than from software. They work then as a soft interrupt.

/C0077/C0083/C0080/C0052/C0051/C0048/C0070/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

The JTAG protection fuse is not implemented in the MSP430F11x devices.

www.ti.com 28-Oct-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples MSP430F110AIDW OBSOLETE SOIC DW 20 TBD Call TI Call TI -40 to 85 MSP430F110AIDWR OBSOLETE SOIC DW 20 TBD Call TI Call TI -40 to 85 MSP430F110AIPW OBSOLETE TSSOP PW 20 TBD Call TI Call TI -40 to 85 MSP430F110AIPWR OBSOLETE TSSOP PW 20 TBD Call TI Call TI -40 to 85 MSP430F110IDW OBSOLETE SOIC DW 20 TBD Call TI Call TI -40 to 85 MSP430F110IDWR OBSOLETE SOIC DW 20 TBD Call TI Call TI -40 to 85 MSP430F110 MSP430F110IPWR OBSOLETE TSSOP PW 20 TBD Call TI Call TI -40 to 85 430F110 MSP430F112AIDW OBSOLETE SOIC DW 20 TBD Call TI Call TI -40 to 85 MSP430F112AIPW OBSOLETE TSSOP PW 20 TBD Call TI Call TI -40 to 85 MSP430F112IDW OBSOLETE SOIC DW 20 TBD Call TI Call TI -40 to 85 MSP430F112IDWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 MSP430F112 MSP430F112IPW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 430F112 MSP430F112IPWR OBSOLETE TSSOP PW 20 TBD Call TI Call TI -40 to 85 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

www.ti.com 28-Oct-2014 Addendum-Page 2 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 12-Mar-2016 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430F112IDWR SOIC DW 20 2000 367.0 367.0 45.0 PACKAGE MATERIALS INFORMATION www.ti.com 12-Mar-2016 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C TYP10.63 9.97

2.65 MAX

18X 1.27 20X 0.51 0.31 11.43 TYP0.33 0.10 0 - 8 0.3 0.1 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 13.0 12.6 B 7.6 7.4 4220724/A 05/2016 SOIC - 2.65 mm max heightDW0020A SOIC NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. 1 20

0.25 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.200

www.ti.com EXAMPLE BOARD LAYOUT (9.3)

0.07 MAX

0.07 MIN

20X (2) 20X (0.6) 18X (1.27) (R ) TYP 0.05 4220724/A 05/2016 SOIC - 2.65 mm max heightDW0020A SOIC SYMM SYMM LAND PATTERN EXAMPLE SCALE:6X 10 11 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (9.3) 18X (1.27) 20X (0.6) 20X (2) 4220724/A 05/2016 SOIC - 2.65 mm max heightDW0020A SOIC NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 10 11 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X

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