MSP30X11X2

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/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Low Supply Voltage Range 1.8 V − 3.6 V /C0068Ultralow-Power Consumption: − Active Mode: 200 µA at 1 MHz, 2.2 V − Standby Mode: 0.7 µA − Off Mode (RAM Retention): 0.1 µA /C0068Five Power Saving Modes /C0068Wake-Up From Standby Mode in less than 6 µs /C006816-Bit RISC Architecture, 125 ns Instruction Cycle Time /C0068Basic Clock Module Configurations: − Various Internal Resistors − Single External Resistor − 32-kHz Crystal − High Frequency Crystal − Resonator − External Clock Source /C006816-Bit Timer_A With Three Capture/Compare Registers /C006810-Bit, 200-ksps A/D Converter With Internal Reference, Sample-and-Hold, Autoscan, and Data Transfer Controller /C0068Serial Communication Interface (USART0) With Software-Selectable Asynchronous UART or Synchronous SPI (MSP430x12x2 Only) /C0068Serial Onboard Programming, No External Programming Voltage Needed Programmable Code Protection by Security Fuse /C0068Supply Voltage Brownout Protection /C0068MSP430x11x2 Family Members Include: MSP430F1122: 4KB + 256B Flash Memory 256B RAM MSP430F1132: 8KB + 256B Flash Memory 256B RAM Available in 20-Pin Plastic SOWB, 20-Pin Plastic TSSOP and 32-Pin QFN Packages /C0068MSP430x12x2 Family Members Include: MSP430F1222: 4KB + 256B Flash Memory 256B RAM MSP430F1232: 8KB + 256B Flash Memory 256B RAM Available in 28-Pin Plastic SOWB, 28-Pin Plastic TSSOP, and 32-Pin QFN Packages /C0068For Complete Module Descriptions, See the MSP430x1xx Family User’s Guide, Literature Number SLAU049

description

The Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6µs. The MSP430x11x2 and MSP430x12x2 series are ultralow-power mixed signal microcontrollers with a built-in 16-bit timer, 10-bit A/D converter with integrated reference and data transfer controller (DTC) and fourteen or twenty-two I/O pins. In addition, the MSP430x12x2 series microcontrollers have built-in communication capability using asynchronous (UART) and synchronous (SPI) protocols. Digital signal processing with the 16-bit RISC performance enables effective system solutions such as glass breakage detection with signal analysis (including wave digital filter algorithm). Another area of application is in stand-alone RF sensors. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2002 − 2003, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SOWB (DW) PLASTIC 20-PIN TSSOP (PW) PLASTIC 28-PIN SOWB (DW) PLASTIC 28-PIN TSSOP (PW) PLASTIC 32-PIN QFN (RHB) −40°C to 85°C MSP430F1122IDW MSP430F1122IPW MSP430F1222IDW MSP430F1222IPW MSP430F1122IRHB MSP430F1132IRHB−40°C to 85°C MSP430F1122IDW MSP430F1132IDW MSP430F1122IPW MSP430F1132IPW MSP430F1222IDW MSP430F1232IDW MSP430F1222IPW MSP430F1232IPW MSP430F1132IRHB MSP430F1222IRHB MSP430F1232IRHB pin designation, MSP430x11x2 (see Note) TEST VCC P2.5/ROSC VSS XOUT XIN RST /NMI P2.0/ACLK/A0 P2.1/INCLK/A1 P2.2/TA0/A2 P1.7/TA2/TDO/TDI P1.6/TA1/TDI/TCLK P1.5/TA0/TMS P1.4/SMCLK/TCK P1.3/TA2 P1.2/TA1 P1.1/TA0 P1.0/TACLK/ADC10CLK P2.4/TA2/A4/V REF+ /VeREF+ P2.3/TA1/A3/VREF− /VeREF− DW or PW PACKAGE (TOP VIEW) RHB PACKAGE (TOP VIEW) XIN P2.5/ROSC NC NC RST /NMI VCC P2.0/ACLK/A0 TEST P2.1/INCLK/A1 P1.7/TA2/TDO/TDI XOUT P1.6/TA1/TDI/TCLK P1.1/TA0 P1.0/TACLK/ADC10CLK NC P2.4/TA2/A4/VREF+ /VeREF+ P2.3/TA1/A3/VREF− /VeREF− P1.2/TA1 Note: It is recommended that all NC pins be connected to VSS to avoid floating nodes, otherwise increased current consumption may occur. Power pad not internally connected. 10 11 12 13 272829 P1.5/TA0/TMS 3031VSS P1.3/TA2 15P2.2/TA0/A2 NC P1.4/SMCLK/TCKNC NC NC NC NC NC NC NC

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 pin designation, MSP430x12x2 (see Note) DW or PW PACKAGE (TOP VIEW) TEST VCC P2.5/ROSC VSS XOUT XIN RST /NMI P2.0/ACLK/A0 P2.1/INCLK/A1 P2.2/TA0/A2 P3.0/STE0/A5 P3.1/SIMO0 P3.2/SOMI0 P3.3/UCLK0 P1.7/TA2/TDO/TDI P1.6/TA1/TDI/TCLK P1.5/TA0/TMS P1.4/SMCLK/TCK P1.3/TA2 P1.2/TA1 P1.1/TA0 P1.0/TACLK/ADC10CLK P2.4/TA2/A4/V REF+ /VeREF+ P2.3/TA1/A3/VREF− /VeREF− P3.7/A7 P3.6/A6 P3.5/URXD0 P3.4/UTXD0 RHB PACKAGE (TOP VIEW) XIN P2.5/ROSC NC NC RST /NMI VCC P2.0/ACLK/A0 TEST P2.1/INCLK/A1 P1.7/TA2/TDO/TDI XOUT P1.6/TA1/TDI/TCLK P1.1/TA0 P1.0/TACLK/ADC10CLK NC P2.4/TA2/A4/VREF+ /VeREF+ P2.3/TA1/A3/VREF− /VeREF− P1.2/TA1 Note: It is recommended that all NC pins be connected to VSS to avoid floating nodes, otherwise increased current consumption may occur. Power pad not internally connected. 10 11 12 13 272829 P3.0/STE0/A5 P3.1/SIMO0 P3.2/SOMI0 P3.3/UCLK0 P3.4/UTXD0 P3.5/URXD0 P3.6/A6 P1.5/TA0/TMS 3031VSS P1.3/TA2 15P2.2/TA0/A2 NC P3.7/A7 P1.4/SMCLK/TCK

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram, MSP430x11x2 Oscillator ACLK SMCLK CPU Incl. 16 Reg Bus Conv MCB XIN XOUT P2 MCLK MAB,

4 Bit

Timer_A3

3 CC Reg

8 I/Os, with

6 I/Os, with

MDB, 8 BitMDB, 16-Bit MAB, 16-Bit JTAG TEST Test JTAG Emulation Module 8 6 functional block diagram, MSP430x12x2 Oscillator ACLK SMCLK CPU Incl. 16 Reg Bus Conv MCB XIN XOUT P3P2 MCLK MAB, Timer_A3

8 I/Os

MDB, 8 BitMDB, 16-Bit MAB, 16-Bit JTAG TEST Test JTAG Emulation Module 8 6 8

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions, MSP430x11x2 TERMINALTERMINAL I/O DESCRIPTIONNAME DW & PW RHB I/O DESCRIPTIONNAME DW & PW RHB I/O DESCRIPTION P1.0/TACLK/ ADC10CLK 13 21 I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input/conversion clock—10-bit ADC P1.1/TA0 14 22 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit P1.2/TA1 15 23 I/O General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output P1.3/TA2 16 24 I/O General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output P1.4/SMCLK/TCK 17 25 I/O General-purpose digital I/O pin/SMCLK signal output/test clock, input terminal for device programming and test P1.5/TA0/TMS 18 26 I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output/test mode select, input terminal for device programming and test P1.6/TA1/TDI/TCLK 19 27 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/test data input terminal or test clock input P1.7/TA2/TDO/TDI† 20 28 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/test data output terminal or data input during programming P2.0/ACLK/A0 8 6 I/O General-purpose digital I/O pin/ACLK output/analog input to 10-bit ADC input A0 P2.1/INCLK/A1 9 7 I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK/analog input to 10-bit ADC input A1 P2.2/TA0/A2 10 8 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0B input, compare: Out0 output/analog input to 10-bit ADC input A2/BSL receive P2.3/TA1/A3/VREF− / VeREF− 11 18 I/O General-purpose digital I/O pin/Timer_A, capture: CCI1B input, compare: Out1 output/analog input to 10-bit ADC input A3/negative reference voltage terminal. P2.4/TA2/A4/VREF+ / VeREF+ 12 19 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/analog input to 10-bit ADC input A4/I/O of positive reference voltage terminal P2.5/ROSC 3 32 I/O General-purpose digital I/O pin/Input for external resistor that defines the DCO nominal frequency RST /NMI 7 5 I Reset or nonmaskable interrupt input TEST 1 29 I Selects test mode for JTAG pins on P1.x VCC 2 30 Supply voltage VSS 4 1 Ground reference XIN 6 3 I Input terminal of crystal oscillator XOUT 5 2 O Output terminal of crystal oscillator NC NA 4,9-16, 17,20,31 No connect. Recommended connection to VSS to avoid floating nodes, otherwise increased current consumption may occur. † TDO or TDI is selected via JTAG instruction.

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions, MSP430x12x2 TERMINALTERMINAL I/O DESCRIPTIONNAME DW & PW RHB I/O DESCRIPTIONNAME DW & PW RHB I/O DESCRIPTION P1.0/TACLK/ ADC10CLK 21 21 I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input/conversion clock—10-bit ADC P1.1/TA0 22 22 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit P1.2/TA1 23 23 I/O General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output P1.3/TA2 24 24 I/O General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output P1.4/SMCLK/TCK 25 25 I/O General-purpose digital I/O pin/SMCLK signal output/test clock, input terminal for device programming and test P1.5/TA0/TMS 26 26 I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output/test mode select, input terminal for device programming and test P1.6/TA1/TDI/TCLK 27 27 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/test data input terminal or test clock input P1.7/TA2/TDO/TDI† 28 28 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/test data output terminal or data input during programming P2.0/ACLK/A0 8 6 I/O General-purpose digital I/O pin/ACLK output/analog input to 10-bit ADC input A0 P2.1/INCLK/A1 9 7 I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK/analog input to 10-bit ADC input A1 P2.2/TA0/A2 10 8 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0B input, compare: Out0 output/analog input to 10-bit ADC input A2/BSL receive P2.3/TA1/A3/VREF− / VeREF− 19 18 I/O General-purpose digital I/O pin/Timer_A, capture: CCI1B input, compare: Out1 output/analog input to 10-bit ADC input A3/negative reference voltage terminal. P2.4/TA2/A4/VREF+ / VeREF+ 20 19 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/analog input to 10-bit ADC input A4/I/O of positive reference voltage terminal P2.5/ROSC 3 32 I/O General-purpose digital I/O pin/Input for external resistor that defines the DCO nominal frequency P3.0/STE0/A5 11 9 I/O General-purpose digital I/O pin/slave transmit enable—USART0/SPI mode/analog input to 10-bit ADC input A5 P3.1/SIMO0 12 10 I/O General-purpose digital I/O pin/slave in/master out of USART0/SPI mode P3.2/SOMI0 13 11 I/O General-purpose digital I/O pin/slave out/master in of USART0/SPI mode P3.3/UCLK0 14 12 I/O General-purpose digital I/O pin/external clock input—USART0/UART or SPI mode, clock output—USART0/SPI mode clock input P3.4/UTXD0 15 13 I/O General-purpose digital I/O pin/transmit data out—USART0/UART mode P3.5/URXD0 16 14 I/O General-purpose digital I/O pin/receive data in—USART0/UART mode P3.6/A6 17 15 I/O General-purpose digital I/O pin/analog input to 10-bit ADC input A6 P3.7/A7 18 16 I/O General-purpose digital I/O pin/analog input to 10-bit ADC input A7 RST /NMI 7 5 I Reset or nonmaskable interrupt input TEST 1 29 I Selects test mode for JTAG pins on P1.x VCC 2 30 Supply voltage VSS 4 1 Ground reference XIN 6 3 I Input terminal of crystal oscillator XOUT 5 2 O Output terminal of crystal oscillator NC NA 4,17, 20,31 No connect. Recommended connection to VSS to avoid floating nodes, otherwise increased current consumption may occur. † TDO or TDI is selected via JTAG instruction.

instruction can operate on word and byte data. Table 1. Instruction Word Formats Table 2. Address Mode Descriptions

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: /C0068Active mode AM; − All clocks are active /C0068Low-power mode 0 (LPM0); − CPU is disabled ACLK and SMCLK remain active. MCLK is disabled /C0068Low-power mode 1 (LPM1); − CPU is disabled ACLK and SMCLK remain active. MCLK is disabled DCO’s dc-generator is disabled if DCO not used in active mode /C0068Low-power mode 2 (LPM2); − CPU is disabled MCLK and SMCLK are disabled DCO’s dc-generator remains enabled ACLK remains active /C0068Low-power mode 3 (LPM3); − CPU is disabled MCLK and SMCLK are disabled DCO’s dc-generator is disabled ACLK remains active /C0068Low-power mode 4 (LPM4); − CPU is disabled ACLK is disabled MCLK and SMCLK are disabled DCO’s dc-generator is disabled Crystal oscillator is stopped

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the memory with an address range of 0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power-up, external reset, watchdogWDTIFG (see Note1) KEYV (see Note 1) Reset 0FFFEh 15, highest NMI, oscillator fault, flash memory access violation NMIIFG (see Notes 1 and 4) OFIFG (see Notes 1 and 4) ACCVIFG (see Notes 1 and 4) (Non)-maskable, (Non)-maskable, (Non)-maskable 0FFFCh 14 0FFFAh 13 0FFF8h 12 0FFF6h 11 Watchdog timer WDTIFG Maskable 0FFF4h 10 Timer_A TACCR0 CCIFG (see Note 2) Maskable 0FFF2h 9 Timer_A TACCR1 and TACCR2 CCIFGs, TAIFG (see Notes 1 and 2) Maskable 0FFF0h 8 USART0 receive (see Note 5) URXIFG0 Maskable 0FFEEh 7 USART0 transmit (see Note 5) UTXIFG0 Maskable 0FFECh 6 ADC10 ADC10IFG Maskable 0FFEAh 5 0FFE8h 4 I/O Port P2 (eight flags − see Note 3)P2IFG.0 to P2IFG.7 (see Notes 1 and 2) Maskable 0FFE6h 3 I/O Port P1 (eight flags) P1IFG.0 to P1IFG.7 (see Notes 1 and 2) Maskable 0FFE4h 2 0FFE2h 1 0FFE0h 0, lowest NOTES: 1. Multiple source flags 2. Interrupt flags are located in the module 3. There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2.0−5) are implemented on the ’11x2 and ’12x2 devices. 4. (Non)-maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot. 5. USART0 is implemented in MSP430x12x2 only.

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

special function registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits that are not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. interrupt enable 1 and 2 76 54 0 OFIE WDTIE 32 1 rw-0 rw-0 rw-0 Address 0h NMIIEACCVIE rw-0 WDTIE: Watchdog Ti mer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in interval timer mode. OFIE: Oscillator fault enable NMIIE: (Non)maskable interrupt enable ACCVIE: Flash access violation interrupt enable 76 54 0 32 1Address 01h UTXIE0 URXIE0 rw-0rw-0 URXIE0: USART0, UART, and SPI receive-interrupt enable (MSP430x12x2 devices only) UTXIE0: USART0, UART, and SPI transmit-interrupt enable (MSP430x12x2 devices only) interrupt flag register 1 and 2 76 54 0 OFIFG WDTIFG 32 1 rw-0 rw-1 rw-0 Address 02h NMIIFG WDTIFG: Set on Watchdog Timer overflow (in watchdog mode) or security key violation. Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode. OFIFG: Flag set on oscillator fault NMIIFG: Set via RST /NMI-pin 76 54 0 32 1Address 03h UTXIFG0 URXIFG0 rw-0rw-1 URXIFG0: USART0, UART, and SPI receive flag (MSP430x12x2 devices only) UTXIFG0: USART0, UART, and SPI transmit flag (MSP430x12x2 devices only)

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 module enable registers 1 and 2 76 54 0 32 1Address 04h 76 54 0 32 1Address 05h UTXE0 URXE0 USPIE0 rw-0 rw-0 URXE0: USART0, UART mode receive enable (MSP430x12x2 devices only) UTXE0: USART0, UART mode transmit enable (MSP430x12x2 devices only) USPIE0: USART0, SPI mode transmit and receive enable (MSP430x12x2 devices only) Legend rw: rw-0: Bit can be read and written. Bit can be read and written. It is reset by PUC SFR bit is not present in device. memory organization Int. Vector 8 KB Flash Segment0−15 256B RAM 16b Per. 8b Per. SFR FFFFh FFE0h FFDFh 02FFh 0200h 01FFh 0100h 00FFh 0010h 000Fh 0000h MSP430F1132 MSP430F1232 E000h Main Memory 10FFh 2 × 128B Flash SegmentA,B Information Memory 1000h 1 KB Boot ROM0C00h Int. Vector

4 KB Flash

Segment0−7 256B RAM 16b Per. 8b Per. SFR FFDFh F000h 02FFh 0200h 0100h 00FFh 0010h 000Fh 0000h MSP430F1122 MSP430F1222 1 KB Boot ROM 2 × 128B Flash SegmentA,B 10FFh 1000h 01FFh 0C00h 0FFFh FFFFh FFE0h 0FFFh

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

bootstrap loader (BSL) The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the Application report Features of the MSP430 Bootstrap Loader, Literature Number SLAA089. BSL Function MSP430x11x2 DW & PW Package (20 Pins) MSP430x12x2 DW & PW Package (28 Pins) MSP430x11x2/12x2 (32 Pins) Data Transmit 14 - P1.1 22 - P1.1 22 - P1.1 Data Receive 10 - P2.2 10 - P2.2 8 - P2.2 flash memory The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: /C0068Flash memory has n segments of main memory and two segments of information memory (A and B) of 128 bytes each. Each segment in main memory is 512 bytes in size. /C0068Segments 0 to n may be erased in one step, or each segment may be individually erased. /C0068Segments A and B can be erased individually, or as a group with segments 0−n. Segments A and B are also called information memory. /C0068New devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory prior to the first use. Segment0 w/ Interrupt Vectors 0FFFFh 0FE00h Information Memory Flash Main Memory Segment1 Segment2 Segment3 Segment4 Segment14 Segment15 SegmentA SegmentB 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 0F800h 0F7FFh 0F600h 0E3FFh 0E200h 0E1FFh 0E000h 010FFh 01080h 0107Fh 01000h NOTE: All segments not implemented on all devices.

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 peripherals Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, see the MSP430x1xx Family User’s Guide, literature number SLAU049. oscillator and system clock The clock system in the MSP430x11x2 and MSP430x12x2 devices is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The basic clock module provides the following clock signals: /C0068Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal. /C0068Main clock (MCLK), the system clock used by the CPU. /C0068Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. digital I/O There are 3 8-bit I/O ports implemented—ports P1, P2, and P3 (only six port P2 I/O signals are available on external pins; port P3 is implemented only on ’x12x2 devices): /C0068All individual I/O bits are independently programmable. /C0068Any combination of input, output, and interrupt conditions is possible. /C0068Edge-selectable interrupt input capability for all the eight bits of ports P1 and six bits of port P2. /C0068Read/write access to port-control registers is supported by all instructions. NOTE: Six bits of port P2, P2.0 to P2.5, are available on external pins, but all control and data bits for port P2 are implemented. Port P3 has no interrupt capability. Port P3 is implemented in MSP430x12x2 only. brownout The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. watchdog timer The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. USART0 (MSP430x12x2 Only) The MSP430x12x2 devices have one hardware universal synchronous/asynchronous receive transmit (USART0) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels. ADC10 The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion result handling allowing ADC samples to be converted and stored without any CPU intervention.

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Timer_A3 Signal Connections Input Pin Number Output Pin Number DW and PW RHB Device Input Signal Module Input Name Module Block Module Output Signal DW and PW RHB ’11x2 20-Pin ’12x2 28-Pin ’11x2/12x2 32-Pin Device Input Signal Module Input Name Module Block Module Output Signal ’11x2 20-Pin ’12x2 28-Pin ’11x2/12x2 32-Pin 13 - P1.0 21 - P1.0 21 - P1.0 TACLK TACLK ACLK ACLK Timer NASMCLK SMCLK Timer NA 9 - P2.1 9 - P2.1 7 - P2.1 INCLK INCLK 10 - P2.2 10 - P2.2 8 - P2.2 TA0 CCI0B CCR0 TA0 18 - P1.5 26 - P1.5 26 - P1.5 DV SS GND CCR0 TA0 10 - P2.2 10 - P2.2 8 - P2.2 DV CC VCC ADC10 Internal 11 - P2.3 19 - P2.3 18 - P2.3 TA1 CCI1B CCR1 TA1 19 - P1.6 27 - P1.6 27 - P1.6 DV SS GND CCR1 TA1 11 - P2.3 19 - P2.3 18 - P2.3 DV CC VCC ADC10 Internal ACLK (internal) CCI2B CCR2 TA2 20 - P1.7 28 - P1.7 28 - P1.7 DV SS GND CCR2 TA2 12 - P2.4 20 - P2.4 19 - P2.4 DV CC VCC ADC10 Internal

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 peripheral file map PERIPHERALS WITH WORD ACCESS ADC10 ADC data transfer start address ADC memory ADC control register 1 ADC control register 0 ADC10SA ADC10MEM ADC10CTL1 ADC10CTL0 1BCh 1B4h 1B2h 1B0hADC control register 0 ADC analog enable ADC data transfer control register 1 ADC data transfer control register 0 ADC10CTL0 ADC10AE ADC10DTC1 ADC10DTC0 1B0h 04Ah 049h 048h Timer_A Reserved Reserved Reserved Reserved Capture/compare register Capture/compare register Capture/compare register Timer_A register Reserved Reserved Reserved Reserved Capture/compare control Capture/compare control Capture/compare control Timer_A control Timer_A interrupt vector TACCR2 TACCR1 TACCR0 TAR TACCTL2 TACCTL1 TACCTL0 TACTL TAIV 017Eh 017Ch 017Ah 0178h 0176h 0174h 0172h 0170h 016Eh 016Ch 016Ah 0168h 0166h 0164h 0162h 0160h 012Eh Flash Memory Flash control 3 Flash control 2 Flash control 1 FCTL3 FCTL2 FCTL1 012Ch 012Ah 0128h Watchdog Watchdog/timer control WDTCTL 0120h PERIPHERALS WITH BYTE ACCESS USART0 (in MSP430x12x2 only) Transmit buffer Receive buffer Baud rate Baud rate Modulation control Receive control Transmit control USART control U0TXBUF U0RXBUF U0BR1 U0BR0 U0MCTL U0RCTL U0TCTL U0CTL 077h 076h 075h 074h 073h 072h 071h 070h Basic Clock Basic clock sys. control2 Basic clock sys. control1 DCO clock freq. control BCSCTL2 BCSCTL1 DCOCTL 058h 057h 056h Port P2 Port P2 selection Port P2 interrupt enable Port P2 interrupt edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN 02Eh 02Dh 02Ch 02Bh 02Ah 029h 028h Port P1 Port P1 selection Port P1 interrupt enable Port P1 interrupt edge select Port P1 interrupt flag Port P1 direction Port P1 output Port P1 input P1SEL P1IE P1IES P1IFG P1DIR P1OUT P1IN 026h 025h 024h 023h 022h 021h 020h

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

peripheral file map (continued) PERIPHERALS WITH BYTE ACCESS (CONTINUED) Port P3 (in MSP430x12x2 only) Port P3 selection Port P3 direction Port P3 output Port P3 input P3SEL P3DIR P3OUT P3IN 01Bh 01Ah 019h 018h Special Function Module enable2 Module enable1 SFR interrupt flag2 SFR interrupt flag1 SFR interrupt enable2 SFR interrupt enable1 ME2 ME1 IFG2 IFG1 IE2 IE1 005h 004h 003h 002h 001h 000h absolute maximum ratings† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: All voltages referenced to VSS . The JTAG fuse-blow voltage, VFB , is allowed to exceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the JTAG fuse. recommended operating conditions MIN NOM MAX UNITS Supply voltage during program execution, VCC (see Note 1) MSP430F11x2 1.8 3.6 VSupply voltage during program execution, VCC (see Note 1) MSP430F11x2 MSP430F12x2 1.8 3.6 V Supply voltage during program/erase flash memory, VCC MSP430F11x2 MSP430F12x2 2.7 3.6 V Supply voltage, VSS 0 V Operating free-air temperature range, TA MSP430F11x2 MSP430F12x2 −40 85 °C LFXT1 crystal frequency, f(LFXT1) LF mode selected, XTS=0 Watch crystal 32768 Hz LFXT1 crystal frequency, f(LFXT1) (see Note 2) XT1 selected mode, XTS=1 Ceramic resonator 450 8000 kHz(see Note 2) XT1 selected mode, XTS=1Crystal 1000 8000 kHz Processor frequency f(system) (MCLK signal) VCC = 1.8 V, MSP430F11x2 MSP430F12x2 dc 4.15 MHzProcessor frequency f(system) (MCLK signal) VCC = 3.6 V, MSP430F11x2 MSP430F12x2 dc 8 MHz NOTES: 1. The LFXT1 oscillator in LF-mode requires a resistor of 5.1 MΩ from XOUT to VSS when VCC <2.5 V. The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or a crystal frequency of 4 MHz at VCC ≥ 2.2 V. The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or a crystal frequency of 8 MHz at VCC ≥ 2.8 V. 2. The LFXT1 oscillator in LF-mode requires a watch crystal. The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or a crystal.

4.15 MHz

program or erase operations require a minimum VCC of 2.7 V. Figure 1. Frequency vs Supply Voltage NOTES: 1. All inputs are tied to 0 V or VCC . Outputs do not source or sink any current.

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) current consumption of active mode versus system frequency IAM = IAM[1 MHz] × fsystem [MHz] current consumption of active mode versus supply voltage IAM = IAM[3 V] + 120 µA/V × (VCC −3 V) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIT+ Positive-going input threshold voltage VCC = 2.2 V 1.1 1.5 VVIT+ Positive-going input threshold voltage VCC = 3 V 1.5 1.9 V VIT− Negative-going input threshold voltage VCC = 2.2 V 0.4 0.9 VVIT− Negative-going input threshold voltage VCC = 3 V 0.9 1.3 V Vhys Input voltage hysteresis, (VIT+ − VIT−) VCC = 2.2 V 0.3 1.1 VVhys Input voltage hysteresis, (VIT+ − VIT−) VCC = 3 V 0.5 1 V standard inputs − RST/NMI; TEST PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIL Low-level input voltage VCC = 2.2 V / 3 V VSS VSS +0.6 V VIH High-level input voltage VCC = 2.2 V / 3 V 0.8×VCC VCC V inputs Px.x, TAx PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Port P1, P2: P1.x to P2.x, External trigger signal 2.2 V/3 V 1.5 cycle t(int) External interrupt timing Port P1, P2: P1.x to P2.x, External trigger signal for the interrupt flag, (see Note 1) 2.2 V 62 ns t(int) External interrupt timing for the interrupt flag, (see Note 1)

3 V 50

t(cap) Timer_A, capture timing TA0, TA1, TA2

2.2 V 62

nst(cap) Timer_A, capture timing TA0, TA1, TA2 f(TAext) Timer_A clock frequency TACLK, INCLK t(H) = t(L)

2.2 V 8

MHzf(TAext) Timer_A clock frequency externally applied to pin TACLK, INCLK t(H) = t(L) 3 V 10 MHz f(TAint) Timer_A clock frequency SMCLK or ACLK signal selected MHzf(TAint) Timer_A clock frequency SMCLK or ACLK signal selected

3 V 10

NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in MCLK cycles. leakage current PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Ilkg(Px.x) High-impedance leakage current Port P1: P1.x, 0 ≤ ×≤ 7 (see Notes 1 and 2) 2.2 V/3 V ±50 nAIlkg(Px.x) High-impedance leakage current Port P2: P2.x, 0 ≤ ×≤ 5 (see Notes 1 and 2) 2.2 V/3 V ±50 nA NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. 2. The leakage of the digital port pins is measured individually. The port pin must be selected for input and there must be no optional pullup or pulldown resistor.

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003 19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I(OHmax) = −1.5 mA VCC = 2.2 V See Note 1 VCC −0.25 VCC VOH High-level output voltage I(OHmax) = −6 mA VCC = 2.2 V See Note 2 VCC −0.6 VCC VVOH High-level output voltageI(OHmax) = −1.5 mA VCC = 3 V See Note 1 VCC −0.25 VCC V I(OHmax) = −6 mA VCC = 3 V See Note 2 VCC −0.6 VCC I(OLmax) = 1.5 mA VCC = 2.2 V See Note 1 VSS VSS +0.25 VOL Low-level output voltage I(OLmax) = 6 mA VCC = 2.2 V See Note 2 VSS VSS +0.6 VVOL Low-level output voltage I(OLmax) = 1.5 mA VCC = 3 V See Note 1 VSS VSS +0.25 V I(OLmax) = 6 mA VCC = 3 V See Note 2 VSS VSS +0.6 NOTES: 1. The maximum total current, IOHmax and IOLmax , for all outputs combined, should not exceed ±12 mA to hold the maximum voltage drop specified. 2. The maximum total current, IOHmax and IOLmax , for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified. outputs P1.x, P2.x, P3.x, TAx PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT f(P20) P2.0/ACLK, CL = 20 pF 2.2 V/3 V fSystem f(TAx) Output frequency TA0, TA1, TA2, CL = 20 pF, Internal clock source, SMCLK signal applied (see Note 1)2.2 V/3 V dc fSystem MHz fSMCLK = fLFXT1 = fXT1 40% 60% P1.4/SMCLK, fSMCLK = fLFXT1 = fLF 2.2 V/3 V 35% 65% P1.4/SMCLK, C L = 20 pF fSMCLK = fLFXT1/n

2.2 V/3 V

50%− 15 ns 50% 50%+ 15 ns t(Xdc) Duty cycle of O/P frequency fSMCLK = fDCOCLK 2.2 V/3 V 50%− 15 ns 50% 50%+ 15 nsfrequency P2.0/ACLK, fP20 = fLFXT1 = fXT1 40% 60% P2.0/ACLK, C L = 20 pF fP20 = fLFXT1 = fLF 2.2 V/3 V 30% 70%C L = 20 pF fP20 = fLFXT1/n 50% t(TAdc) TA0, TA1, TA2, C L = 20 pF, Duty cycle = 50%2.2 V/3 V 0 ±50 ns NOTES: 1. The limits of the system clock MCLK has to be met. MCLK and SMCLK can have different frequencies.

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) outputs − Ports P1, P2, and P3 (see Note) Figure 2 VOL − Low-Level Output Voltage − V VCC = 2.2 V P1.0 TA = 25°C TA = 85°C OLI − Typical Low-Level Output Current − mA TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE Figure 3 VOL − Low-Level Output Voltage − V VCC = 3 V P1.0 TA = 25°C TA = 85°C TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE OLI − Typical Low-Level Output Current − mA Figure 4 VOH − High-Level Output Voltage − V −28 −24 −20 −16 −12 VCC = 2.2 V P1.0 TA = 25°C TA = 85°C OHI − Typical High-Level Output Current − mA TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE Figure 5 VOH − High-Level Output Voltage − V −60 −50 −40 −30 −20 −10 VCC = 3 V P1.0 TA = 25°C TA = 85°C TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE OHI − Typical High-Level Output Current − mA NOTE: Only one output is loaded at a time.

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003 21POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) USART (see Note 1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t( ) USART: deglitch time VCC = 2.2 V 200 430 800 nst(τ) USART: deglitch time VCC = 3 V 150 280 500 ns NOTES: 1. The signal applied to the USART receive signal/terminal (URXD) should meet the timing requirements of t(τ) to ensure that the URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(τ). The operating conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the URXD line. RAM PARAMETER MIN NOM MAX UNIT V(RAMh) CPU halted (see Note 1) 1.6 V NOTES: 1. This parameter defines the minimum supply voltage VCC when the data in the program memory RAM remains unchanged. No program execution should happen during this supply voltage condition. POR brownout, reset (see Notes 1 and 2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td(BOR) 2000 µs VCC(start) dVCC /dt ≤ 3 V/s 0.7 × V(B_IT−) V V(B_IT−) Brownout dVCC /dt ≤ 3 V/s 1.71 V Vhys(B_IT−) Brownout dVCC /dt ≤ 3 V/s 70 130 180 mV t(reset) Pulse length needed at RST/NMI pin to accepted reset internally, VCC = 2.2 V/3 V 2 µs NOTES: 1. The current consumption of the brown-out module is already included in the ICC current consumption data. 2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT−) + Vhys(B_IT−). The default DCO settings must not be changed until VCC ≥ VCC(min). See the MSP430x1xx Family User’s Guide for more information on the brownout circuit.

22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 6. POR/Brownout Reset (BOR) vs Supply Voltage Figure 7. VCC(min) Level With a Square Voltage Drop to Generate a POR/Brownout Signal Figure 8. VCC(min) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003 23POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) crystal oscillator,LFXT1 PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT C XIN Pin load XTS=0; LF mode selected 2.2 V / 3 V 12 pFC XIN Pin load capacitance XTS=1; XT1 mode selected (see Note 1) 2.2 V / 3 V 2 pF C XOUT Pin load capacitance XTS=0; LF mode selected 2.2 V / 3 V 12 pFC XOUT Pin load capacitance XTS=1; XT1 mode selected (see Note 1) 2.2 V / 3 V 2 pF VIL Input levels at XINsee Note 2 2.2 V / 3 V VSS 0.2 × VCC V VIH Input levels at XINsee Note 2 2.2 V / 3 V 0.8 × VCC VCC V NOTES: 1. Requires external capacitors at both terminals. Values are specified by crystal manufacturers. 2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator. DCO PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT f(DCO03) R sel = 0, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C 2.2 V 0.08 0.12 0.15 MHzf(DCO03) R sel = 0, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C 3 V 0.08 0.13 0.16 MHz f(DCO13) R sel = 1, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C 2.2 V 0.14 0.19 0.23 MHzf(DCO13) R sel = 1, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C 3 V 0.14 0.18 0.22 MHz f(DCO23) R sel = 2, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C 2.2 V 0.22 0.3 0.36 MHzf(DCO23) R sel = 2, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C 3 V 0.22 0.28 0.34 MHz f(DCO33) R sel = 3, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C 2.2 V 0.37 0.49 0.59 MHzf(DCO33) R sel = 3, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C 3 V 0.37 0.47 0.56 MHz f(DCO43) R sel = 4, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C 2.2 V 0.61 0.77 0.93 MHzf(DCO43) R sel = 4, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C 3 V 0.61 0.75 0.9 MHz f(DCO53) R sel = 5, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C 2.2 V 1 1.2 1.5 MHzf(DCO53) R sel = 5, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C 3 V 1 1.3 1.5 MHz f(DCO63) R sel = 6, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C 2.2 V 1.6 1.9 2.2 MHzf(DCO63) R sel = 6, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C 3 V 1.69 2 2.29 MHz f(DCO73) R sel = 7, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C 2.2 V 2.4 2.9 3.4 MHzf(DCO73) R sel = 7, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C 3 V 2.7 3.2 3.65 MHz f(DCO77) R sel = 7, DCO = 7, MOD = 0, DCOR = 0, TA = 25°C 2.2 V 4 4.5 4.9 MHzf(DCO77) R sel = 7, DCO = 7, MOD = 0, DCOR = 0, TA = 25°C 3 V 4.4 4.9 5.4 MHz f(DCO47) R sel = 4, DCO = 7, MOD = 0, DCOR = 0, TA = 25°C 2.2 V/3 V fDCO40 fDCO40 fDCO40 MHzf(DCO47) R sel = 4, DCO = 7, MOD = 0, DCOR = 0, TA = 25°C 2.2 V/3 V fDCO40 x1.7 fDCO40 x2.1 fDCO40 x2.5 MHz S(Rsel) SR = fRsel+1/fRsel 2.2 V/3 V 1.35 1.65 2 ratio S(DCO) SDCO = fDCO+1 /fDCO 2.2 V/3 V 1.07 1.12 1.16 ratio D t Temperature drift, Rsel = 4, DCO = 3, MOD = 0 (see Note 1) %/°CD t Temperature drift, Rsel = 4, DCO = 3, MOD = 0 (see Note 1) %/°C D V Drift with VCC variation, Rsel = 4, DCO = 3, MOD = 0 (see Note 1) 2.2 V/3 V ±5 %/V NOTES: 1. These parameters are not production tested.

24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2.2 V 3 V

Figure 9. DCO Characteristics fDCOx0 to fDCOx7 are valid for all devices. /C0068The DCO control bits DCO0, DCO1 and DCO2 have a step size as defined in parameter SDCO . cycles. fDCO is used for the remaining cycles. The frequency is an average = fDCO × (2MOD/32 ). /C0068All ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps with Rsel1, ... Rsel6 overlaps with Rsel7. NOTES: 1. Parameter applicable only if DCOCLK is used for MCLK.

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003 25POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 10-bit ADC, power supply and input range conditions (see Note 1) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT VCC Analog supply voltage VSS = 0 V 2.2 3.6 V V(P6.x/Ax) Analog input voltage range (see Note 2) All Ax terminals. Analog inputs selected in ADC10AE register and PxSel.x=1 VSS ≤ VPx.x/Ax ≤ VCC

0 VCC V

fADC10CLK = 5.0 MHz ADC10ON = 1, REFON = 0 2.2 V 0.52 1.05 mAIADC10 into VCC terminal (see Note 3) ADC10ON = 1, REFON = 0 ADC10SHT0=1, ADC10SHT1=0, ADC10DIV=0 3 V 0.6 1.2 mA IREF+ Reference operating supply current, reference buffer disabled (see Note 4) fADC10CLK = 5.0 MHz ADC10ON = 0, REFON = 1, REF2_5V = x; REFOUT = 0 2.2V/3 V 0.25 0.4 mA IREFB Reference buffer operating supply current fADC10CLK = 5.0 MHz ADC10ON = 0, ADC10SR = 0 1.1 1.4 mAIREFB operating supply current (see Note 4) ADC10ON = 0, REFON = 1, REF2_5V = 0 REFOUT = 1 ADC10SR = 1 0.46 0.55 mA C I † Input capacitance Only one terminal can be selected at one time, Px.x/Ax 2.2 V 27 pF R I† Input MUX ON resistance0V ≤ VAx ≤ VCC 3 V 2000 Ω † Not production tested, limits verified by design NOTES: 1. The leakage current is defined in the leakage current table with Px.x/Ax parameter. 2. The analog input voltage range must be within the selected reference voltage range VR+ to VR− for valid conversion results. 3. The internal reference supply current is not included in current consumption parameter IADC10 . 4. The internal reference current is supplied via terminal VCC . Consumption is independent of the ADC10ON control bit, unless a conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion. 10-bit ADC, external reference (see Note 1) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT VeREF+ Positive external reference voltage inputVeREF+ > VREF− /VeREF− (see Note 2) 1.4 VCC V VREF− /VeREF− Negative external reference voltage inputVeREF+ > VREF− /VeREF− (see Note 3) 0 1.2 V (VeREF+ − VREF−/VeREF− ) Differential external reference voltage inputVeREF+ > VREF− /VeREF− (see Note 4) 1.4 VCC V IVeREF+ Static input current 0V ≤VeREF+ ≤ VCC 2.2 V/3 V ±1 µA IVREF−/VeREF− Static input current 0V ≤ VeREF− ≤ VCC 2.2 V/3 V ±1 µA NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy. 2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements. 3. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements. 4. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements.

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003

26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 10-bit ADC, built-in reference PARAMETER TEST CONDITIONS MIN NOM MAX UNIT VREF+ Positive built-in reference REF2_5V = 1 for 2.5 V IVREF+ ≤ IVREF+ max 3 V 2.35 2.5 2.65 VVREF+ Positive built-in reference voltage output REF2_5V = 0 for 1.5 V IVREF+ ≤ IVREF+ max 2.2 V/3 V 1.41 1.5 1.59 V VCC minimum voltage, REF2_5V = 0, IVREF+ ≤ 1mA 2.2 VCC(min) VCC minimum voltage, Positive built-in reference active REF2_5V = 1, IVREF+ ≤ 0.5mA VREF+ + 0.15 VVCC(min) Positive built-in reference active REF2_5V = 1, IVREF+ ≤ 1mA VREF+ + 0.15 V IVREF+ Load current out of VREF+ 2.2 V ±0.5 mAIVREF+ Load current out of VREF+ terminal 3 V ±1 mA IVREF+ = 500 µA +/− 100 µA Analog input voltage ~0.75 V;

2.2 V ±2

IL(VREF)+ † Load-current regulation VREF+ Analog input voltage ~0.75 V; REF2_5V = 0 3 V ±2 LSB IL(VREF)+ † Load-current regulation VREF+ terminal IVREF+ = 500 µA ± 100 µA Analog input voltage ~1.25 V; REF2_5V = 1

3 V ±2 LSB

tDL(VREF) +‡ Load current regulationIVREF+ =100 µA → 900 µA, VCC =3 V, Ax ~0.5 x VREF+ ADC10SR = 0 400 nstDL(VREF) +‡ Load current regulation VREF+ terminal VREF+ VCC =3 V, Ax ~0.5 x VREF+ Error of conversion result ≤ 1 LSB ADC10SR = 1 2000 ns C VREF+ Capacitance at pin VREF+ (see Note 1) REFON =1, IVREF+ ≤± 1 mA 2.2 V/3 V 100 pF TREF+ † Temperature coefficient of built-in reference IVREF+ is a constant in the range of 0 mA ≤ IVREF+ ≤ 1 mA 2.2 V/3 V ±100 ppm/°C t † Settle time of internal reference voltage and IVREF+ = 0.5 mA,VREF+ = 1.5 V, VCC = 3.6 V, REFON = 0 → 1 30 stREFON † reference voltage and VREF+ (see Note 2) IVREF+ = 0.5 mA, VREF+ = 1.5 V, ADC10SR = 0 0.8 µsVREF+ (see Note 2) IVREF+ = 0.5 mA, VREF+ = 1.5 V, VCC = 2.2 V, REFON = 1 ADC10SR = 1 2.5 † Not production tested, limits characterized ‡ Not production tested, limits verified by design NOTES: 1. The capacitance applied to the internal buffer operational amplifier, if switched to terminal P2.4/TA2/A4/VREF+ /VeREF+ (REFOUT=1), must be limited; the reference buffer may become unstable otherwise. NOTES: 2. The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003 27POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 10-bit ADC, timing parameters PARAMETER TEST CONDITIONS MIN NOM MAX UNIT fADC10CLK Error of conversion result ≤± 1 ADC10SR = 0 0.450 6.3 MHzfADC10CLK Error of conversion result ≤± 1 LSB ADC10SR = 1 0.450 1.5 MHz fADC10OSC ADC10DIV=0, fADC10CLK =fADC10OSC 2.2 V/ 3V 3.7 6.3 MHz tCONVERT Conversion time Internal oscillator, fADC10OSC = 3.7 MHz to

6.3 MHz

2.2 V/ 3 V 2.06 3.51 µs tCONVERT Conversion time External fADC10CLK from ACLK, MCLK or SMCLK: ADC10SSEL ≠ 0 13×ADC10DIV × 1/fADC10CLK µs tADC10ON ‡ Turn on settling time of the ADC (see Note 1) 100 ns tSample‡ Sampling time R S = 400 Ω, RI = 2000 Ω, 3 V 1400 nstSample‡ Sampling time R S = 400 Ω, RI = 2000 Ω, C I = 20 pF (see Note 2) 2.2 V 1400 ns † Not production tested, limits characterized ‡ Not production tested, limits verified by design NOTES: 1. The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already settled. 2. Approximately eight Tau (τ) are needed to get an error of less than ±0.5 LSB. tSample = ln(2n+1) x (RS + RI) x CI+ 800 ns. (ADC10SR = 0, n = ADC resolution = 10, RS = external source resistance) tSample = ln(2n+1) x (RS + RI) x CI+ 2.5 µs. (ADC10SR = 1, n = ADC resolution = 10, RS = external source resistance) 10-bit ADC, linearity parameters PARAMETER TEST CONDITIONS MIN NOM MAX UNIT EI Integral linearity error 1.4 V ≤ (VeREF+ − VREF− /VeREF− ) min ≤ 1.6 V LSBEI Integral linearity error 1.6 V < (VeREF+ − VREF− /VeREF− ) min ≤ [VCC ] 2.2 V/3 V ±1 LSB ED Differential linearity error (VeREF+ − VREF− /VeREF− )min ≤ (VeREF+ − VREF− /VeREF− ) 2.2 V/3 V ±1 LSB EO Offset error (VeREF+ − VREF− /VeREF− )min ≤ (VeREF+ − VREF− /VeREF− ), Internal impedance of source RS < 100 Ω, 2.2 V/3 V ±2 ±4 LSB EG Gain error (VeREF+ − VREF− /VeREF− )min ≤ (VeREF+ − VREF− /VeREF− ), 2.2 V/3 V ±1.1 ±2 LSB ET Total unadjusted error (VeREF+ − VREF− /VeREF− )min ≤ (VeREF+ − VREF− /VeREF− ), 2.2 V/3 V ±2 ±5 LSB

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003

28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 10-bit ADC, temperature sensor and built-in VMID PARAMETER TEST CONDITIONS MIN NOM MAX UNIT ISENSOR Operating supply current intoREFON = 0, INCH = 0Ah, 2.2 V 40 120 AISENSOR Operating supply current into VCC terminal (see Note 1) REFON = 0, INCH = 0Ah, ADC10ON=NA, T A = 25/C0095C 3 V 60 160 µA VSENSOR † ADC10ON = 1, INCH = 0Ah, 2.2 V 986 986±5% mVVSENSOR † ADC10ON = 1, INCH = 0Ah, TA = 0°C 3 V 986 986±5% mV TC SENSOR † ADC10ON = 1, INCH = 0Ah 2.2 V 3.55 3.55±3% mV/°CTC SENSOR † ADC10ON = 1, INCH = 0Ah 3 V 3.55 3.55±3% mV/°C tSENSOR(sample) † Sample time required if channelADC10ON = 1, INCH = 0Ah, 2.2 V 30 stSENSOR(sample) † Sample time required if channel 10 is selected (see Note 2) ADC10ON = 1, INCH = 0Ah, Error of conversion result ≤ 1 LSB 3 V 30 µs IVMID Current into divider at channel 11ADC10ON = 1, INCH = 0Bh,

2.2 V NA

Current into divider at channel 11 (see Note 3) ADC10ON = 1, INCH = 0Bh, 3 V NA µA VMID VCC divider at channel 11 ADC10ON = 1, INCH = 0Bh, 2.2 V 1.1 1.1±0.04 VVMID VCC divider at channel 11 ADC10ON = 1, INCH = 0Bh, VMID is ~0.5 x VCC 3 V 1.5 1.50±0.04 V tVMID(sample) Sample time required if channelADC10ON = 1, INCH = 0Bh, 2.2 V 1400 nstVMID(sample) Sample time required if channel 11 is selected (see Note 4) ADC10ON = 1, INCH = 0Bh, Error of conversion result ≤ 1 LSB 3 V 1220 ns † Not production tested, limits characterized NOTES: 1. The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1), or (ADC10ON=1 and INCH=0Ah and sample signal is high). Therefore it includes the constant current through the sensor and the reference. 2. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on) . 3. No additional current is needed. The VMID is used during sampling. 4. The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003 29POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) Flash Memory PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT VCC(PGM/ ERASE) Program and Erase supply voltage 2.7 3.6 V fFTG Flash Timing Generator frequency 257 476 kHz IPGM Supply current from VCC during program 2.7 V/ 3.6 V 3 5 mA IERASE Supply current from VCC during erase 2.7 V/ 3.6 V 3 7 mA tCPT Cumulative program time see Note 1 2.7 V/ 3.6 V 4 ms tCMErase Cumulative mass erase time see Note 2 2.7 V/ 3.6 V 200 ms Program/Erase endurance 104 105 cycles tRetention Data retention duration TJ = 25°C 100 years tWord Word or byte program time 35 tBlock, 0 Block program time for 1st byte or word 30 tBlock, 1-63 Block program time for each additional byte or word see Note 3 tFTGtBlock, End Block program end-sequence wait time see Note 3 6 tFTG tMass Erase Mass erase time 5297 tSeg Erase Segment erase time 4819 NOTES: 1. The cumulative program time must not be exceeded during a block-write operation. This parameter is only relevant if the block write feature is used. 2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG ,max = 5297x1/476kHz). To achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met. (A worst case minimum of 19 cycles are required). 3. These values are hardwired into the Flash Controller’s state machine; tFTG = 1/fFTG . JTAG Interface PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT fTCK TCK input frequency see Note 1

2.2 V 0 5 MHz

fTCK TCK input frequency see Note 1 3 V 0 10 MHz R Internal Internal pull-up resistance on TMS, TCK, TDI/TCLKsee Note 2 2.2 V/ 3 V 25 60 90 kΩ NOTES: 1. f TCK may be restricted to meet the timing requirements of the module selected. 2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all Flash versions. JTAG Fuse (see Note 1) PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT VCC(FB) Supply voltage during fuse-blow condition TA = 25°C 2.5 V VFB Voltage level on TEST for fuse-blow 6 7 V IFB Supply current into TEST during fuse blow 100 mA tFB Time to blow fuse 1 ms NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched to bypass mode.

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003

30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

Port P1, P1.0 to P1.3, input/output with Schmitt-trigger EN D P1.0/TACLK/ADC10CLK P1.1/TA0 P1.2/TA1 P1.3/TA2 Interrupt Edge Select EN Set Q P1IE.x P1IFG.x P1IRQ.x Interrupt Flag P1IES.x P1SEL.x Module X IN P1IN.x P1OUT.x Module X OUT Direction Control From Module P1DIR.x P1SEL.x Pad Logic NOTE: x = Bit/identifier, 0 to 3 for port P1 PnSel.x PnDIR.x DIRECTION CONTROL FROM MODULE † Signal from or to Timer_A

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003 31POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 input/output schematic (continued) Port P1, P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features EN D P1.4−P1.7 Interrupt Edge Select EN Set Q P1IE.x P1IFG.x P1IRQ.x Interrupt Flag P1IES.x P1SEL.x Module X IN P1IN.x P1OUT.x Module X OUT Direction Control From Module P1DIR.x P1SEL.x Pad Logic Bus Keeper 60 kΩ Control by JTAG TDO Controlled By JTAG P1.x TDI P1.xTST TMS TST TCK TST Controlled by JTAG TST P1.x P1.x NOTE: The test pin should be protected from potential EMI and ESD voltage spikes. This may require a smaller external pulldown resistor in some applications. x = Bit identifier, 4 to 7 for port P1 During programming activity and during blowing the fuse, the pin TDO/TDI is used to apply the test input for JTAG circuitry. P1.7/TA2/TDO/TDI P1.6/TA1/TDI/TCLK P1.5/TA0/TMS P1.4/SMCLK/TCK Typical TEST Bum and Test Fuse DV CC PnSel.x PnDIR.x DIRECTION CONTROL FROM MODULE † Signal from or to Timer_A

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003

32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

input/output schematic (continued) Port P2, P2.0 to P2.2, input/output with Schmitt-trigger P2OUT. x Module X Out P2DIR.x Direction Control From Module P2SEL.x D EN Interrupt Edge Select P2IES.x P2SEL.x P2IE.x P2IFG.x P2IRQ.x EN Set Q to ADC10, P2.0/ACLK/A0 P2.1/INCLK/A1 P2.2/TA0/A2 Module X In P2IN.x a0, or a1, or a2 selected in ADC10 Pad Logic 0: input 1: output Bus Keeper ADC10AE.x NOTE: 0 ≤ x ≤ 2 a0, or a1, or a2 PnSel.x PnDIR.x DIRECTION CONTROL FROM MODULE † Timer_A

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003 33POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 input/output schematic (continued) Port P2, P2.3 to P2.4, input/output with Schmitt-trigger P2OUT.4 Module X Out P2DIR.4 P2SEL.4 D EN Interrupt Edge Select P2IES.4 P2SEL.4 P2IE.4 P2IFG.4 P2IRQ.07 EN Set Q to ADC10, a4 P2.4/ Unused P2IN.4 a4 Selected Pad Logic 0: input 1: output Bus Keeper ADC10AE.4 P2DIR.4 TA2/ A4/ V REF+ P2OUT.3 Module X Out P2DIR.3 P2SEL.3 D EN Interrupt Edge Select P2IES.x P2SEL.x P2IE.4 P2IFG.4 P2IRQ.07 EN Set Q to ADC10, a3 P2.3/ Module X In P2IN.4 a3 Selected Pad Logic 0: input 1: output Bus Keeper ADC10AE.3 P2DIR.3 TA1/ A3/ V REF− Reference Circuit in ADC10 Module ON ON Typ. 1.25 V a10 on REFON REF_x AV CC OUTREF+ 2_5 V AV CC V +R AV SS V −R SREF ADC10 CTL0.12..14) SREF.2 ADC10 CTL0.14) 0,4 1,5 /VeREF− V eREF+

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003

34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Port P2, P2.3 to P2.4, input/output with Schmitt-trigger (continued) PnSel.x PnDIR.x DIRECTION CONTROL FROM MODULE † Timer_A input/output schematic (continued) Port P2, P2.5, input/output with Schmitt-trigger and ROSC function for the Basic Clock Module EN D P2.5/ROSC Interrupt Edge Select EN Set Q P2IE.5 P2IFG.5 P2IRQ.5 Interrupt Flag P2IES.5 P2SEL.5 Module X IN P2IN.5 P2OUT.5 Module X OUT Direction Control From Module P2DIR.5 P2SEL.5 Pad Logic NOTE: DCOR: Control bit from Basic Clock Module: if it is set P2.5 is disconnected from P2.5 pad. Bus Keeper 0 1VCC Internal to Basic Clock Module DCOR DC Generator 0: Input 1: Output PnSel.x PnDIR.x DIRECTION CONTROL FROM MODULE

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003 35POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 input/output schematic (continued) Port P2, unbonded bits P2.6 and P2.7 EN D Interrupt Edge Select EN Set Q P2IE.x P2IFG.x P2IRQ.x Interrupt Flag P2IES.x P2SEL.x Module X IN P2IN.x P2OUT.x Module X OUT Direction Control From Module P2DIR.x P2SEL.x Bus Keeper 0: Input 1: Output Node Is Reset With PUC PUC NOTE: x = Bit/identifier, 6 to 7 for port P2 without external pins P2Sel.x P2DIR.x DIRECTION CONTROL FROM MODULE NOTE: Unbonded bits 6 and 7 of port P2 can be used as interrupt flags. Only software can affect the interrupt flags. They work as software interrupts.

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003

36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

input/output schematic (continued) port P3, P3.0, P3.6 and P3.7 input/output with Schmitt-trigger P3OUT.x Module X Out P3DIR.x Direction Control From Module P3SEL.x D EN To ADC10 P3.0/STE0/A5 P3.6/A6 P3.7/A7 Module X In P3IN.x a5, or a6, or a7 selected in ADC10 Pad Logic 0: input 1: output Bus Keeper ADC10AE.x NOTE: x (0,6,7) a5, or a6, or a7 PnSel.x PnDIR.x Direction Control From Module PnOUT.x Module X OUT PnIN.x Module X IN P3Sel.0 P3DIR.0 VSS P3OUT.0 VSS P3IN.0 STE0 † † USART0

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003 37POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 input/output schematic (continued) port P3, P3.1 input/output with Schmitt-trigger P3.1/SIMO0 P3IN.1 Pad Logic EN D P3OUT1 P3DIR.1 P3SEL.1 (SI)MO0 DCM_SIMO SYNC MM STE STC From USART0 SI(MO)0 To USART0 0: Input 1: Output port P3, P3.2, input/output with Schmitt-trigger P3.2/SOMI0 P3IN.2 Pad Logic EN D P3OUT.2 P3DIR.2 P3SEL.2 DCM_SOMI SYNC MM STE STC SO(MI)0 From USART0 (SO)MI0 To USART0 0: Input 1: Output

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003

38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

input/output schematic (continued) port P3, P3.3, input/output with Schmitt-trigger P3.3/UCLK0 P3IN.3 Pad Logic EN D P3OUT.3 P3DIR.3 P3SEL.3 UCLK.0 DCM_UCLK SYNC MM STE STC From USART0 UCLK0 To USART0 0: Input 1: Output NOTE: UART mode: The UAR T clock can only be an input. If UART mode and UART function are selected, the P3.3/UCLK0 is always an input. SPI, slave mode: The clock applied to UCLK0 is used to shift data in and out. SPI, master mode: The clock to shift data in and out is supplied to connected devices on pin P3.3/UCLK0 (in slave mode). port P3, P3.4, and P3.5 input/output with Schmitt-trigger P3IN.x Module X IN Pad Logic EN D P3OUT.x P3DIR.x P3SEL.x Module X OUT Direction Control From Module 1 P3.4/UTXD0 P3.5/URXD0 0: Input 1: Output x {4,5} PnSel.x PnDIR.x DIRECTION CONTROL FROM MODULE PnOUT.x MODULE X OUT PnIN.x MODULE X IN P3Sel.4 P3DIR.4 VCC P3OUT.4 UTXD0 † P3IN.4 Unused P3Sel.5 P3DIR.5 VSS P3OUT.5 VSS P3IN.5 URXD0 ‡ † Output from USART0 module ‡ Input to USART0 module

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003

40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

16 PINS SHOWN

0.400 (10,15) 0.419 (10,65) 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) A 0.020 (0,51) 0.014 (0,35) 0.291 (7,39) 0.299 (7,59) 0.010 (0,25) 0.050 (1,27) 0.016 (0,40) (15,24) (15,49) PINS ** 0.010 (0,25) NOM A MAX DIM A MIN Gage Plane 0.500 (12,70) (12,95) 0.510 (10,16) (10,41) 0.400 0.410 0.600 0.610 (17,78) 0.700 (18,03) 0.710 0.004 (0,10) M0.010 (0,25) 0.050 (1,27) 0°−/C0257 8° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MS-013

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003 41POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°−/C0257 8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120/C0050/C0044 /C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0050/C0120/C0050 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLAS361C − JANUARY 2002 − REVISED DECEMBER 2003

42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

RHB (S−PQFP−N32) PLASTIC QUAD FLATPACK ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ 4204326/A 04/02 0,05 MAX SEATING PLANE 5,00 0,80 1,00 0,08 5,00 3,25 3,00 C 0,20 REF DIE PAD 3,50 B A C SQ 0,50 0,3032X 0,50 0,18 0,30 0,10 M C A B 32X EXPOSED THERMAL 0,23 0,23 0,18 0,18 D PIN 1 INDEX AREA IDENTIFIER PIN 1 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. QFN (Quad Flatpack No−Lead) Package configuration. D. The Package thermal performance may be enhanced by bonding the thermal die pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected ground leads. E. Falls within JEDEC MO−220.

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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