MSP-STK430A320

MSP430P325_10 TI | Alldatasheet

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MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Low Supply Voltage Range, 2.7 V – 5.5 V /C0068Low Operation Current, 3 mA at 1 MHz, 3 V /C0068Ultralow Power Consumption (Standby Mode Down to 0.1 /C0109A) /C0068Five Power-Saving Modes /C0068Wakeup From Standby Mode in 6 /C0109s /C006816-Bit RISC Architecture, 300 ns Instruction Cycle Time /C0068Single Common 32 kHz Crystal, Internal System Clock up to 3.3 MHz /C0068Integrated LCD Driver for up to 84 Segments /C0068Integrated 12+2 Bit A/D Converter /C0068Family Members Include: – MSP430P325, 16KB OTP, 512 Byte RAM /C0068EPROM Version Available for Prototyping: PMS430E325 /C0068Serial Onboard Programming /C0068Programmable Code Protection by Security Fuse /C0068Avaliable in 64 Pin Quad Flatpack (QFP),

68 Pin Plastic J-Leaded Chip Carrier

(PLCC), 68 Pin J-Leaded Ceramic Chip Carrier (JLCC) Package (EPROM Version)

description

The Texas Instruments MSP430 is an ultralow-power mixed-signal microcontroller family consisting of several devices which feature different sets of modules targeted to various applications. The microcontroller is designed to be battery operated for an extended application lifetime. With 16-bit RISC architecture, 16-bit integrated registers on the CPU, and a constant generator, the MSP430 achieves maximum code efficiency. The digitally- controlled oscillator, together with the frequency-locked-loop (FLL), provides a wakeup from a low-power mode to active mode in less than 6 /C0109s. Copyright  2000, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 20 2122 23 2425 26 27282930 31 32 64 636261 60 595857 56 55 545352 (TOP VIEW) AV CC DV CC SV CC Rext Xin Xout/TCLK CIN TP0.0 TP0.1 TP0.2 TP0.3 TP0.4 TP0.5 P0.0 P0.1/RXD COM0 S20/O20/CMPI S19/O19 S18/O18 S17/O17 S16/O16 S15/O15 S14/O14 S13/O13 S12/O12 S11/O11 S10/O10 S9/O9 S8/O8 S7/O7 S6/O6 S5/O5 S4/O4 S3/O3 DVSS AVSS XBUF RST/NMI TCK TMS TDI/VPP TDO/TDI COM3 COM2 COM1 P0.2/TXD P0.3 P0.4 P0.5 P0.6 P0.7 R33 R23 R13 R03 S2/O2

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description (continued) Typical applications include sensor systems that capture analog signals, convert them to digital values, and then process the data and display them or transmit them to a host system. The MSP430x32x offers an integrated 12+2 bit A/D converter with six multiplexed inputs. AVAILABLE OPTIONS PACKAGED DEVICES TA PLASTIC 64-PIN QFP (PG) PLASTIC 64-PIN QFP (PM) PLASTIC 68-PIN PLCC (FN) CERAMIC 68-PIN JLCC (FZ) 40°Ct o8 5°C MSP430P325IPG MSP430P325IPM MSP430P325IFN–40°C to 85°C MSP430P325IPG MSP430P325IPM MSP430P325IFN — 25°C PMS430E325FZ25°C — — — PMS430E325FZ functional block diagram Oscillator FLL System Clock ACLK MCLK 8/16 kB ROM 16 kB OTP ’C’: ROM 256/512 B RAM Power-on- Reset 8 b Timer/ Counter Serial Protocol I/O Port

8 I/O’s, All With

Interr. Cap. 3 Int. Vectors CPU Incl. 16 Reg. Test JTAG Bus Conv Timer/Port Applications: Timer, O/P Basic LCD

84 Segments

1, 2, 3, 4 MUX Timer1 ADC 12 + 2 Bit

6 Channels

MAB, 16 Bit MDB, 16 Bit MAB, 4 Bit MDB, 8 Bit MCB LCDf CMPI TP0.0–5 CIN XIN Xout/TCLK XBUF P0.0 P0.7 Com0–3 S0–19/O2–19 S20/O20CMPI R33 R13 TDI/VPP TDO/TDI TMS TCK TXD ’P’: OTP A/D Conv. Support RXD Watchdog Timer 15/16 Bit Current S. A0–5 Rext SVCC RST /NMI R23 R03

MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION AV CC 1 Positive analog supply voltage AV SS 63 Analog ground reference A0 61 I Analog-to-digital converter input port 0 or digital input port 0 A1 62 I Analog-to-digital converter input port 1 or digital input port 1 A2–A5 5–8 I Analog-to-digital converter inputs ports 2–5 or digital inputs ports 2–5 CIN 11 I Input used as enable of counter TPCNT1 – Timer/Port COM0–3 51–54 O Common outputs, used for LCD backplanes – LCD DV CC 2 Positive digital supply voltage DV SS 64 Digital ground reference P0.0 18 I/O General-purpose digital I/O P0.1/RXD 19 I/O General-purpose digital I/O, receive digital input port, 8-Bit Timer/Counter P0.2/TXD 20 I/O General-purpose digital I/O, transmit data output port, 8-Bit Timer/Counter P0.3–P0.7 21–25 I/O Five general-purpose digital I/Os, bit 3 to bit 7 Rext 4 I Programming resistor input of internal current source RST /NMI 59 I Reset input or non-maskable interrupt input R03 29 I Input of fourth positive analog LCD level (V4) – LCD R13 28 I Input of third positive analog LCD level (V3) – LCD R23 27 I Input of second positive analog LCD level (V2) – LCD R33 26 O Output of first positive analog LCD level (V1) – LCD SV CC 3 Switched AVCC to analog-to-digital converter S0 30 O Segment line S0 – LCD S1 31 O Segment line S1 – LCD S2–S5/O2–O5 32–35 O Segment lines S2 to S5 or digital output ports O2–O5, group 1 – LCD S20/O20/CMPI 50 I/O Segment line S20 can be used as comparator input port CMPI – Timer/Port S6–S9/O6–O9 36–39 O Segment lines S6 to S9 or digital output ports O6–O9, group 2 – LCD S10–S13/O10–O13 40–43 O Segment lines S10 to S13 or digital output ports O10–O13, group 3 – LCD S14–S17/O14–O17 44–47 O Segment lines S14 to S17 or digital output ports O14 to O17, group 4 – LCD S18-S19/O18-O19 48, 49 O Segment lines S18 and S19 or digital output port O18 and O19, group 5 – LCD TCK 58 I Test clock, clock input terminal for device programming and test TDO/TDI 55 I/O Test data output, data output terminal or data input during programming TDI/VPP 56 I Test data input, data input terminal or input of programming voltage TMS 57 I Test mode select, input terminal for device programming and test TP0.0 12 O General-purpose 3-state digital output port, bit 0 – Timer/Port TP0.1 13 O General-purpose 3-state digital output port, bit 1 – Timer/Port TP0.2 14 O General-purpose 3-state digital output port, bit 2 – Timer/Port TP0.3 15 O General-purpose 3-state digital output port, bit 3 – Timer/Port TP0.4 16 O General-purpose 3-state digital output port, bit 4 – Timer/Port TP0.5 17 I/O General-purpose digital input/output port, bit 5 – Timer/Port XBUF 60 O Clock signal output of system clock MCLK or crystal clock ACLK Xin 9 I Input terminal of crystal oscillator Xout/TCLK 10 I/O Output terminal of crystal oscillator or test clock input

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time to one cycle of the processor frequency. language. The instruction set consists of 51 instructions with three formats and seven addressing modes. Table 1. Instruction Word Formats Each instruction that operates on word and byte data is identified by the suffix B.

Table 2. Address Mode Descriptions instead of using flag type programs for flow control. instruction to the mode that was selected before the interrupt event. The clocks used are ACLK and MCLK. ACLK is the crystal frequency and MCLK is a multiple of ACLK and is used as the system clock. /C0068Active mode (AM). The CPU is enabled with different combinations of active peripheral modules. are active, and loop control for MCLK is active. are active, and loop control for MCLK is inactive. and MCLK and loop control for MCLK are inactive. (/C0179MCLK generator) is switched off. on or off using one register bit.

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operation modes and interrupts (continued) The most general bits that influence current consumption and support fast turnon from low-power operating modes are located in the status register (SR). Four of these bits control the CPU and the system clock generator: SCG1, SCG0, OscOff, and CPUOff. Reserved For Future Enhancements 15 9 8 7 0 V SCG1 SCG0 OscOff CPUOff GIE N Z C rw-0 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the ROM with an address range of 0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power-up, external reset, watchdog WDTIFG (see Note1) Reset 0FFFEh 15, highest NMI, oscillator fault NMIIFG (see Notes 1 and 3) OFIFG (see Notes 1 and 4) Non-maskable, (Non)-maskable 0FFFCh 14 Dedicated I/O P0.0 P0.0IFG Maskable 0FFFAh 13 Dedicated I/O P0.1 or 8-Bit Timer/Counter RXD P0.1IFG Maskable 0FFF8h 12 0FFF6h 11 Watchdog Timer WDTIFG Maskable 0FFF4h 10 0FFF2h 9 0FFF0h 8 0FFEEh 7 0FFECh 6 ADC ADCIFG Maskable 0FFEAh 5 Timer/Port RC1FG, RC2FG, EN1FG (see Note 2) Maskable 0FFE8h 4 0FFE6h 3 0FFE4h 2 Basic Timer1 BTIFG Maskable 0FFE2h 1 I/O port 0, P0.2–7 P0.27IFG (see Note 1) Maskable 0FFE0h 0, lowest NOTES: 1. Multiple source flags 2. Timer/Port interrupt flags are located in the T/P registers 3. Non-maskable: neither the individual nor the general interrupt enable bit will disable an interrupt event. 4. (Non)-maskable: the individual interrupt enable bit can disable on interrupt event, but the general interrupt enable bit cannot.

MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operation modes and interrupts (continued) special function registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits that are not allocated to a functional purpose are not physically present in the device. Simple SW access is provided with this arrangement. interrupt enable 1 and 2 76 54 0 P0IE.1 OFIE WDTIE 32 1 P0IE.0 rw-0 rw-0 rw-0 rw-0 Address WDTIE: Watchdog Timer enable signal OFIE: Oscillator fault enable signal P0IE.0: Dedicated I/O P0.0 P0IE.1: P0.1 or 8-Bit Timer/Counter, RXD 76 54 0 ADIE rw-0 32 1 rw-0 Address 01h BTIE TPIE rw-0 ADIE: A/D converter enable signal TPIE: Timer/Port enable signal BTIE: Basic Timer1 enable signal interrupt flag register 1 and 2 76 54 0 P0IFG.1 OFIFG WDTIFG 32 1 rw-0 rw-1 rw-0 Address 02h NMIIFG P0IFG.0 rw-0 rw-0 WDTIFG: Set on overflow or security key violation or Reset on V CC power on or reset condition at RST/NMI-pin OFIFG: Flag set on oscillator fault P0.0IFG: Dedicated I/O P0.0 P0.1IFG: P0.1 or 8-Bit Timer/Counter, RXD NMIIFG: Signal at RST /NMI-pin 76 54 0 rw 32 1Address 03h BTIFG ADIFG rw-0 BTIFG Basic Timer1 flag ADFIG Analog-to-digital converter flag

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operation modes and interrupts (continued) module enable register 1 and 2 76 54 0 32 1Address 04h 76 54 0 32 1Address 05h Legend rw: rw-0: Bit can be read and written. Bit can be read and written. It is reset by PUC. SFR bit not present in device. memory organization Int. Vector 16 kB OTP or EPROM 512B RAM 16b Per. 8b Per. SFR FFFFh FFE0h FFDFh C000h 03FFh 0200h 01FFh 0100h 00FFh 0010h 000Fh 0000h MSP430P325 PMS430E325

MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 peripherals Peripherals connect to the CPU through data, address, and control busses and can be handled easily with all instructions for memory manipulation. peripheral file map PERIPHERALS WITH WORD ACCESS Watchdog Watchdog Timer control WDTCTL 0120h ADC Data register Reserved Control register Input enable register Input register ADAT ACTL AEN AIN 0118h 0116h 0114h o112h 0110h PERIPHERALS WITH BYTE ACCESS EPROM EPROM control EPCTL 054h Crystal buffer Crystal buffer control CBCTL 053h System clock SCG frequency control SCG frequency integrator SCG frequency integrator SCFQCTL SCFI1 SCFI0 052h 051h 050h Timer/Port Timer/Port enable Timer/Port data Timer/Port counter2 Timer/Port counter1 Timer/Port control TPE TPD TPCNT2 TPCNT1 TPCTL 04Fh 04Eh 04Dh 04Ch 04Bh 8-Bit Timer/Counter 8-Bit Timer/Counter data 8-Bit Timer/Counter preload 8-Bit Timer/Counter control TCDAT TCPLD TCCTL 044h 043h 042h Basic Timer1 Basic Timer counter2 Basic Timer counter1 Basic Timer control BTCNT2 BTCNT1 BTCTL 047h 046h 040h LCD LCD memory 15 LCD memory 1 LCD control & mode LCDM15 LCDM1 LCDCTL 03Fh 031h 030h Port P0 Port P0 interrupt enable Port P0 interrupt edge select Port P0 interrupt flag Port P0 direction Port P0 output Port P0 input P0IE P0IES P0IFG P0DIR P0OUT P0IN 015h 014h 013h 012h 011h 010h Special function SFR interrupt flag2 SFR interrupt flag1 SFR interrupt enable2 SFR interrupt enable1 IFG2 IFG1 IE2 IE1 003h 002h 001h 000h oscillator and system clock Two clocks are used in the system, the system (master) clock (MCLK) and the auxiliary clock (ACLK). The MCLK is a multiple of the ACLK. The ACLK runs with the crystal oscillator frequency. The special design of the oscillator supports the feature of low current consumption and the use of a 32 768 Hz crystal. The crystal is connected across two terminals without any other external components being required. The oscillator starts after applying VCC, due to a reset of the control bit (OscOff) in the status register (SR). It can be stopped by setting the OscOff bit to a 1. The enabled clock signals ACLK, ACLK/2, ACLK/4, or MCLK are accessible for use by external devices at output terminal XBUF.

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oscillator and system clock (continued) The controller system clock has to operate with different requirements according to the application and system conditions. Requirements include: /C0068High frequency in order to react quickly to system hardware requests or events /C0068Low frequency in order to minimize current consumption, EMI, etc. /C0068Stable frequency for timer applications e.g. real-time clock (RTC) /C0068Enable start-stop operation with a minimum of delay These requirements cannot all be met with fast frequency high-Q crystals or with RC-type low-Q oscillators. The compromise selected for the MSP430 uses a low-crystal frequency, which is multiplied to achieve the desired nominal operating range: f (system) = (N+1) × f(crystal) The crystal frequency multiplication is achieved with a frequency locked loop (FLL) technique. The factor N is set to 31 after a power-up clear condition. The FLL technique, in combination with a digital controlled oscillator (DCO) provides immediate start-up capability together with long term crystal stability. The frequency variation of the DCO with the FLL inactive is typically 330 ppm, which means that with a cycle time of 1 ms the maximum possible variation is 0.33 ns. For more precise timing, the FLL can be used forcing longer cycle times, if the previous cycle time was shorter than the selected one. This switching of cycle times makes it possible to meet the chosen system frequency over a long period of time. The start-up operation of the system clock depends on the previous machine state. During a power-up clear (PUC), the DCO is reset to its lowest possible frequency. The control logic starts operation immediately after recognition of PUC. Connect operation of the FLL control logic requires the presence of a stable crystal oscillator. digital I/O One 8-Bit I/O port (Port0) is implemented. Six control registers give maximum flexibility of digital input/output to the application: /C0068All individual I/O bits are programmable independently. /C0068Any combination of input, output, and interrupt conditions is possible. /C0068Interrupt processing of external events is fully implemented for all eight bits of port P0. /C0068Provides read/write access to all registers with all instructions The six registers are: /C0068Input register Contains information at the pins /C0068Output register Contains output information /C0068Direction register Controls direction /C0068Interrupt flags Indicates if interrupt(s) are pending /C0068Interrupt edge select Contains input signal change necessary for interrupt /C0068Interrupt enable Contains interrupt enable pins All six registers contain eight bits except for the interrupt flag register and the interrupt enable register. The two LSBs of the interrupt flag and interrupt enable registers are located in the special functions register (SFR). Three interrupt vectors are implemented, one for Port0.0, one for Port0.1, and one commonly used for any interrupt

MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 LCD drive Liquid crystal displays (LCDs) for static, 2-, 3- and 4-MUX operations can be driven directly. The controller LCD logic operation is defined by software using memory-bit manipulation. LCD memory is part of the LCD module, not part of data memory. Eight mode and control bits define the operation and current consumption of the LCD drive. The information for the individual digits can be easily obtained using table programming techniques combined with the correct addressing mode. The segment information is stored in LCD memory using instructions for memory manipulation. The drive capability is mainly defined by the external resistor divider that supports the analog levels for 2-, 3- and 4-MUX operation. Groups of the LCD segment lines can be selected for digital output signals. The MSP430x32x configuration has four common signal lines and 21 segment lines. A/D converter The analog-to-digital converter (ADC) is a cascaded converter type that converts analog signals from V CC to GND. It is a 12+2 bit converter with a software or automatically-controlled range select. Five inputs can be selected for analog or digital function. A ratiometric current source can be used on four of the analog pins. The current is adjusted by an external resistor and is enabled/disabled by bits located in the control registers. The conversion is started by setting the start-of-conversion bit (SOC) in the control register and the end-of-conversions sets the interrupt flag. The analog input signal is sampled starting with SOC during the next twelve MCLK clock pulses. The power-down bit in the control register controls the operating mode of the ADC peripheral. The current consumption and operation is stopped when it is set. The system reset PUC sets the power-down bit. Basic Timer1 The Basic Timer1 (BT1) divides the frequency of MCLK or ACLK, as selected with the SSEL bit, to provide low frequency control signals. This is done within the system by one central divider, the Basic Timer1, to support low current applications. The BTCTL control register contains the flags which control or select the different operational functions. When the supply voltage is applied or when a reset of the device (RST /NMI pin), a watchdog overflow or a watchdog security key violation occurs, and all bits in the register hold undefined or unchanged status. The user software usually configures the operational conditions on the BT1 during initialization. The Basic Timer1 has two 8-Bit timers which can be cascaded to a 16-bit timer. Both timers can be read and written by software. Two bits in the SFR address range handle the system control interaction according to the function implemented in the Basic Timer1. These two bits are the Basic Timer1 interrupt flag (BTIFG) and the Basic Timer1 interrupt enable (BTIE) bit. Watchdog Timer The primary function of the Watchdog Timer (WDT) module is to perform a controlled system restart after a software upset has occurred. If the selected time interval expires, a system reset is generated. If this watchdog function is not needed in an application, the module can work as an interval timer, which generates an interrupt after the selected time interval. The Watchdog Timer counter (WDTCNT) is a 15/16-bit up-counter which is not directly accessible by software. The WDTCNT is controlled using the Watchdog Timer control register (WDTCTL), which is an 8-Bit read/write register. Writing to WDTCTL, in both operating modes (watchdog or timer) is only possible by using the correct password in the high-byte. The low-byte stores data written to the WDTCTL. The high-byte password is 05Ah. If any value other than 05Ah is written to the high-byte of the WDTCTL, a system reset PUC is generated. When the password is read its value is 069h. This minimizes accidental write operations to the WDTCTL register. In addition to the Watchdog Timer control bits, two bits included in the WDTCTL configure the NMI pin.

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The 8-Bit interval timer supports three major functions for the application: /C0068Serial communication or data exchange /C0068Pulse counting or pulse accumulation /C0068Timer The 8-Bit Timer/Counter peripheral includes the following major blocks: an 8-Bit up-counter with preload register, an 8-Bit control register, an input clock selector, an edge detection (e.g. Start bit detection for asynchronous protocols), and an input and output data latch, triggered by the carry-out-signal from the 8-Bit counter. The 8-Bit counter counts up with an input clock which is selected by two control bits from the control register. The four possible clock sources are MCLK, ACLK, the external signal from terminal P0.1, and the signal from the logical AND of MCLK and terminal P0.1. Two counter inputs (load, enable) control the counter operation. The load input controls load operations. A write-access to the counter results in loading the content of the preload register into the counter. The software writes or reads the preload register with all instructions. The preload register acts as a buffer and can be written immediately after the load of the counter is completed. The enable input enables the count operation. When the enable signal is set to high, the counter will count-up each time a positive clock edge is applied to the clock input of the counter. Serial protocols, like UART protocol, need start-bit edge-detection to determine, at the receiver, the start of a data transmission. When this function is activated, the counter starts counting after the start-bit condition is detected. The first signal level is sampled into the RXD input data-latch after completing the first timing interval, which is programmed into the counter. Two latches are used for input and output data (RXD_FF and TXD_FF) are clocked by the counter after the programmed timing interval has elapsed. UART The serial communication uses software and the 8-Bit Timer/Counter hardware. The hardware supports the output of the serial data stream, bit-by-bit, with the timing determined by the counter. The software/hardware interface connects the mixed signal controller to external devices, systems, or networks. Timer/Port The Timer/Port module has two 8-Bit counters, an input that triggers one counter, and six 3-state digital outputs. Both counters have an independent clock-selector for selecting an external signal or one of the internal clocks (ACLK or MCLK). One of the counters has an extended control capability to halt, count continuously, or gate the counter by selecting one of two external signals. This gate signal sets the interrupt flag, if an external signal is selected, and the gate stops the counter. Both timers can be read from and written to by software. The two 8-Bit counters can be cascaded to a 16-bit counter. A common interrupt vector is implemented. The interrupt flag can be set from three events in the 8-Bit counter mode (gate signal, overflow from the counters) or from two events in the 16-bit counter mode (gate signal, overflow from the MSB of the cascaded counter).

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 5: All voltage values relative to VSS .

0.7 VCC VCC

NOTE: Minimum processor frequency is defined by system clock. Figure 1. Processor Frequency vs Supply Voltage

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electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) supply current into AVCC +DV CC excluding external current, fsystem = 1 MHz PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I(AM) Active mode, A/D conversion in P325 TA = –40°C to 85°C, VCC = 3 V 3000 5000 mAI(AM) power-down P325 TA = –40°C to 85°C, VCC = 5 V 10000 12000 mA I(CPUOff) Low power mode (LPM0 LPM1) P325 TA = –40°C to 85°C, VCC = 3 V 70 110 mAI(CPUOff) Low pow er mode , (LPM0 , LPM1) P325 TA = –40°C to 85°C, VCC = 5 V 150 200 mA I(LPM2) Low power mode (LPM2) TA = –40°C to 85°C, VCC = 3 V 6 12 mAI(LPM2) Low pow er mode , (LPM2) TA = –40°C to 85°C, VCC = 5 V 15 25 mA TA = –40°C 1.5 2.4 TA = 25°C VCC = 3 V 1.3 2 I(LPM3) Low power mode (LPM3) TA = 85°C 1.6 2.8 mAI(LPM3) Low pow er mode , (LPM3) TA = –40°C 5.2 7 mA TA = 25°C VCC = 5 V 4.2 6.5 TA = 85°C 4 7 TA = –40°C 0.1 0.8 I(LPM4) Low power mode, (LPM4) TA = 25°C VCC = 3 V/5 V 0.1 0.8 mA() TA = 85°C 0.4 1.3 NOTE: All inputs are tied to 0 V or VCC . Outputs do not source or sink any current. The current consumption in LPM2, LPM3 and LPM4 are measured with active Basic Timer1 (ACLK selected) and LCD module (f(LCD)=1024 Hz, 4 MUX). current consumption of active mode versus system frequency IAM = IAM[1 MHz] × fsystem [MHz] current consumption of active mode versus supply voltage IAM = IAM[3 V] + 200 mA/V × (VCC –3 V) Schmitt-trigger inputs Port 0, P0.x Timer/Port, CIN, TP 0.5 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIT Positive going input threshold voltage VCC = 3 V 1.2 2.1 VIT+ Positive-going input threshold voltage VCC = 5 V 2.3 3.4 VIT Negative going input threshold voltage VCC = 3 V 0.5 1.35 VVIT– Negative-going input threshold voltage VCC = 5 V 1.4 2.3 V Vh Hysteresis (VIT VIT ) VCC = 3 V 0.3 1 Vhys H ysteresis (VIT+–VIT–) VCC = 5 V 0.6 1.4

MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IOH = –1.2 mA, VCC = 3 V, See Note 6 VCC –0.4 VCC VOH High level output current IOH = –3.5 mA, VCC = 3 V, See Note 7 VCC –1 VCC VVOH High-level output current IOH = –1.5 mA, VCC = 5 V, See Note 6 VCC –0.4 VCC V IOH = –4.5 mA, VCC = 5 V, See Note 7 VCC –1 VCC IOL = 1.2 mA, VCC = 3 V, See Note 6 VSS VSS +0.4 VOL Low-level output voltage IOL = 3.5 mA, VCC = 3 V, See Note 7 VSS VSS +1 VVOL Low -level out ut voltage IOL = 1.5 mA, VCC = 5 V, See Note 6 VSS VSS +0.4 V IOL = 4.5 mA, VCC = 5 V, See Note 7 VSS VSS +1 NOTES: 6. The maximum total current, IOH max and IOL max, for all outputs combined, should not exceed ±9.6 mA to satisfy the maximum voltage drop specified. 7. The maximum total current, IOH max and IOL max, for all outputs combined, should not exceed ±20 mA to satisfy the maximum voltage drop specified. leakage current (see Note 8) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Ilkg(TP) Leakage current, Timer/Port Timer/Port: V(TP0.x,CIN) (see Note 9) ±50 nA Ilkg(P0x) Leakage current, port 0 Port 0: V(P0.x) (see Note 10) V 3 V/5 V ±50 nA Ilkg(S20) Leakage current, S20 V(S20) = VSS to VCC VCC = 3 V/5 V ±50 nA Ilkg(Ax) Leakage current, ADC ADC: Ax, x= 0 to 5 (see Note 11) ±30 nA Ilkg(RST/NMI) Leakage current, RST/NMI ±50 nA NOTES: 8. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. measurement. In the leakage measurement the input CIN is included. The input voltage is VSS or VCC . 10. The port pin must be selected for input and there must be no optional pullup or pulldown resistor. 11. The input voltage is V(IN) = VSS to VCC , the current source is off, AEN.x bit is normally reset to stop throughput current flowing from VCC to VSS terminal. input frequency – Port 0: P0.1; Timer/Port: CIN, TP0.5 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f(IN) Input frequency DC f(system) MHz t(H)or t(L) High level or low level time P0.x, CIN, TP.5 3 V 300 ns t(H) or t(L) High level or low level time

5 V 125 ns

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fXBUF XBUF, C L = 20 pF f(system) MHz XBUF C 20 pF fMCLK = 1.1 MHz 40% 60% tXdc Duty cycle of O/P frequency XBUF , C L = 20 pF, VCC = 3 V/5 V fXBUF = fACLK 35% 65%VCC = 3 V/5 V fXBUF = fACLK/n 50%

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electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) external interrupt timing PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t(int) Port P0: External trigger signal for the interrupt flag (see Notes 12 and 13) 1.5 cycle NOTES: 12. The external signal sets the interrupt flag every time t(int) is met. It may be set even with trigger signals shorter than t(int). The conditions to set the flag must be met independently of this timing constraint. Input frequency (t(int)) is defined in MCLK cycles. 13. The external signal needs additionally a timing resulting from the maximum input frequency constraint. RAM PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VRAMh CPU halted (see Note 14) 1.8 V NOTE 14: This parameter defines the minimum supply voltage when the data in the program memory RAM remains unchanged. No program execution should take place during this supply voltage condition. DCO PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f(NOM) DCO N DCO = 1A0h, FN_4=FN_3=FN_2=0 VCC = 3 V/5 V 1 MHz fDCO3 N DCO = 00 0110 0000 FN 4=FN 3=FN 2=0 VCC = 3 V 0.15 0.6 f(NOM) fDCO3 N DCO = 00 0110 0000, FN _4=FN _3=FN _2=0 VCC = 5 V 0.18 0.62 MHzf(NOM) fDCO26 N DCO = 11 0100 0000 FN 4=FN 3=FN 2=0 VCC = 3 V 1.25 4.7 MH z fDCO26 N DCO = 11 0100 0000 FN _4=FN _3=FN _2=0 VCC = 5 V 1.45 5.5 fDCO3 N DCO = 00 0110 0000 FN 4=FN 3=0 FN 2=1 VCC = 3 V 0.36 1.05 2xf(NOM) fDCO3 N DCO = 00 0110 0000, FN _4=FN _3=0, FN _2=1 VCC = 5 V 0.39 1.2 MHz2xf(NOM) fDC26 N DCO = 11 0100 0000 FN 4=FN 3=0 FN 2=1 VCC = 3 V 2.5 8.1 MHz fDC26 N DCO = 11 0100 0000, FN _4=FN _3=0, FN _2=1 VCC = 5 V 3 9.9 fDCO3 N DCO = 00 0110 0000 FN 4=0 FN 3= 1 FN 2=X VCC = 3 V 0.5 1.5 3xf(NOM) fDCO3 N DCO = 00 0110 0000, FN _4=0, FN _3= 1, FN _2=X VCC = 5 V 0.6 1.8 MHz3xf(NOM) fDCO26 N DCO = 11 0100 0000 FN 4= 0 FN 3=1 FN 2=X VCC = 3 V 3.7 11 MHz fDCO26 N DCO = 11 0100 0000, FN _4= 0, FN _3=1, FN _2=X VCC = 5 V 4.5 13.8 fDCO3 N DCO = 00 0110 0000 FN 4 =1 FN 3=FN 2=X VCC = 3 V 0.7 1.85 4xf(NOM) fDCO3 N DCO = 00 0110 0000 FN _4 =1, FN _3=FN _2=X VCC = 5 V 0.8 2.4 MHz4xf(NOM) fDCO26 N DCO = 11 0100 0000 FN 4=1 FN 3=FN 2=X VCC = 3 V 4.8 13.3 MHz fDCO26 N DCO = 11 0100 0000, FN _4=1, FN _3=FN _2=X VCC = 5 V 6 17.7 N DCO fMCLK = fNOM , FN_4=FN_3=FN_2=0 VCC = 3 V/5 V A0h 1A0h 340h S fNDCO+1 = S × fNDCO VCC = 3 V/5 V 1.07 1.13

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Figure 4. V(POR) vs Temperature

MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) ADC supply current (f(ADCLK) = 1 MHz) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT I(ADC) ADC current SV CC on, current source off, VCC = 3 V 200 400 mA I(ADC) ADC current SV CC on, current source off, VCC = 5 V 300 740 mA SV CC (switched AVCC ) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT V(SVCC) SV CC on, I(SVCC) = –8 mA, VCC = 2.5 V VCC –0.2 V VCC V I(SVCC) SV CC off, SVCC = 0 V, VCC = 5 V ±0.1 mA Z(SVCC) Input impedance SV CC off, VCC = 3 V/5 V 40 100 kW current source (ADC) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(Rext) Voltage, (Rext) V(Rext) = V(SVCC) – V(RI), I(RI) = 6 mA, VCC = 3 V/5 V, 0.246 × V(SVCC) 0.249 × V(SVCC) 0.252 × V(SVCC) V R (ext) External resistor VCC = 3 V/5 V 95 1600 W V(Rext)/R(ext) = 1 mA VCC = 3 V, –1 1 mA DIS Load compliance IS = V(Rext)/R(ext) = 6 mA VCC = 3 V, –3.2 3.2 mA DIS Load compliance IS = V(Rext)/R(ext)= 1 mA VCC = 5 V, –1.5 1.5 mA IS = V(Rext)/R(ext)= 6 mA VCC = 5 V, –3.2 3.2 mA

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electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) A/D converter (f(ADCLK) = 1 MHz) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution 12 + 2 bits f() Conversion frequency f() =f(ADCLK) 12-bit conversion VCC = 3 V/5 V 0.1 1.5 MHzf(con) Conversion frequency f(con) = f(ADCLK) 12+2-bit conversion VCC = 3 V/5 V 0.14 1.5 MHz f() Conversion cycles f(ADCLK) =f(MCLK)/N 12-bit conversion VCC = 3 V/5 V 96 cycles off(concyc) Conversion cycles f(ADCLK) = f(MCLK)/N 12+2-bit conversion VCC = 3 V/5 V 132 y ADCLK LSB Voltage VCC = 3 V/5 V 0.000061×VSVCC V INL1 0 ≤ DDV ≤ 127 VCC = 3 V/5 V –2 2 LSB INL2 Integral nonlinearity 128 ≤ DDV ≤ 255 VCC = 3 V/5 V –3 3 LSB INL3 gy (see Note 15) 256 ≤ DDV ≤ 2047 VCC = 3 V/5 V –7 7 LSB INL4 2048 ≤ DDV ≤ 4095 VCC = 3 V/5 V –10 10 LSB DNL Differential nonlinearity (see Note 16) VCC = 3 V/5 V –1 1 LSB dN/dT Tem perature stability V(Rext)/R(ext) = 6mA, Range A VCC = 3 V/5 V 0.008 LSB/°CdN/dT Temperature stability Range B VCC = 3 V/5 V

0.015 LSB/°C

dN/dV(SVCC) V(SVCC)rejection ratio Range A, B, V(Rext)/R(ext) = 1 mA, SV CC ±10% VCC = 3 V/5 V 1.25 LSB/V Range A VCC = 3 V/5 V –1.2 –0.49 0.24 % FSR A (see Note 18) Conversion offset 12 bit analog input to Range B VCC = 3 V/5 V –1.7 –0.6 0.49 % FSR B (see Note 18)g digital value (see Note 17) Range C VCC = 3 V/5 V –1.8 –0.6 0.6 % FSR C (see Note 18) Range D VCC = 3 V/5 V –1.7 0.6 0.49 % FSR D (see Note 18) Conversion offset 14 bit analog input to digital value (see Note 17) Range ABCD VCC = 3 V/5 V –0.27 –0.06 0.13 %FSR ABCD (see Note 18) Slope 12 bit VCC = 3 V/5 V 0.9925 1 1.0075 Slope 14 bit VCC = 3 V/5 V 0.9982 1 1.0018 C (IN) Input capacitance VCC = 3 V/5 V 40 45 pF R (SIN) Serial input resistance VCC = 3 V/5 V 2 kW NOTES: 15. DDV is short form of delta digital value. The DDV is a span of conversion results. It is assumed that the conversion is of 12 bit not 12+2 bit. 16. DNL is valid for all 12-bit ranges and the 14-bit (12+2) range. 17. Offset referred to full scale 12/14 bit 18. FSRx: full scale range, separate for the four 12-bit ranges and the 14-bit (12+2) range.

MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 21POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) JTAG PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f(TCK) TCK frequency VCC = 3 V DC 5 MHzf(TCK) JTAG/test TCK frequency VCC = 5 V DC 10 MH z R (TEST) JTAG/test Pullup resistors on TMS, TCK, TDI (see Note 19) VCC = 3 V/ 5 V 25 60 90 kW V(FB) JTAG/f ( N t 20) Fuse blow voltage, E/P versions (see Note 21) VCC = 3 V/ 5 V 11 12 V I(FB) JTAG/fuse (see Note 20) Supply current on TDI to blow fuse 100 mA t(FB) Time to blow the fuse 1 ms V(PP) Programming voltage, applied to TDI/VPP 11 11.5 13 V I(PP) Current from programming voltage source 70 mA t(pps) EPROM (E) and OTP(P) – Programming time, single pulse 5 ms t(ppf) () () versions only Programming time, fast algorithm 100 ms Pn Number of pulses for successful programming 4 100 Pulses Data retention TJ < 55°C 10 year t(erase) EPROM (E) versions only Erase time wave length 2537 Å at 15 Ws/cm2 (UV lamp of 12 mW/ cm2) 30 min() y Write/Erase cycles 1000 cycles NOTES: 19. The TMS and TCK pullup resistors are implemented in all C-, P-, and E-versions. 20. Once the JTAG fuse is blown, no further access to the MSP430 JTAG/test feature is possible. The JTAG block switches to by-pass mode. 21. The voltage supply to blow the JTAG fuse is applied to TDI/VPP pin when fuse blowing is desired.

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DIGITAL CONTROLLED OSCILLATOR FREQUENCY vs OPERATING FREE-AIR TEMPERATURE T – Operating Free-Air Temperature – °C 0.9 0.6 0.3 1.2 1.5 1.8 f(DCO) /f(DCO@ 25 )C° –40 –20 0 20 40 90 60 80 Figure 6 VCC – Supply Voltage – V 0.6 0.4 0.2 0.8 1.2 DIGITAL CONTROLLED OSCILLATOR FREQUENCY vs SUPPLY VOLTAGE f(DCO) /f(DCO@ 3 V)

MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 23POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS typical input/output schematics CMOS INPUT (RST /NMI) I/O WITH SCHMITT-TRIGGER INPUT (P0.x, TP5) CMOS 3-STATE OUTPUT (TP0–4, XBUF) VCC (see Note A) (see Note A) GND VCC (see Note A) (see Note A) GND VCC (see Note A) (see Note A) GND VCC 60 k TYP MSP430P/E325: TMS, TCK NOTES: A. Optional selection of pullup or pulldown resistors with ROM (masked) versions. Anti-parallel diodes are connected between AVSS and DVSS . B. Fuses for the optional pullup and pulldown resistors can only be programmed at the factory. CMOS SCHMITT-TRIGGER INPUT (CIN) (see Note B) (see Note B) (see Note B) (see Note B) (see Note B) (see Note B) MSP430P/E325: TDO/TDI TDO_Internal TDO_Control TDI_Control TDI_Internal

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NOTE: The signals VA, VB, VC, and VD come from the LCD module analog voltage generator. source. The TDO/TDI terminal is used to apply the test input data for JTAG circuitry. recommended to avoid a floating node which could increase the current consumption of the device. floating a node which could increase the current consumption of the device. Figure 7. MSP430P325/E325: TDI/VPP, TDO/TDI

TF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TDI/VPP pin to ground if the fuse is not burned. is being held low during power-up. The second positive edge on the TMS pin deactivates the fuse check mode. check mode has the potential to be activated. Figure 8. Fuse Check Mode Current, MSP430P/E325 spikes that could cause signal edges on the TMS pin. Configuration of TMS, TCK, TDI/VPP and TDO/TDI pins in applications.

MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

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PG (R-PQFP-G64) PLASTIC QUAD FLATPACK 4040101/B 03/95 0,15 NOM 18,0014,20 13,80 17,20 12,00 TYP 0,25 1,10 0,70 0,10 MIN Gage Plane 18,00 TYP 23,60 24,40 19,80 20,20 3,10 MAX 2,70 TYP 0,25 0,45 0°–10° Seating Plane 0,10 1,00 M0,20 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Contact field sales office to determine if a tighter coplanarity requirement is available for this package.

MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 27POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSP430P325 (PM package) 17 18 19 S19/O19 S18/O18 S17/O17 S16/O16 S15/O15 S14/O14 S13/O13 S12/O12 S11/O11 S10/O10 S9/O9 S8/O8 S7/O7 S6/O6 S5/O5 S4/O4 DV CC SV CC Rext Xin Xout/TCLK CIN TP0.0 TP0.1 TP0.2 TP0.3 TP0.4 TP0.5 21 22 23 24 COM0 TDO/TDI 63 62 61 60 5964 58 AV XBUF RST/NMI TCK TMS R32 R13 R03 P0.2/TXD P0.3 P0.4 P0.5 P0.6 P0.7 R33 56 55 5457 25 26 27 28 29 53 52 P0.0 COM3 COM2 51 50 49 30 31 32 S2/O2 S3/O3 COM1 TDI/ S20/O20/CMPI AV DV P0.1/RXD SS SS CC PM PACKAGE (TOP VIEW) V PP

MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

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PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 4040152/C 11/96 0,13 NOM 0,25 0,45 0,75 Seating Plane 0,05 MIN Gage Plane 0,27 0,17 SQ SQ10,20 11,80 12,20 9,80 7,50 TYP 1,60 MAX 1,45 1,35 0,08 0,50 M0,08 0°–7° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 D. May also be thermally enhanced plastic with leads connected to the die pads.

MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 29POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSP430P325 (FN package) 28 29 S20/O20/CMPI S19/O19 S18/O18 S17/O17 S16/O16 S15/O15 S14/O14 S13/O13 S12/O12 S11/O11 S10/O10 S9/O9 S8/O8 S7/O7 S6/O6 S5/O5 S4/O4 DV CC SV CC Rext Xin Xout/TCLK CIN TP0.0 TP0.1 TP0.2 TP0.3 TP0.4 TP0.5 P0.0 31 32 33 34 FN PACKAGE (TOP VIEW) TMS TDI/VPP 87 6 5493 XBUF RST/NMI TCK R23 R13 R03 P0.2/TXD P0.3 P0.4 P0.5 P0.6 P0.7 R33 16 8 6 72 35 36 37 38 39 66 65 NC P0.1/RXD TDO/TDI COM3 64 63 62 61 40 41 42 43S1 S2/O2 S3/O3 NC COM2 COM1 COM0 NC NC AVSS DV SS AVCC NC – No internal connection

MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

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FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 4040005/B 03/95

20 PIN SHOWN

0.026 (0,66) 0.032 (0,81) D2/E2 0.020 (0,51) MIN 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D2/E2 0.013 (0,33) 0.021 (0,53) Seating Plane MAX D2/E2 0.219 (5,56) 0.169 (4,29) 0.319 (8,10) 0.469 (11,91) 0.569 (14,45) 0.369 (9,37) MAX 0.356 (9,04) 0.456 (11,58) 0.656 (16,66) 0.008 (0,20) NOM 1.158 (29,41) 0.958 (24,33) 0.756 (19,20) 0.191 (4,85) 0.141 (3,58) MIN 0.441 (11,20) 0.541 (13,74) 0.291 (7,39) 0.341 (8,66) D E1E MINMAXMIN PINS 0.385 (9,78) 0.485 (12,32) 0.685 (17,40) 84 1.185 (30,10) 0.985 (25,02) 0.785 (19,94) D/E 0.395 (10,03) 0.495 (12,57) 1.195 (30,35) 0.995 (25,27) 0.695 (17,65) 0.795 (20,19) NO. OF D1/E1 0.350 (8,89) 0.450 (11,43) 1.150 (29,21) 0.950 (24,13) 0.650 (16,51) 0.750 (19,05) 0.004 (0,10) M0.007 (0,18) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018

MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 31POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PMS430E325 (FZ package) 28 29 S20/O20/CMPI S19/O19 S18/O18 S17/O17 S16/O16 S15/O15 S14/O14 S13/O13 S12/O12 S11/O11 S10/O10 S9/O9 S8/O8 S7/O7 S6/O6 S5/O5 S4/O4 DV CC SV CC rext Xin Xout/TCLK CIN TP0.0 TP0.1 TP0.2 TP0.3 TP0.4 TP0.5 P0.0 31 32 33 34 FZ PACKAGE (TOP VIEW) TMS TDI/ 87 6 5493 XBUF RST/NMI TCK R23 R13 R03 P0.2/TXD P0.3 P0.4 P0.5 P0.6 P0.7 R33 16 8 6 72 35 36 37 38 39 66 65 NC P0.1/RXD COM3 COM2 64 63 62 61 40 41 42 43S1 S2/O2 S3/O3 NC NC AV NC NC – No internal connection CC AVSS DV SS COM1 COM0 TDO/TDI Vpp

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FZ (S-CQCC-J) J-LEADED CERAMIC CHIP CARRIER 4040219/B 03/95 0.180 (4,57) 0.140 (3,55) C 0.020 (0,51) 0.032 (0,81)A B A B 0.025 (0,64) R TYP 0.026 (0,66) 0.120 (3,05) 0.155 (3,94) 0.014 (0,36) 0.120 (3,05) 0.040 (1,02) MIN 0.090 (2,29) A MIN MAX 0.485 (12,32) (12,57) 0.495 0.455 (11,56)(10,92) 0.430 MAXMIN BC MIN MAX 0.410 (10,41) (10,92) 0.430 PINS NO. OFJEDEC MO-087AC MO-087AB MO-087AA OUTLINE

28 LEAD SHOWN

(at Seating Plane) 142 6 1812 5 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit.

www.ti.com 22-Nov-2010 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) MSP-EVK430A320 OBSOLETE 0 TBD Call TI Call TI Samples Not Available MSP-EVK430B320 OBSOLETE 0 TBD Call TI Call TI Samples Not Available MSP-STK430A320 OBSOLETE 0 TBD Call TI Call TI Samples Not Available MSP-STK430B320 OBSOLETE 0 TBD Call TI Call TI Samples Not Available MSP430P325IFN ACTIVE PLCC FN 68 18 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Purchase Samples MSP430P325IPG ACTIVE QFP PG 64 66 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples MSP430P325IPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 22-Nov-2010 Addendum-Page 2

MPLC004A – OCTOBER 1994 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 4040005/B 03/95 0.026 (0,66) 0.032 (0,81) D2/E2 0.020 (0,51) MIN 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D2/E2 0.013 (0,33) 0.021 (0,53) Seating Plane MAX D2/E2 0.219 (5,56) 0.169 (4,29) 0.319 (8,10) 0.469 (11,91) 0.569 (14,45) 0.369 (9,37) MAX 0.356 (9,04) 0.456 (11,58) 0.656 (16,66) 0.008 (0,20) NOM 1.158 (29,41) 0.958 (24,33) 0.756 (19,20) 0.191 (4,85) 0.141 (3,58) MIN 0.441 (11,20) 0.541 (13,74) 0.291 (7,39) 0.341 (8,66) D E1E MINMAXMIN PINS 0.385 (9,78) 0.485 (12,32) 0.685 (17,40) 84 1.185 (30,10) 0.985 (25,02) 0.785 (19,94) D/E 0.395 (10,03) 0.495 (12,57) 1.195 (30,35) 0.995 (25,27) 0.695 (17,65) 0.795 (20,19) NO. OF D1/E1 0.350 (8,89) 0.450 (11,43) 1.150 (29,21) 0.950 (24,13) 0.650 (16,51) 0.750 (19,05) 0.004 (0,10) M0.007 (0,18) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018

MQFP008 – JULY 1998 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PG (R-PQFP-G64) PLASTIC QUAD FLATPACK 4040101/B 03/95 0,15 NOM 18,0014,20 13,80 17,20 12,00 TYP 0,25 1,10 0,70 0,10 MIN Gage Plane 18,00 TYP 23,20 24,00 19,80 20,20 3,10 MAX 2,70 TYP 0,25 0,45 0°–10° Seating Plane 0,10 1,00 M0,20 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Contact field sales office to determine if a tighter coplanarity requirement is available for this package.

MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 4040152/C 11/96 0,13 NOM 0,25 0,45 0,75 Seating Plane 0,05 MIN Gage Plane 0,27 0,17 SQ SQ10,20 11,80 12,20 9,80 7,50 TYP 1,60 MAX 1,45 1,35 0,08 0,50 M0,08 0°–7° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 D. May also be thermally enhanced plastic with leads connected to the die pads.

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