MSHN MSI | Alldatasheet
Document overview
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Technical content
Features
Six Filter Types In One Package No External Components Switched-Capacitor Filters Low Power Operation Low Voltage Operation Input Multiplexor Adjustable Gain 0, 10 or 20 dB Small Package Size Low Cost On Chip Power Save Pin
Applications
Highpass Responses Notch Responses Web Site “www.mix-sig.com” © 2002 Mixed Signal Integration 1 -120 -100 -80 -60 -40 -20 850 875 900 925 950 975 1000 1025 1050 1075 1100 1125 1150 Narrow Deep WideWide -100 -80 -60 -40 -20 50 250 450 650 850 1050 1250 1450 1650 1850 Elliptic Butterworth Bessel
MSHN1/MSHN2/MSHN3/MSHN4/MSHN5/MSHN6 Selectable Highpass/Notch Filter Data Sheet (VDD = +5.0V, T = 25 C)o Web Site “www.mix-sig.com” © 2002 Mixed Signal Integration 2 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC Specifications Operating Voltage VDD 2.7 5 5.5 V Supply Current IDD MSHN1, MSHN2, MSHN5 1 1.5 mA Supply Current IDD MSHN3, MSHN4, MSHN6 200 300 uA Supply Current (Power Down) IDD MSHN2, MSHN4 100 200 uA AC Specifications Gain Av -0.5 0 0.5 dB Noise To 1/2 Sample 250 uVrms Distortion THD A weighted -72 dB Signal Swing 1 kHz 4 4.5 V p-p Input Impedance ZIN 1 Mohm Output Drive Io 1 mA Output Impedance Zo 500 ohm Output Capacitive Load 50 pF Clock to Corner MSHN5, MSHN6 900 1000 1020 Clock to Corner MSHN1, MSHN3 99 100 101 Clock to Corner MSHN2, MSHN4, Fo=0 99 100 101 Clock to Corner MSHN2, MSHN4, Fo=1 900 1000 1020 Center Frequency Range Fo MSHN1, MSHN2 0.001 20 kHz Center Frequency Range Fo MSHN3, MSHN4 0.001 5 kHz Center Frequency Range Fo MSHN5 0.001 2 kHz Center Frequency Range Fo MSHN6 0.001 500 Hz Ripple Elliptic Highpass 0.2 dB Stop Band Rejection Elliptic/Butterworth Highpass 80 dB -3 dB top Notch Bandwidth Narrow Normalized Fo 0.92 1.08 Wide Normalized Fo 0.88 1.12 Deep Normalized Fo 0.89 1.11 Bottom Notch Bandwidth Narrow Normalized Fo 0.99 1.00 1.01 Wide Normalized Fo 0.97 1.00 1.03 Deep Normalized Fo 0.99 1.00 1.01 Notch depth Narrow -70 dB Wide -60 dB Deep -80 dB
MSHN1/MSHN2/MSHN3/MSHN4/MSHN5/MSHN6 Selectable Highpass/Notch Filter Data Sheet Web Site “www.mix-sig.com” © 2002 Mixed Signal Integration 3 VCC 100nF FILTER_OUTPUT HIGHPASS_NOTCH 47kohm 47kohm C2100nF FILTER_INPUT C6 100nF 300kHz 5V MSHN1_3_5_6 FSEL OUT TYPE CLK IN GND VSS VDD 2.5V VDD C1100nF FILTER_OUTPUT HIGHPASS_NOTCH C2100nF FILTER_INPUT -2.5V VSS P2V5_N2V5_300kHz MSHN1_3_5_6 FSEL OUT TYPE CLK IN GND VSS VDD Single Supply Dual Supply
MSHN1/MSHN2/MSHN3/MSHN4/MSHN5/MSHN6 Selectable Highpass/Notch Filter Data Sheet Web Site “www.mix-sig.com” © 2002 Mixed Signal Integration 4 SELECT3_4 0_10_20dB VCC POWERDOWN 50_100 100nF SELECT_1_2 FILTER_OUTPUT LOWPASS_BANDPASS 47kohm 47kohm C2100nF INPUT_4 INPUT_3 INPUT_2 INPUT_1 C3 100nF C4 100nF C5 100nF C6 100nF 300kHz 5V MSFS2_4 TYPE CLK G VDD PD VSS FO OUT FSEL IN4 IN3 IN2 IN1 GND SELECT3_4 0_10_20dB 2.5V VDD POWERDOWN 50_100 100nF SELECT_1_2 FILTER_OUTPUT LOWPASS_BANDPASS C2100nF INPUT_4 INPUT_3 INPUT_2 INPUT_1 C3 100nF C4 100nF C5 100nF C6 100nF MSFS2_4 TYPE CLK G VDD PD VSS FO OUT FSEL IN4 IN3 IN2 IN1 GND -2.5V VSS P2V5_N2V5_300kHz Single Supply Dual Supply
0 Butterworth Deep
1 Bessel Narrow
2 Elliptic Wide
The filter type is selected using the two filter select pins, TYPE and FSEL, FSEL is a CMOS level pin that selects highpass or notch (highpass = 0, notch = 1). TYPE Is a tertiary control pin that selects the filter response. State 0 is VSS, state 1 is GND and state 2 is VDD. MSHN1/MSHN2/MSHN3/MSHN4/MSHN5/MSHN6 Selectable Highpass/Notch Filter Data Sheet 1. TYPE Filter Response Select Pin. 2. S2 Input Multiplexor Select Pin 3. CLK Clock Input 4. G Gain Select Pin 5. VDD Positive Power Supply, Typically 2.5 Volts for Split Supply 5.0 Volts for Single Supply 6. PD Power Down Pin, CMOS level, Hi = Power Down 7, VSS Negative Power Supply, Typically -2.5 Volts for Split Supply. 0 Volts for Single Supply 8. F0 Clock to Corner Select Pin 9. GND GND Pin, OV for Split Supplies
2.5 Volts Typical for Single Supply
- IN1 Input 1, Select Code 00 11. IN2 Input 2, Select Code 01 12. IN3 Input 3, Select Code 10 13. IN4 Input 4, Select Code 11 14. FSEL Selects Filter. O = High Pass, 1 = Notch 15. Out Filter Output 16. S1 Input Multiplexor Select Pin Pin Configuration The Gain control pin G is a tertiary control pin where state 0 is VSS, state 1 is GND level and state 2 is VDD. G Gain
0 OdB
The frequency control pin F0 is a CMOS level pin where high is clock to corner of 1000 to 1 and low is clock to corner of 100 to 1. FSEL IN OUT GND TYPE VSS CLK 5 VDD TYPE S1 S2 OUT CLK FSEL G IN4 VDD IN3 PD IN2 VSS IN1 F0 GND
8 Pin
16 Pin
Web Site “www.mix-sig.com” © 2002 Mixed Signal Integration 5
MSHN1/MSHN2/MSHN3/MSHN4/MSHN5/MSHN6 Selectable Highpass/Notch Filter Data Sheet SCF Section One Input MUX Filter and Clock Select (TYPE, FSEL, Fo) SCF SCF Two Section Section Three Four SCF Section Two Single Pole Lowpass Buffer Adjustable Gain IN1 IN2 IN3 IN4 G Out o Input Selection The input is selected using the Input Select Pins S1 and S2. S2 S1 Input 0 0 1 0 1 2 1 0 3 1 1 4 Digital Levels All the clock and control pins (except FSEL and G) are referenced between GND and VDD. In single supply applications, the digital levels should be CMOS levels from VSS to VDD. In dual supply systems, the digital levels should be CMOS levels from GND to VDD. Part Number Package Clock to Corner Ratio 100 100 or 1000 100 100 or 1000 1000 1000 100 100 or 1000 100 100 or 1000 1000 1000 MSHN1P 8 Pin DIP MSHN2P 16 Pin DIP MSHN3P 8 Pin DIP MSHN4P 16 Pin DIP MSHN5P 8 Pin DIP MSHN6P 8 Pin DIP MSHN1S 8 Pin SOIC MSHN2S 16 Pin SOIC MSHN3S 8 Pin SOIC MSHN4S 16 Pin SOIC MSHN5S 8 Pin SOIC MSHN6S 8 Pin SOIC Absolute Maximum Ratings Power Supply Voltage +6V Storage Temperature -60 to +150 C Operating Temperature 0 to 70 C Web Site “www.mix-sig.com” © 2002 Mixed Signal Integration 6 Mixed Signal Integration Corporation reserves the right to to change any product or specification without notice at any time. Mixed Signal Integration products are not designed or authorized for use in life support systems. Mixed Signal Integration assumes no responsibility for errors in this docu- ment.