SCMIMX6DQIEC NXP | Alldatasheet

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NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. SCM-i.MX 6Dual/6Quad Datasheet for Industrial Products 1. Introduction NXP Single Chip System Modules (SCMs) are a suite of highly integrated products in an ultra-small form factor. The first member of this portfolio, the NXP SCM-i.MX 6Dual/6Quad, drastically reduces time to market by providing a solution that minimizes design time. We’ve integrated and validated dual- and quad-core performance, the power management system, flash memory, and over a hundred passive system components all in the size of a dime. The SCM-i.MX 6Dual/6Quad is enabled with the standard i.MX 6Dual/6Quad multimedia, connectivity and security features including High Assurance Boot, cryptographic cipher engines, random number generator, and tamper detection. It is a scalable solution intended for use in a wide variety of consumer and industrial applications. The SCM-i.MX 6Dual/6Quad speeds and eases development time by addressing technology challenges such as design of DDR and power management. Our single chip module i.MX 6Dual/6Quad consists of the i.MX 6Dual/6Quad applications processor, PF0100 (PMIC) for power management, 16 MB SPI NOR, over a hundred discrete components, and is enabled for LPDDR2 via PoP assembly. NXP Semiconductor, Inc. Document Number: SCMIMX6DQIEC Data Sheet: Technical Data Rev. 0 , 01/2017

Contents

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Figure 1. Part Number Nomenclature The table below shows examples of orderable part numbers. Table 1. Part Numbers

800 MHz Industrial: -40 to

SCM-i.MX 6Dual/6Quad Datasheet for Industrial Products, Data Sheet: Technical Data , Rev. 0, 01/2017 NXP Semiconductors 3 1.2. Features 1.2.1. i.MX 6Dual/6Quad Features The i.MX 6Dual/6Quad processors are based on ARM® Cortex®-A9 MPCore platform, which has the following features:

  • ARM Cortex-A9 MPCore 4xCPU processor (with TrustZone®)
  • The core configuration is symmetric, where each core includes: — 32 Kbyte L1 Instruction Cache — 32 Kbyte L1 Data Cache — Private Timer and Watchdog — Cortex-A9 NEON MPE (Media Processing Engine) Co-processor The ARM Cortex-A9 MPCore complex includes:
  • General Interrupt Controller (GIC) with 128 interrupt support
  • Global Timer
  • Snoop Control Unit (SCU)
  • 1 MB unified I/D L2 cache, shared by two/four cores
  • Two Master AXI (64-bit) bus interfaces output of L2 cache
  • Frequency of the core (including Neon and L1 cache) as per Table 5
  • NEON MPE coprocessor — SIMD Media Processing Architecture — NEON register file with 32x64-bit general-purpose registers — NEON Integer execute pipeline (ALU, Shift, MAC) — NEON dual, single-precision floating point execute pipeline (FADD, FMUL) — NEON load/store and permute pipeline The SoC-level memory system consists of the following additional components: — Boot ROM, including HAB (96 KB) — Internal multimedia / shared, fast access RAM (OCRAM, 256 KB) — Secure/non-secure RAM (16 KB)
  • External memory interfaces: — 32-bit LPDDR2, supporting DDR interleaving mode, or fixed 2x32. — 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size, BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 40 bits.

SCM-i.MX 6Dual/6Quad Datasheet for Industrial Products, Data Sheet: Technical Data , Rev. 0, 01/2017

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— 16/32-bit NOR Flash. All EIMv2 pins are muxed on other interfaces. — 16/32-bit PSRAM, Cellular RAM Each i.MX 6Dual/6Quad processor enables the following interfaces to external devices (some of them are muxed and not available simultaneously):

  • Hard Disk Drives—SATA II, 3.0 Gbps
  • Displays—Total of five interfaces available. Total raw pixel rate of all interfaces is up to 450 Mpixels/sec, 24 bpp. Up to four interfaces may be active in parallel. — One Parallel 24-bit display port, up to 225 Mpixels/sec (for example, WUXGA at 60 Hz or dual HD1080 and WXGA at 60 Hz) — LVDS serial ports—One port up to 165 Mpixels/sec or two ports up to 85 MP/sec (for example, WUXGA at 60 Hz) each — HDMI 1.4 port — MIPI/DSI, two lanes at 1 Gbps
  • Camera sensors: — Parallel Camera port (up to 20 bit and up to 240 MHz peak) — MIPI CSI-2 serial camera port, supporting up to 1000 Mbps/lane in 1/2/3-lane mode and up to 800 Mbps/lane in 4-lane mode. The CSI-2 Receiver core can manage one clock lane and up to four data lanes. Each i.MX 6Dual/6Quad processor has four lanes.
  • Expansion cards: — Four MMC/SD/SDIO card ports all supporting: – 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR-104 mode (104 MB/s max) – 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR and DDR modes (104 MB/s max)
  • USB: — One High Speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB PHY — Three USB 2.0 (480 Mbps) hosts: – One HS host with integrated High Speed PHY – Two HS hosts with integrated HS-IC USB (High Speed Inter-Chip USB) PHY
  • Expansion PCI Express port (PCIe) v2.0 one lane: — PCI Express (Gen 2.0) dual mode complex, supporting Root complex operations and Endpoint operations. Uses x1 PHY configuration.
  • Miscellaneous IPs and interfaces: — SSI block capable of supporting audio sample frequencies up to 192 kHz stereo inputs and outputs with I2S mode

SCM-i.MX 6Dual/6Quad Datasheet for Industrial Products, Data Sheet: Technical Data , Rev. 0, 01/2017 NXP Semiconductors 5 — ESAI is capable of supporting audio sample frequencies up to 260kHz in I2S mode with 7.1 multi-channel outputs — Five UARTs, up to 4.0 Mbps each: – Providing RS232 interface – Supporting 9-bit RS485 multidrop mode – One of the five UARTs (UART1) supports 8-wire while others four supports 4- wire. This is due to the SoC IOMUX limitation, since all UART IPs are identical. — Five eCSPI (Enhanced CSPI) — Three I2C, supporting 400 kbps — Gigabit Ethernet Controller (IEEE1588 compliant), 10/100/10001 Mbps — Four Pulse Width Modulators (PWM) — System JTAG Controller (SJC) — GPIO with interrupt capabilities — 8x8 Key Pad Port (KPP) — Sony Philips Digital Interconnect Format (SPDIF), Rx and Tx — Two Controller Area Network (FlexCAN), 1 Mbps each — Two Watchdog timers (WDOG) — Audio MUX (AUDMUX) The i.MX 6Dual/6Quad processors integrate advanced power management unit and controllers:

  • Provide PMU, including LDO supplies, for on-chip resources
  • Use Temperature Sensor for monitoring the die temperature
  • Support DVFS techniques for low power modes
  • Use Software State Retention and Power Gating for ARM and MPE
  • Support various levels of system power modes
  • Use flexible clock gating control scheme The i.MX 6Dual/6Quad processors use dedicated hardware accelerators to meet the targeted multimedia performance. The use of hardware accelerators is a key factor in obtaining high performance at low power consumption numbers, while having the CPU core relatively free for performing other tasks.

1 The theoretical maximum performance of 1 Gbps ENET is limited to 470 Mbps (total for Tx and Rx)

due to internal bus throughput limitations. The actual measured performance in optimized environment is up to 400 Mbps. For details, see the ERR004512 erratum in the i.MX 6Dual/6Quad errata document IMX6DQCE.

SCM-i.MX 6Dual/6Quad Datasheet for Industrial Products, Data Sheet: Technical Data , Rev. 0, 01/2017

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The i.MX 6Dual/6Quad processors incorporate the following hardware accelerators:

  • VPU—Video Processing Unit
  • IPUv3H—Image Processing Unit version 3H (2 IPUs)
  • GPU3Dv4—3D Graphics Processing Unit (OpenGL ES 2.0) version 4
  • GPU2Dv2—2D Graphics Processing Unit (BitBlt)
  • GPUVG—OpenVG 1.1 Graphics Processing Unit
  • ASRC—Asynchronous Sample Rate Converter Security functions are enabled and accelerated by the following hardware:
  • ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.)
  • SJC—System JTAG Controller. Protecting JTAG from debug port attacks by regulating or blocking the access to the system debug features.
  • CAAM—Cryptographic Acceleration and Assurance Module, containing 16 KB secure RAM and True and Pseudo Random Number Generator (NIST certified)
  • SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock
  • CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be configured during boot and by eFUSEs and will determine the security level operation mode as well as the TZ policy.
  • A-HAB—Advanced High Assurance Boot—HABv4 with the new embedded enhancements: SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization. 1.2.2. PF0100Z Features
  • Input voltage range to PMIC: 2.8 - 4.5 V
  • Buck regulators — Four to six channel configurable – SW1A/B/C, 4.5 A (single); 0.3 to 1.875 V – SW1A/B, 2.5 A (single/dual); SW1C 2.0 A (independent); 0.3 to 1.875 V – SW2, 2.0 A; 0.4 to 3.3 V – SW3A/B, 2.5 A (single/dual); 0.4 to 3.3 V – SW3A, 1.25 A (independent); SW3B, 1.25 A (independent); 0.4 to 3.3 V – SW4, 1.0 A; 0.4 to 3.3 V – SW4, VTT mode provide DDR termination at 50% of SW3A — Dynamic voltage scaling — Modes: PWM, PFM, APS

SCM-i.MX 6Dual/6Quad Datasheet for Industrial Products, Data Sheet: Technical Data , Rev. 0, 01/2017 NXP Semiconductors 7 — Programmable output voltage — Programmable current limit — Programmable soft start — Programmable PWM switching frequency — Programmable OCP with fault interrupt

  • Boost regulator — SWBST, 5.0 to 5.15 V, 0.6 A, OTG support — Modes: PFM and Auto — OCP fault interrupt
  • LDOs — Six user programmable LDO – VGEN1, 0.80 to 1.55 V, 100 mA – VGEN2, 0.80 to 1.55 V, 250 mA – VGEN3, 1.8 to 3.3 V, 100 mA – VGEN4, 1.8 to 3.3 V, 350 mA – VGEN5, 1.8 to 3.3 V, 100 mA NOTE VGEN5 power characteristics are modified from what is displayed in Table 106 of the MMPF0100 datasheet. SCM-specific tolerances are ±5%, rather than ± 3% as presented in the table. – VGEN6, 1.8 to 3.3 V, 200 mA — Soft start — LDO/Switch supply
  • DDR memory reference voltage — VREFDDR, 0.6 to 0.9 V, 10 mA
  • 16 MHz internal master clock
  • OTP(One time programmable) memory for device configuration — User programmable start-up sequence and timing
  • Battery backed memory including coin cell charger
  • I2C interface
  • User programmable Standby, Sleep, and Off modes

SCM-i.MX 6Dual/6Quad Datasheet for Industrial Products, Data Sheet: Technical Data , Rev. 0, 01/2017

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1.3. References This document is intended to be a companion to the data sheets of the following integrated parts: a) NXP i.MX 6Dual/6Quad (Document Number: IMX6DQIEC) b) NXP MMPF0100 (Document Number: MMPF0100Z) c) SPI NOR (N25Q128A13)

The following subsection provides an architectural overview of the SCM-i.MX 6Dual/6Quad. Figure 2. SCM-i.MX 6Dual/6Quad Block Diagram

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Table 2. Modules List 6Dual/6Quad except the MLB bus is disabled and not pinned out. references to entire SCM. Refer to section 4 for electrical details. SPI NOR 16 megabytes of SPI NOR which is fully available for user programming. Discrete Components 109 passives for decoupling capacitors and reference resistors. The figure below shows critical internal connections, pull-ups and pulldowns. Figure 3. SCM-i.MX 6Dual/6Quad Critical Internal Connections DDR_VREF is connected internally to the LPDDR2 memory through one of the PoP landing pads.

  1. Electrical Characteristics

Table 3. Absolute Max Ratings Table 4 provides the FO-WLP thermal resistance data. Table 4. FO-WLP Thermal Resistance Data 2 Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3 Per JEDEC JESD51-6 with the board horizontal. the top surface of the board near the package. per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. temperatures will vary between die according to power ratios and use case.

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Table 5. Operating Ranges

  1. Power Supplies Requirements and Restrictions

SCM-specific power-up sequence requirements are shown in SCM-IMX6DQHUG. recommendations for power up. The internal PMIC simplifies power sequence design. recommendations for power down. recommendations for power supply usage. LPDDR2 usage with SW3. SW3 cannot be used to supply anything else but the LPDDR2. Table 6. OTP Fuse Map

SCM-i.MX 6Dual/6Quad Datasheet for Industrial Products, Data Sheet: Technical Data , Rev. 0, 01/2017 NXP Semiconductors 13 Registers Default Configuration Pre-programmed OTP Configuration Program code (hex) Intended Use SW1C_VOLT 1.375 1.375V 00 VDDARM SW1C_SEQ 1 2 02 SW1C CONFIG Independent, 2.0 MHz Independent, 2.0 MHz 00 SW2_VOLT 3.0V 3.15V 6F VDDHIGH_IN SW2_SEQ 2 1 01 SW2 CONFIG Single Phase, 2.0 MHz Single Phase, 2.0 MHz 01 SW3A_VOLT 1.5V 1.2V 20 DDR 1.2V SW3A_SEQ 3 4 04 SW3A CONFIG Single Phase, 2.0 MHz Single Phase, 2.0 MHz 05 SW3B_VOLT 1.5V 1.2V 20 DDR 1.2V SW3B_SEQ 3 4 04 SW3B CONFIG Single Phase, 2.0 MHz Single Phase, 2.0 MHz 01 SW4_VOLT 1.8V 1.8V 54 DDR 1.8V SW4_SEQ 3 4 04 SW4_CONFIG No VTT, 2.0MHz No VTT, 2.0 MHz 01 SWBST_VOLT - - 00 Customer SWBST_SEQ - 4 04 VSNVS_VOLT 3.0V 3.0V 06 VDD_SNVS_IN VREFDDR_SEQ 3 4 04 VGEN1_VOLT - - 00 Customer VGEN1_SEQ - - 00 VGEN2_VOLT 1.5V - 00 Customer VGEN2_SEQ 2 - 00 VGEN3_VOLT - - 00 Customer VGEN3_SEQ - - 00 VGEN4_VOLT 1.8V - 00 Customer VGEN4_SEQ 3 - 00 VGEN5_VOLT 2.5V - 00 Customer VGEN5_SEQ 3 - 00 VGEN6_VOLT 2.8V - 00 Customer VGEN6_SEQ 3 - 00 PU CONFIG1, SEQ_CLK_SPEED 1.0ms 1.0ms 01 PU CONFIG2, SWDVS_CLK 6.25 mV/us 12.5mV/us 00 PU CONFIG3, PWRON Level sensitive Level sensitive 00 PG EN RESETBMCU in Default Mode 00

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  1. Refer to application notes AN4714 (Features of Voltage Regulators in the MMPF0100) and

AN4536 (MMPF0100 OTP Programming Instructions) for further usage instructions.

  1. The OTP registers for regulators which default to (OFF) are free to be programmed according to
  2. The OTP Lock bit is not programmed from factory.
  3. NXP not responsible for device issues caused by customer fuse programming.

Refer to the i.MX 6Dual/6Quad industrial datasheet (Document Number: IMX6DQIEC). Not limited to booting from internal SPI NOR. Refer to the i.MX 6Dual/6Quad industrial datasheet (Document Number: IMX6DQIEC). Table 7. Signal List

SCM-i.MX 6Dual/6Quad Datasheet for Industrial Products, Data Sheet: Technical Data , Rev. 0, 01/2017 NXP Semiconductors 15 Ball Name Ball Power Group Comments CSI_D3M L20 NVCC_MIPI CSI_D3P L19 NVCC_MIPI CSI0_DAT10 H17 NVCC_CSI CSI0_DAT11 H18 NVCC_CSI CSI0_DAT12 J17 NVCC_CSI CSI0_DAT13 J18 NVCC_CSI CSI0_DAT14 K17 NVCC_CSI CSI0_DAT15 K16 NVCC_CSI CSI0_DAT16 N16 NVCC_CSI CSI0_DAT17 M18 NVCC_CSI CSI0_DAT18 L17 NVCC_CSI CSI0_DAT19 M17 NVCC_CSI CSI0_DAT4 E17 NVCC_CSI CSI0_DAT5 E18 NVCC_CSI CSI0_DAT6 F17 NVCC_CSI CSI0_DAT7 F18 NVCC_CSI CSI0_DAT8 G17 NVCC_CSI CSI0_DAT9 G18 NVCC_CSI CSI0_DATA_EN D18 NVCC_CSI CSI0_MCLK C18 NVCC_CSI CSI0_PIXCLK C17 NVCC_CSI CSI0_VSYNC D17 NVCC_CSI DI0_DISP_CLK A4 NVCC_LCD DI0_PIN15 A2 NVCC_LCD DI0_PIN2 B4 NVCC_LCD DI0_PIN3 B3 NVCC_LCD DI0_PIN4 A3 NVCC_LCD DISP0_DAT0 D5 NVCC_LCD DISP0_DAT1 C5 NVCC_LCD DISP0_DAT10 B7 NVCC_LCD DISP0_DAT11 A7 NVCC_LCD DISP0_DAT12 D8 NVCC_LCD DISP0_DAT13 C8 NVCC_LCD DISP0_DAT14 B8 NVCC_LCD DISP0_DAT15 A8 NVCC_LCD DISP0_DAT16 D9 NVCC_LCD DISP0_DAT17 C9 NVCC_LCD DISP0_DAT18 B9 NVCC_LCD DISP0_DAT19 A9 NVCC_LCD DISP0_DAT2 B5 NVCC_LCD

SCM-i.MX 6Dual/6Quad Datasheet for Industrial Products, Data Sheet: Technical Dat a, Rev. 0, 01/2017

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Ball Name Ball Power Group Comments DISP0_DAT20 D10 NVCC_LCD DISP0_DAT21 C10 NVCC_LCD DISP0_DAT22 B10 NVCC_LCD DISP0_DAT23 A10 NVCC_LCD DISP0_DAT3 A5 NVCC_LCD DISP0_DAT4 D6 NVCC_LCD DISP0_DAT5 C6 NVCC_LCD DISP0_DAT6 B6 NVCC_LCD DISP0_DAT7 A6 NVCC_LCD DISP0_DAT8 D7 NVCC_LCD DISP0_DAT9 C7 NVCC_LCD DSI_CLK0M P18 NVCC_MIPI DSI_CLK0P P17 NVCC_MIPI DSI_D0M R17 NVCC_MIPI DSI_D0P R18 NVCC_MIPI DSI_D1M N17 NVCC_MIPI DSI_D1P N18 NVCC_MIPI EIM_A16 H1 NVCC_EIM1 EIM_A17 H4 NVCC_EIM1 EIM_A18 J2 NVCC_EIM1 EIM_A19 J3 NVCC_EIM1 EIM_A20 J4 NVCC_EIM1 EIM_A21 K1 NVCC_EIM1 EIM_A22 K2 NVCC_EIM1 EIM_A23 K3 NVCC_EIM1 EIM_A24 K4 NVCC_EIM1 EIM_A25 R5 NVCC_EIM0 EIM_BCLK B1 NVCC_EIM2 EIM_CS0 H3 NVCC_EIM1 EIM_CS1 H2 NVCC_EIM1 EIM_D16_NOR V3 NVCC_EIM0_NOR EIM_D17_NOR U4 NVCC_EIM0_NOR EIM_D18_NOR U3 NVCC_EIM0_NOR EIM_D19 T4 NVCC_EIM0_NOR EIM_D20 T3 NVCC_EIM0_NOR EIM_D21 R4 NVCC_EIM0_NOR EIM_D22 P3 NVCC_EIM0_NOR EIM_D23 P4 NVCC_EIM0_NOR EIM_D24 T5 NVCC_EIM0_NOR EIM_D25 N3 NVCC_EIM0_NOR

SCM-i.MX 6Dual/6Quad Datasheet for Industrial Products, Data Sheet: Technical Data , Rev. 0, 01/2017 NXP Semiconductors 17 Ball Name Ball Power Group Comments EIM_D26 M4 NVCC_EIM0_NOR EIM_D27 M3 NVCC_EIM0_NOR EIM_D28 L4 NVCC_EIM0_NOR EIM_D29 L3 NVCC_EIM0_NOR EIM_D30 L2 NVCC_EIM0_NOR EIM_D31 L1 NVCC_EIM0_NOR EIM_DA0 E1 NVCC_EIM2 EIM_DA1 F4 NVCC_EIM2 EIM_DA10 D2 NVCC_EIM2 EIM_DA11 D4 NVCC_EIM2 EIM_DA12 C4 NVCC_EIM2 EIM_DA13 B2 NVCC_EIM2 EIM_DA14 C2 NVCC_EIM2 EIM_DA15 C3 NVCC_EIM2 EIM_DA2 F2 NVCC_EIM2 EIM_DA3 F3 NVCC_EIM2 EIM_DA4 E2 NVCC_EIM2 EIM_DA5 D1 NVCC_EIM2 EIM_DA6 E4 NVCC_EIM2 EIM_DA7 E3 NVCC_EIM2 EIM_DA8 C1 NVCC_EIM2 EIM_DA9 D3 NVCC_EIM2 EIM_EB0 G3 NVCC_EIM2 EIM_EB1 G2 NVCC_EIM2 EIM_EB2_NOR V4 NVCC_EIM0_NOR EIM_EB3 N4 NVCC_EIM0_NOR EIM_LBA F1 NVCC_EIM1 EIM_OE G1 NVCC_EIM1 EIM_RW G4 NVCC_EIM1 EIM_WAIT F5 NVCC_EIM2 ENET_CRS_DV D11 NVCC_ENET ENET_MDC D12 NVCC_ENET ENET_MDIO C12 NVCC_ENET ENET_REF_CLK C13 NVCC_ENET ENET_RX_ER C11 NVCC_ENET ENET_RXD0 A11 NVCC_ENET ENET_RXD1 B11 NVCC_ENET ENET_TX_EN D13 NVCC_ENET ENET_TXD0 A12 NVCC_ENET ENET_TXD1 B12 NVCC_ENET

SCM-i.MX 6Dual/6Quad Datasheet for Industrial Products, Data Sheet: Technical Data , Rev. 0, 01/2017

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Ball Name Ball Power Group Comments GPIO_0 E16 NVCC_GPIO GPIO_1 E15 NVCC_GPIO GPIO_16 M15 NVCC_GPIO GPIO_17 R16 NVCC_GPIO GPIO_18_PMIC_INTB AD12 NVCC_GPIO GPIO_19 P16 NVCC_GPIO GPIO_2 D16 NVCC_GPIO GPIO_3 A19 NVCC_GPIO GPIO_4 F16 NVCC_GPIO GPIO_5 G16 NVCC_GPIO GPIO_6 H16 NVCC_GPIO GPIO_7 J16 NVCC_GPIO GPIO_8 L16 NVCC_GPIO GPIO_9 M16 NVCC_GPIO HDMI_CLKM K19 HDMI_VPH HDMI_CLKP K20 HDMI_VPH HDMI_D0M J19 HDMI_VPH HDMI_D0P J20 HDMI_VPH HDMI_D1M G19 HDMI_VPH HDMI_D1P G20 HDMI_VPH HDMI_D2M F19 HDMI_VPH HDMI_D2P F20 HDMI_VPH HDMI_HPD K18 HDMI_VPH JTAG_MOD U19 NVCC_JTAG JTAG_TCK T17 NVCC_JTAG JTAG_TDI V18 NVCC_JTAG JTAG_TDO V17 NVCC_JTAG JTAG_TMS T18 NVCC_JTAG JTAG_TRST_B T16 NVCC_JTAG KEY_COL0 E12 NVCC_GPIO KEY_COL1 E13 NVCC_GPIO KEY_COL2 C14 NVCC_GPIO KEY_COL3_PMIC_SCL W13 NVCC_GPIO KEY_COL4 C15 NVCC_GPIO KEY_ROW0 E11 NVCC_GPIO KEY_ROW1 F14 NVCC_GPIO KEY_ROW2 D14 NVCC_GPIO KEY_ROW3_PMIC_SDA W12 NVCC_GPIO KEY_ROW4 D15 NVCC_GPIO LVDS0_CLK_N B19 NVCC_LVDS_2P5

SCM-i.MX 6Dual/6Quad Datasheet for Industrial Products, Data Sheet: Technical Data , Rev. 0, 01/2017 NXP Semiconductors 19 Ball Name Ball Power Group Comments LVDS0_CLK_P B20 NVCC_LVDS_2P5 LVDS0_TX0_N E19 NVCC_LVDS_2P5 LVDS0_TX0_P E20 NVCC_LVDS_2P5 LVDS0_TX1_N D19 NVCC_LVDS_2P5 LVDS0_TX1_P D20 NVCC_LVDS_2P5 LVDS0_TX2_N C19 NVCC_LVDS_2P5 LVDS0_TX2_P C20 NVCC_LVDS_2P5 LVDS0_TX3_N A18 NVCC_LVDS_2P5 LVDS0_TX3_P B18 NVCC_LVDS_2P5 LVDS1_CLK_N A16 NVCC_LVDS_2P5 LVDS1_CLK_P B16 NVCC_LVDS_2P5 LVDS1_TX0_N A17 NVCC_LVDS_2P5 LVDS1_TX0_P B17 NVCC_LVDS_2P5 LVDS1_TX1_N B15 NVCC_LVDS_2P5 LVDS1_TX1_P A15 NVCC_LVDS_2P5 LVDS1_TX2_N B14 NVCC_LVDS_2P5 LVDS1_TX2_P A14 NVCC_LVDS_2P5 LVDS1_TX3_N A13 NVCC_LVDS_2P5 LVDS1_TX3_P B13 NVCC_LVDS_2P5 NANDF_ALE U15 NVCC_NANDF NANDF_CLE T15 NVCC_NANDF NANDF_CS0 T14 NVCC_NANDF NANDF_CS1 Y16 NVCC_NANDF NANDF_CS2 W16 NVCC_NANDF NANDF_CS3 U16 NVCC_NANDF NANDF_D0 R13 NVCC_NANDF NANDF_D1 T13 NVCC_NANDF NANDF_D2 R12 NVCC_NANDF NANDF_D3 T12 NVCC_NANDF NANDF_D4 R11 NVCC_NANDF NANDF_D5 T11 NVCC_NANDF NANDF_D6 R10 NVCC_NANDF NANDF_D7 T10 NVCC_NANDF NANDF_RB0 U14 NVCC_NANDF NANDF_WP_B V16 NVCC_NANDF NOR_HOLD_B V13 NVCC_EIM0 NOR_W_B AA13 NVCC_EIM0 ONOFF AD13 VDD_SNVS_IN PCIE_RXM Y20 PCIE_VPH PCIE_RXP Y19 PCIE_VPH

SCM-i.MX 6Dual/6Quad Datasheet for Industrial Products, Data Sheet: Technical Data , Rev. 0, 01/2017

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Ball Name Ball Power Group Comments PCIE_TXM AA19 PCIE_VPH PCIE_TXP AA20 PCIE_VPH RGMII_RD0 N1 NVCC_RGMII RGMII_RD1 N2 NVCC_RGMII RGMII_RD2 M1 NVCC_RGMII RGMII_RD3 M2 NVCC_RGMII RGMII_RX_CTL P2 NVCC_RGMII RGMII_RXC P1 NVCC_RGMII RGMII_TD0 T1 NVCC_RGMII RGMII_TD1 T2 NVCC_RGMII RGMII_TD2 R1 NVCC_RGMII RGMII_TD3 R2 NVCC_RGMII RGMII_TX_CTL U2 NVCC_RGMII RGMII_TXC U1 NVCC_RGMII RTC_XTALI V19 VDD_SNVS_CAP RTC_XTALO V20 VDD_SNVS_CAP SATA_RXM AE17 SATA_VPH SATA_RXP AD17 SATA_VPH SATA_TXM AE18 SATA_VPH SATA_TXP AD18 SATA_VPH SD1_CLK AE14 NVCC_SD1 SD1_CMD AD14 NVCC_SD1 SD1_DAT0 AE16 NVCC_SD1 SD1_DAT1 AD16 NVCC_SD1 SD1_DAT2 AE15 NVCC_SD1 SD1_DAT3 AD15 NVCC_SD1 SD2_CLK AB13 NVCC_SD2 SD2_CMD AC13 NVCC_SD2 SD2_DAT0 AB14 NVCC_SD2 SD2_DAT1 AB12 NVCC_SD2 SD2_DAT2 AC12 NVCC_SD2 SD2_DAT3 AC14 NVCC_SD2 SD3_CLK AC17 NVCC_SD3 SD3_CMD AC16 NVCC_SD3 SD3_DAT0 AC18 NVCC_SD3 SD3_DAT1 AB17 NVCC_SD3 SD3_DAT2 AB18 NVCC_SD3 SD3_DAT3 AA17 NVCC_SD3 SD3_DAT4 Y17 NVCC_SD3 SD3_DAT5 Y18 NVCC_SD3

Table 8. Signal Name differences from i.MX6 Dual

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– – ZQPAD Tied to ground through 240Ohm resistor. Table 9. Supply Signal List for i.MX6 Dual GPANAIO U12 Test signal. Should be unconnected.

SCM-i.MX 6Dual/6Quad Datasheet for Industrial Products, Data Sheet: Technical Data , Rev. 0, 01/2017 NXP Semiconductors 23 Supply Name Balls Remark AE20, AC8, AC9, AE1, T6, T7, T8, T9, U6, U7, U8 HDMI_DDCCEC H19 HDMI_VP L14 HDMI_VPH K14 LICELL Y11 LICELL output from PMIC NVCC_CSI H15 NVCC_EIM0_NOR L5 EIM0 domain shared with the SPI NOR. NVCC_EIM1 K5 NVCC_EIM2 J5 NVCC_ENET G5 NVCC_GPIO G15 NVCC_JTAG P15 NVCC_LCD H5 NVCC_LVDS2P5 F15 NVCC_MIPI M14 NVCC_NANDF P10 NVCC_PLL_OUT R14 NVCC_RGMII M5 NVCC_SD1 M6 NVCC_SD2 N10 NVCC_SD3 P11 PCIE_VP N15 PCIE_VPH N12 PCIE_VPTX N14 PMIC_VCOREREF AD9 PMIC V_core_ref PMIC_VDDOTP Y9 PMIC VDD OTP PMIC_VIN AC10, AE11, AE2, AE3, V7, V8, AC11, AC2, AC3, AD10, AD11, AD2, AD3, AE10 Main system supply. SATA_VP N13 SATA_VPH N11 SW1ABFB AE9 SW1ABLX AD7, AD8, AE6, AE7, AE8 SW1CFB AE5 SW1CLX AD4, AD5, AD6, AE4 SW2LX W1, W2, W3, Y1, Y2, Y3 SW3ABLX W6, W7, Y6, Y7 SW4LX AA1, AA2, AB2 SWBSTFB Y10 SWBSTIN AB10 SWBSTLX AA10, AA11

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Table 10. Ball Map

SCM-i.MX 6Dual/6Quad Datasheet for Industrial Products, Data Sheet: Technical Data , Rev. 0, 01/2017 NXP Semiconductors 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 E EIM_DA0 EIM_DA4 EIM_DA7 EIM_DA6 DDR_1V2 GND GND GND DDR_1V2 GND KEY_ROW0 KEY_COL0 KEY_COL1 DDR_1V2 GPIO_1 GPIO_0 CSI0_DAT4 CSI0_DAT5 LVDS0_TX0_ N LVDS0_TX0_P F EIM_LBA EIM_DA2 EIM_DA3 EIM_DA1 EIM_WAIT GND GND GND GND GND GND VDDSOC_CAP VDDSOC_CAP KEY_ROW1 NVCC_LVDS2 GPIO_4 CSI0_DAT6 CSI0_DAT7 HDMI_D2M HDMI_D2P G EIM_OE EIM_EB1 EIM_EB0 EIM_RW NVCC_ENET GND GND VDDSOC_IN GND GND GND GND VDDSOC_CAP GND NVCC_GPIO GPIO_5 CSI0_DAT8 CSI0_DAT9 HDMI_D1M HDMI_D1P H EIM_A16 EIM_CS1 EIM_CS0 EIM_A17 NVCC_LCD VDDSOC_IN VDDSOC_IN VDDSOC_IN GND GND GND GND VDDSOC_CAP GND NVCC_CSI GPIO_6 CSI0_DAT10 CSI0_DAT11 HDMI_DDCC EC GND J GND EIM_A18 EIM_A19 EIM_A20 NVCC_EIM2 VDDPU_CAP GND GND GND GND GND GND GND GND VDDARM23_I N GPIO_7 CSI0_DAT12 CSI0_DAT13 HDMI_D0M HDMI_D0P K EIM_A21 EIM_A22 EIM_A23 EIM_A24 NVCC_EIM1 VDDPU_CAP GND GND GND GND GND GND VDDARM23_ CAP HDMI_VPH VDDARM23_I N CSI0_DAT15 CSI0_DAT14 HDMI_HPD HDMI_CLKM HDMI_CLKP L EIM_D31 EIM_D30 EIM_D29 EIM_D28 NVCC_EIM0_ NOR VDDPU_CAP GND GND GND GND GND GND VDDARM23_ CAP HDMI_VP VDDARM23_I N GPIO_8 CSI0_DAT18 GND CSI_D3P CSI_D3M M RGMII_RD2 RGMII_RD3 EIM_D27 EIM_D26 NVCC_RGMII NVCC_SD1 VDDARM_IN VDDARM_IN VDDARM_IN VDDARM_CA P VDDARM_CA P VDDARM_CA P VDDARM23_ CAP NVCC_MIPI GPIO_16 GPIO_9 CSI0_DAT19 CSI0_DAT17 CSI_D2M CSI_D2P N RGMII_RD0 RGMII_RD1 EIM_D25 EIM_EB3 SD4_DAT6 SD4_DAT4 SD4_DAT2 SD4_DAT0 SD4_CMD NVCC_SD2 SATA_VPH PCIE_VPH SATA_VP PCIE_VPTX PCIE_VP CSI0_DAT16 DSI_D1M DSI_D1P CSI_CLK0P CSI_CLK0M P RGMII_RXC RGMII_RX_CT L EIM_D22 EIM_D23 SD4_DAT7 SD4_DAT5 SD4_DAT3 SD4_DAT1 SD4_CLK NVCC_NAND F NVCC_SD3 VDD_SNVS_C AP VDDUSB_CAP VDDHIGH_CA P NVCC_JTAG GPIO_19 DSI_CLK0P DSI_CLK0M CSI_D1M CSI_D1P R RGMII_TD2 RGMII_TD3 GND EIM_D21 EIM_A25 GND GND GND TEST_MODE NANDF_D6 NANDF_D4 NANDF_D2 NANDF_D0 NVCC_PLL_O UT VDDHIGH_IN GPIO_17 DSI_D0M DSI_D0P CSI_D0P CSI_D0M T RGMII_TD0 RGMII_TD1 EIM_D20 EIM_D19 EIM_D24 GND GND GND GND NANDF_D7 NANDF_D5 NANDF_D3 NANDF_D1 NANDF_CS0 NANDF_CLE JTAG_TRST_B JTAG_TCK JTAG_TMS XTALI XTALO U RGMII_TXC RGMII_TX_CT L EIM_D18_NO R EIM_D17_NO R VGEN3 GND GND GND GND VGEN6 BOOT_MODE GPANAIO TAMPER NANDF_RB0 NANDF_ALE NANDF_CS3 CLK1_P CLK1_N JTAG_MOD GND

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Figure 4. SCM-i.MX 6Dual/6Quad without Memory

SCM-i.MX 6Dual/6Quad Datasheet for Industrial Products, Data Sheet: Technical Data , Rev. 0, 01/2017 NXP Semiconductors 27

SCM-i.MX 6Dual/6Quad Datasheet for Industrial Products, Data Sheet: Technical Data , Rev. 0, 01/2017

28 NXP Semiconductors

SCM-i.MX 6Dual/6Quad Datasheet for Industrial Products, Data Sheet: Technical Data, Rev. 0, 01/2017 NXP Semiconductors 29

SCM-i.MX 6Dual/6Quad Datasheet for Industrial Products, Data Sheet: Technical Data , Rev. 0, 01/2017

30 NXP Semiconductors

  1. Revision History Revision Date Change description 0 01/2017 Technical Data Sheet

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