MSC8254SVT800B

MSC8254 FREESCALE | Alldatasheet

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Data Sheet: Product Preview Document Number: MSC8254 Rev. 2, 12/2010 © 2008, 2010 Freescale Semiconductor, Inc. This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. MSC8254 FC-PBGA–783 29 mm × 29 mm

• Four StarCore SC3850 DSP subsystems, each with an SC3850 DSP core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, unified 512 Kbyte L2 cache configurable as M2 memory in

64 Kbyte increments, memory management unit (MMU),

extended programmable interrupt controller (EPIC), two general-purpose 32-bit timers, debug and profiling support, low-power Wait, Stop, and power-down processing modes, and ECC/EDC support.  Chip-level arbitration and switching system (CLASS) that provides full fabric non-blocking arbitration between the cores and other initiators and the M2 memory, shared M3 memory, DDR SRAM controllers, device configuration control and status registers, and other targets.  1056 Kbyte 128-bit wide M3 memory, 1024 Kbytes of which can be turned off to save power.  96 Kbyte boot ROM.  Three input clocks (one global and two differential).  Five PLLs (three global and two Serial RapidIO PLLs).  Two DDR controllers with up to a 400 MHz clock (800 MHz data rate), 64/32 bit data bus, supporting up to a total 2 Gbyte in up to four banks (two per controller) and support for DDR2 and DDR3.  DMA controller with 32 unidirectional channels supporting 16 memory-to-memory channels with up to 1024 buffer descriptors per channel, and programmable priority, buffer, and multiplexing configuration. It is optimized for DDR SDRAM.  Up to four independent TDM modules with programmable word size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion, up to 62.5 Mbps data rate for each TDM link, and with glueless interface to E1 or T1 framers that can interface with H-MVIP/H.110 devices, TSI, and codecs such as AC-97.  High-speed serial interface that supports two Serial RapidIO interfaces, one PCI Express interface, and two SGMII interfaces (multiplexed). The Serial RapidIO interfaces support 1x/4x operation up to 3.125 Gbaud with a single messaging unit and two DMA units. The PCI Express controller supports 32- and 64-bit addressing, x4, x2, and x1 link.  QUICC Engine technology subsystem with dual RISC processors, 48 Kbyte multi-master RAM, 48 Kbyte instruction RAM, supporting two communication controllers for two Gigabit Ethernet interfaces (RGMII or SGMII), to offload scheduling tasks from the DSP cores, and an SPI.  I/O Interrupt Concentrator consolidates all chip maskable interrupt and non-maskable interrupt sources and routes then to INT_OUT , NMI_OUT, and the cores.  UART that permits full-duplex operation with a bit rate of up to 6.25 Mbps.  Two general-purpose 32-bit timers for RTOS support per SC3850 core, four timer modules with four 16-bit fully programmable timers, and eight software watchdog timers (SWT).  Eight programmable hardware semaphores.  Up to 32 virtual interrupts and a virtual NMI asserted by simple write access. I 2C interface.  Up to 32 GPIO ports, sixteen of which can be configured as external interrupts.  Boot interface options include Ethernet, Serial RapidIO interface, I2C, and SPI.  Supports standard JTAG interface  Low power CMOS design, with low-power standby and power-down modes, and optimized power-management circuitry.  45 nm SOI CMOS technology. Quad-Core Digital Signal Processor

3.3 Clock and Timing Signal Board Layout Considerations 57

3.6 Guide to Selecting Connections for Remote Power

Figure 4. Differential Voltage Definitions for Transmitter or Figure 6. SerDes Transmitter and Re ceiver Reference Circuits . 31 Figure 7. Differential Reference Clock Input DC Requirements Figure 8. Differential Reference Clock Input DC Requirements Figure 9. Single-Ended Reference Clock Input DC Requirements 32

Figure 1. MSC8254 Block Diagram Figure 2. StarCore SC3850 DSP Subsystem Block Diagram Note: The arrow direction indicates master or slave.

4 TDMs

1056 Kbyte

512 Kbyte

32 Kbyte 32 Kbyte

32 Kbyte Address

32 Kbyte

512 Kbyte L2 Cache / M2 Memory

1 Pin Assignment

1.1 FC-PBGA Ball Layout Diagram

The top view of the FC-PBGA package is shown in Figure 3 with the ball location index numbers. Figure 3. MSC8254 FC-PBGA Package, Top View

1.2 Signal List By Ball Location

recommended, and so on) and not the power supplies themselves. Table 1. Signal List by Ball Number

Table 1. Signal List by Ball Number (continued)

unconnected (Reserved), pulled dow n (VSS), or pulled up (VDD).

1. Signal function during power-on reset is determined by the RCW source type.
2. Selection of TDM versus RGMII functionality is determined by the RCW bit values.
3. Selection of RapidIO, SGMII, and PCI Express f unctionality is determined by the RCW bit values.
4. Selection of the GPIO function and other functions is done by GPIO register setup. For configuration details, see the GPIO

chapter in the MSC8254 Reference Manual.

1. Internal 20 KΩ pull-up resistor.
2. For signals with GPIO functionality, the open-drain and internal 20 K Ω pull-up resistor can be configured by GPIO register

programming. See the GPIO chapter of the MSC8254 Reference Manual for configuration details.

1. Connect to power supply via external filter. See Section 3.2, PLL Power Supply Design Considerations for details.
2. Pin types are: Ground = all VSS connections; Power = all VDD connections; I = Input; O = Output; I/O = Input/Output; NC =

Electrical Characteristics

MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 23

2 Electrical Characteristics

This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications. For additional information, see the MSC8254 Reference Manual.

2.1 Maximum Ratings

In calculating timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. Table 2 describes the maximum electrical ratings for the MSC8254. Table 2. Absolute Maximum Ratings Notes: 1. Functional operating conditions are given in Table 3.

1. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond

the listed limits may affect device reliability or cause permanent damage.

1. PLL supply voltage is specified at input of the filter and not at pin of the MSC8254 (see Figure 37 and Figure 38)

MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2

2.2 Recommended Operating Conditions

Table 3 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed. Table 3. Recommended Operating Conditions Notes: 1. The typical power values are derived for a device running under the following conditions.  Four cores running at 1 GHz, Core voltage at 1V, 75% utilization (50% control/50% DSP).  A single 64 bit DDR3 running at 800 MHz, 50% utilization (50% reads/50% writes). disabled, 1 RGMII at 1 Gbps 50% loading.  A junction temperature of 60°C.

1. The typical power values are derived for a device running under the following conditions.

 Four cores running at 800 MHz, Core voltage at 1V, 75% utilization (50% control/50% DSP).  A single 64 bit DDR3 running at 800 MHz, 50% utilization (50% reads/50% writes). disabled, 1 RGMII at 1 Gbps 50% loading.  A junction temperature of 60°C.

MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 25

2.3 Thermal Characteristics

Table 4 describes thermal characteristics of the MSC8254 for the FC-PBGA packages.

2.4 CLKIN Requirements

Table 5 summarizes the required characteristics for the CLKIN signal. Table 4. Thermal Characteristics for the MSC8254

1. Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESDC51-6. Thermal test board meets JEDEC

specification for the specified package.

1. Junction-to-board thermal resistance determined per JEDEC JESD 51-8. Thermal test board meets JEDEC specification for
2. Junction-to-case at the top of the package determined using MIL- STD-883 Method 1012.1. The cold plate temperature is used

Table 5. CLKIN Requirements Notes: 1. For clock frequencies, see the Clock chapter in the MSC8254 Reference Manual.

1. Measured at the rising edge and/or the falling edge at V DDIO/2.
2. Slew rate as measured from ±20% to 80% of voltage swing at clock input.
3. Phase noise is calculated as FFT of TIE jitter.

MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2

2.5 DC Electrical Characteristics

This section describes the DC electrical characteristics for the MSC8254.

2.5.1 DDR SDRAM DC Electr ical Characteristics

This section describes the DC electrical specifications for the DDR SDRAM interface of the MSC8254. Note: DDR2 SDRAM uses VDDDDR(typ) = 1.8 V and DDR3 SDRAM uses VDDDDR(typ) = 1.5 V. 2.5.1.1 DDR2 (1.8 V) SDRAM DC Electrical Characteristics Table 6 provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR2 SDRAM. Note: At recommended operating conditions (see Table 3) with VDDDDR =1 . 8V . Table 6. DDR2 SDRAM Interface DC Electrical Characteristics use the same or different sources.

1. MVREF is expected to be equal to 0.5 × VDDDDR and to track VDDDDR DC variations as measured at the receiver. Peak-to-peak

noise on MVREF may not exceed ±2% of the DC value.

1. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal
2. The voltage regulator for MVREF must be able to supply up to 300 μA.
3. Input capacitance load for DQ, DQS, and DQS signals are available in the IBIS models.
4. Output leakage is measured with all outputs are disabled, 0 V ≤ VOUT ≤ VDDDDR.
5. Refer to the IBIS model for the complete output IV curve characteristics.

MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 27 2.5.1.2 DDR3 (1.5V) SDRAM DC Electrical Characteristics Table 7 provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3 SDRAM. Note: At recommended operating conditions (see Table 3) with VDDDDR =1 . 5V .

2.5.1.3 DDR2/DDR3 SDRAM Capacitance

Table 8 provides the DDR controller interface capacitance for DDR2 and DDR3 memory. Note: At recommended operating conditions (see Table 3) with VDDDDR = 1.8 V for DDR2 memory or VDDDDR =1 . 5V f o r DDR3 memory. Table 7. DDR3 SDRAM Interface DC Electrical Characteristics

1. MVREF is expected to be equal to 0.5 × VDDDDR, and to track VDDDDR DC variations as measured at the receiver.

Peak-to-peak noise on MVREF may not exceed ±1% of the DC value.

1. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
2. The voltage regulator for MVREF must be able to supply up to 250 μA.
3. Input capacitance load for DQ, DQS, and DQS signals are available in the IBIS models.
4. Output leakage is measured with all outputs are disabled, 0 V ≤ VOUT ≤ VDDDDR.

Table 8. DDR2/DDR3 SDRAM Capacitance VOUT (peak-to-peak) = 0.2 V.

1. This parameter is sampled. VDDDDR = 1.5 V ± 0.075 V (for DDR3), f = 1 MHz, T A = 25°C, VOUT = VDDDDR/2,

VOUT (peak-to-peak) = 0.175 V.

MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2

2.5.1.4 DDR Reference Current Draw

Table 9 lists the current draw characteristics for MVREF. Note: Values when used at recommended operating conditions (see Table 3).

2.5.2 High-Speed Serial Interface (HSSI) DC Electrical Characteristics

The MSC8254 features an HSSI that includes two 4-channel SerDes ports used for high-speed serial interface applications (PCI Express, Serial RapidIO interfaces, and SGMII). This section and its subsections describe the common portion of the SerDes DC, including the DC requirements for the SerDes reference clocks and the SerDes data lane transmitter (Tx) and receiver (Rx) reference circuits. The data lane circuit specifications are specific for each supported interface, and they have individual subsections by protocol. The selection of individual data channel functionality is done via the Reset Configuration Word High Register (RCWHR) SerDes Protocol selection fields (S1P and S2P). Specific AC electrical characteristics are defined in Section 2.6.2, “HSSI AC Timing Specifications.”

2.5.2.1 Signal Term Definitions

The SerDes interface uses differential signaling to transfer data across the serial link. This section defines terms used in the description and specification of differential signals. Figure 4 shows how the signals are defined. For illustration purposes only, one SerDes lane is used in the description. Figure 4 shows the waveform for either a transmitter output (SR[1–2]_TX and SR[1–2]_TX) or a receiver input (SR[1–2]_RX and SR[1–2]_RX). Each signal swings between A volts and B volts where A>B . Table 9. Current Draw Characteristics for MVREF Figure 4. Differential Voltage Definitions for Transmitter or Receiver

MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 29 Using this waveform, the definitions are listed in Table 10. To simplify the illustration, the definitions assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling environment. To illustrate these definitions using real values, consider the example of a current mode logic (CML) transmitter that has a common mode voltage of 2.25 V and outputs, TD and TD. If these outputs have a swing from 2.0 V to 2.5 V , the peak-to-peak voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred to as the single-ended swing for each signal. Because the differential signaling environment is fully symmetrical in this example, the transmitter output differential swing (VOD) has the same amplitude as each signal single-ended swing. The differential output signal ranges between 500 mV and –500 mV . In other words, VOD is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage (VDIFFp) is 500 mV . The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p. Table 10. Differential Signal Definitions signal wire’s single-ended swing. defined as the differential peak voltage, V DIFFp = |A – B| volts. waveform is not referenced to ground. Refer to Figure 16 as an example for differential waveform.

MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2

2.5.2.2 SerDes Reference Clock Receiver Characteristics

The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding SerDes lanes. The SerDes reference clock inputs are SR1_REF_CLK/SR1_REF_CLK or SR2_REF_CLK/SR2_REF_CLK. Figure 5 shows a receiver reference diagram of the SerDes reference clocks. The characteristics of the clock signals are as follows:  The supply voltage requirements for VDDSXC are as specified in Table 3.  The SerDes reference clock receiver reference circuit structure is as follows: —T h e SR[1–2]_REF_CLK and SR[1–2]_REF_CLK are internally AC-coupled differential inputs as shown in Figure 5. Each differential clock input (SR[1–2]_REF_CLK or SR[1–2]_REF_CLK) has on-chip 50-Ω termination to GNDSXC followed by on-chip AC-coupling. — The external reference clock driver must be able to drive this termination. single-ended mode descriptions below for detailed requirements.  The maximum average current requirement also determines the common mode voltage range.  The input amplitude requirement is described in detail in the following sections. Figure 5. Receiver of SerDes Reference Clocks

MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 31

2.5.2.3 SerDes Transmitter and Receiver Reference Circuits

Figure 6 shows the reference circuits for SerDes data lane transmitter and receiver.

2.5.3 DC-Level Requirements for SerDes Interfaces

The following subsections define the DC-level requirements for the SerDes reference clocks, the PCI Express data lines, the Serial RapidIO data lines, and the SGMII data lines.

2.5.3.1 DC-Level Requirements for SerDes Reference Clocks

The DC-level requirement for the SerDes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs, as described below:  Differential Mode — The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-peak (or between 200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have a single-ended swing of less than 800 mV and greater than 200 mV . This requirement is the same for both external DC-coupled or AC-coupled connection. — For an external DC-coupled connection, the maximum average current requirements sets the requirement for average voltage (common mode voltage) as between 100 mV and 400 mV . Figure 7 shows the SerDes reference clock input requirement for DC-coupled connection scheme. Figure 6. SerDes Transmitter and Receiver Reference Circuits Figure 7. Differential Reference Clock Input DC Requirements (External DC-Coupled)

MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 — For an external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Because the external AC-coupling capacitor blocks the DC-level, the clock driver and the SerDes reference clock receiver operate in different command mode voltages. The SerDes reference clock receiver in this connection scheme has its common mode voltage set to GNDSXC. Each signal wire of the differential inputs is allowed to swing below and above the command mode voltage GNDSXC. Figure 8 shows the SerDes reference clock input requirement for AC-coupled connection scheme.  Single-Ended Mode — The reference clock can also be single-ended. The SR[1–2]_REF_CLK input amplitude (single-ended swing) must be between 400 mV and 800 mV peak-peak (from VMIN to VMAX) with SR[1–2]_REF_CLK either left unconnected or tied to ground. — The SR[1–2]_REF_CLK input average voltage must be between 200 and 400 mV . Figure 9 shows the SerDes reference clock input requirement for single-ended signaling mode. — To meet the input amplitude requirement, the reference clock inputs may need to be DC- or AC-coupled externally. For the best noise performance, the reference of the clock could be DC- or AC-coupled into the unused phase (SR[1–2]_REF_CLK) through the same source impedance as the clock input (SR[1–2]_REF_CLK) in use.

2.5.3.2 DC-Level Requirements for PCI Express Configurations

The DC-level requirements for PCI Express implementations have separate requirements for the Tx and Rx lines. The MSC8254 supports a 2.5 Gbps PCI Express interface defined by the PCI Express Base Specification, Revision 1.0a. The transmitter specifications are defined in Table 11 and the receiver specifications are defined in Table 12. Figure 8. Differential Reference Clock Input DC Requirements (External AC-Coupled) Figure 9. Single-Ended Reference Clock Input DC Requirements

MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 33 Note: Specifications are valid at the recommended operating conditions listed in Table 3.

2.5.3.3 DC-Level Requirements for Serial RapidIO Configurations

This sections provided various DC-level requirements for Serial RapidIO Configurations. Note: Specifications are valid at the recommended operating conditions listed in Table 3. Table 11. PCI Express (2.5 Gbps) Differential Transmitter (Tx) Output DC Specifications Notes: 1. VTX-DIFFp-p = 2 × |VTX-D+ – VTX-D-| Measured at the package pins with a test load of 50 Ω to GND on each pin.

1. Ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by the V TX-DIFFp-p of the first bit after a

transition. Measured at the package pins with a test load of 50 Ω to GND on each pin.

1. Tx DC differential mode low impedance
2. Required Tx D+ as well as D– DC Impedance during all states

Table 12. PCI Express (2.5 Gbps) Differential Receiver (Rx) Input DC Specifications Notes: 1. VRX-DIFFp-p = 2 × |VRX-D+ – VRX-D-| Measured at the package pins with a test load of 50 Ω to GND on each pin.

1. Rx DC differential mode impedance. Impedance during all LTSSM states. When transitioning from a fundamental reset to

unconfigured lanes of a port.

1. Required Rx D+ as well as D– DC Impedance (50 ±20% toler ance). Measured at the package pins with a test load of 50 Ω to
2. Required Rx D+ as well as D– DC Impedance when the receiver terminations do not have power. The Rx DC common mode
3. VRX-IDLE-DET-DIFFp-p = 2 × |VRX-D+ –V RX-D–|. Measured at the package pins of the receiver

Table 13. Serial RapidIO Transmitter DC Specifications Note: Voltage relative to COMMON of either signal comprising a differential pair.

MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2

2.5.3.4 DC-Level Requirements for SGMII Configurations

Note: Specifications are valid at the recommended operating conditions listed in Table 3 Table 15 describes the SGMII SerDes transmitter AC-coupled DC electrical characteristics. Transmitter DC characteristics are measured at the transmitter outputs (SR[1–2]_TX[n] and SR[1–2]_TX[n]) as shown in Figure 10. Table 14. Serial RapidIO Receiver DC Specifications Notes: 1. Measured at receiver. Table 15. SGMII DC Transmitter Electrical Characteristics5 Notes: 1. Input must be externally AC-coupled.

1. VRX_DIFFp-p is also referred to as peak-to-peak input differential voltage.
2. The concept of this parameter is equivalent to the Electrical Idle Detect Threshold parameter in the PCI Express interface.
3. The LSTS shown in the table refers to the LSTS AB or LSTSEF bit fields of the SerDes Control Register.
4. The supply voltage is 1.0 V.

Figure 10. SGMII Transmitter DC Measurement Circuit

MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 35 Table 16 describes the SGMII SerDes receiver AC-coupled DC electrical characteristics. Table 16. SGMII DC Receiver Electrical Characteristics5 Notes: 1. Input must be externally AC-coupled.

1. VRX_DIFFp-p is also referred to as peak-to-peak input differential voltage.
2. The concept of this parameter is equivalent to the Electrical Idle Detect Threshold parameter in the PCI Express interface.

Refer to the PCI Express Differential Receiver (RX) Input Specifications section of the PCI Express Specification document.

1. The values for SGMII1 and SGMII2 are selected in the SRDS control registers.
2. The supply voltage is 1.0 V.

MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2

2.5.4 RGMII and Other Interface DC Electrical Characteristics

Table 17 describes the DC electrical characteristics for the following interfaces: R G M I I E t h e r n e t  SPI T D M G P I O  UART T I M E R E E  Interrupts (IRQn , NMI_OUT, INT_OUT)  Clock and resets (CLKIN, PORESET , HRESET, SRESET)  DMA External Request J T A G s i g n a l s Table 17. 2.5 V I/O DC Electrical Characteristics Notes: 1. The min VIL and max VIH values are based on the respective min and max V IN values listed in Table 3.

1. The symbol VIN represents the input voltage of the supply. It is referenced in Table 3.

MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 37

2.6 AC Timing Characteristics

This section describes the AC timing characteristics for the MSC8254.

2.6.1 DDR SDRAM AC Timing Specifications

This section describes the AC electrical characteristics for the DDR SDRAM interface.

2.6.1.1 DDR SDRAM Input AC Timing Specifications

Table 18 provides the input AC timing specifications for the DDR SDRAM when VDDDDR (typ) = 1.8 V . Table 19 provides the input AC timing specifications for the DDR SDRAM when VDDDDR (typ) = 1.5 V . Table 20 provides the input AC timing specifications for the DDR SDRAM interface. Table 18. DDR2 SDRAM Input AC Timing Specifications for 1.8 V Interface Note: At recommended operating conditions with V DDDDR of 1.8 ± 5%. Table 19. DDR3 SDRAM Input AC Timing Specifications for 1.5 V Interface Note: At recommended operating conditions with V DDDDR of 1.5 ± 5%. Table 20. DDR SDRAM Input AC Timing Specifications captured with MDQS[n]. Subtract this value from the total timing budget.

1. At recommended operating conditions with V DDDDR (1.8 V or 1.5 V) ± 5%
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t DISKEW.This can be

MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Figure 11 shows the DDR2 and DDR3 SDRAM interface input timing diagram.

2.6.1.2 DDR SDRAM Output AC Timing Specifications

Table 21 provides the output AC timing specifications for the DDR SDRAM interface. Figure 11. DDR2 and DDR3 SDRAM Interface Input Timing Diagram Table 21. DDR SDRAM Output AC Timing Specifications

MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Figure 13 shows the DDR SDRAM output timing diagram. Figure 14 provides the AC test load for the DDR2 and DDR3 controller bus.

2.6.1.3 DDR2 and DDR3 SDRAM Differential Timing Specifications

This section describes the DC and AC differential timing specifications for the DDR2 and DDR3 SDRAM controller interface. Figure 15 shows the differential timing specification. Note: VTR specifies the true input signal (such as MCK or MDQS) and VCP is the complementary input signal (such as MCK or MDQS). Figure 13. DDR SDRAM Output Timing Figure 14. DDR2 and DDR3 Controller Bus AC Test Load Figure 15. DDR2 and DDR3 SDRAM Differential Timing Specifications

MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 41 Table 22 provides the DDR2 differential specifications for the differential signals MDQS/MDQS and MCK/MCK. Table 23 provides the DDR3 differential specifications for the differential signals MDQS/MDQS and MCK/MCK.

2.6.2 HSSI AC Timing Specifications

The following subsections define the AC timing requirements for the SerDes reference clocks, the PCI Express data lines, the Serial RapidIO data lines, and the SGMII data lines.

2.6.2.1 AC Requirements for SerDes Reference Clock

Table 24 lists AC requirements for the SerDes reference clocks. Note: Specifications are valid at the recommended operating conditions listed in Table 3. Table 22. DDR2 SDRAM Differential Electrical Characteristics Table 23. DDR3 SDRAM Differential Electrical Characteristics Table 24. SR[1–2]_REF_CLK and SR[1–2]_REF_CLK Input Clock Requirements

MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 43

2.6.2.2 PCI Express AC Physical Layer Specifications

The AC requirements for PCI Express implementations have separate requirements for the Tx and Rx lines. The MSC8254 supports a 2.5 Gbps PCI Express interface defined by the PCI Express Base Specification, Revision 1.0a. The transmitter specifications are defined in Table 25 and the receiver specifications are defined in Table 26. The parameters are specified at the component pins. the AC timing specifications do not include REF_CLK jitter. Note: Specifications are valid at the recommended operating conditions listed in Table 3. Table 25. PCI Express (2.5 Gbps) Differential Transmitter (Tx) Output AC Specifications maximum deviation from the median.

1. The maximum transmitter jitter can be derived as T TX-MAX-JITTER = 1 – TTX-EYE = 0.3 UI.
2. Specified at the measurement point into a ti ming and voltage compliance test load as shown in Figure 8 and measured over

unit intervals of sample data.

1. Jitter is measured using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the Tx UI.
2. All transmitters shall be AC-coupled. The AC coupling is required either within the media or within the transmitting component

itself. The SerDes transmitter does not have built-in Tx ca pacitance. An external AC coupling capacitor is required. Table 26. PCI Express (2.5 Gbps) Differential Receiver (Rx) Input AC Specifications and maximum deviation from the median.

1. The maximum interconnect media and transmitter jitter that can be tolerated by the receiver can be derived as

TRX-MAX-JITTER =1 – TRX-EYE = 0.6 UI.

1. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 8 should be used as

Tx UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram.

1. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deter ministic and random jitter budget for the transmitter and

be used as the reference for the eye diagram.

1. Jitter is defined as the measurement variation of the crossing points (VRX-DIFFp-p = 0 V) in relation to a recovered Tx UI. A

squares and median deviation fi ts have worked well with experimental and simulated data.

MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2

2.6.2.3 Serial RapidIO AC Timing Specifications

Note: Specifications are valid at the recommended operating conditions listed in Table 3. Table 27 defines the transmitter AC specifications for the Serial RapidIO interface. The AC timing specifications do not include REF_CLK jitter. Table 28 defines the Receiver AC specifications for the Serial RapidIO interface. The AC timing specifications do not include REF_CLK jitter. Table 27. Serial RapidIO Transmitter AC Timing Specifications Table 28. Serial RapidIO Receiver AC Timing Specifications Notes: 1. Measured at receiver.

1. Total jitter is composed of three components, deterministic jitter, random jitter, and single frequency sinusoidal jitter. The

is included to ensure margin for low frequency jitter, wander , noise, crosstalk, and other variable system effects. Figure 18. Single Frequency Sinusoidal Jitter Limits

8.5 UI p-p

0.10 UI p-p

MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 45

2.6.2.4 SGMII AC Timing Specifications

Note: Specifications are valid at the recommended operating conditions listed in Table 3. Transmitter and receiver AC characteristics are measured at the transmitter outputs (SR[1–2]_TX[n] and SR[1–2]_TX[n]) or at the receiver inputs (SR[1–2]_RX[n] and SR[1–2]_RX[n]) as depicted in Figure 19, respectively. Table 29 provides the SGMII transmit AC timing specifications. A source synchronous clock is not supported. The AC timing specifications do not include REF_CLK jitter. Table 30 provides the SGMII receiver AC timing specifications. The AC timing specifications do not include REF_CLK jitter. Figure 19. SGMII AC Test/Measurement Load Table 29. SGMII Transmit AC Timing Specifications Table 30. SGMII Receive AC Timing Specifications Notes: 1. Measured at receiver.

1. Refer to RapidIOTM 1x/4x LP Serial Physical Layer Specification for interpretation of jitter specifications. Also see Figure 18.

MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2

2.6.3 TDM Timing

Table 31 provides the input and output AC timing specifications for the TDM interface. Figure 20 shows the TDM receive signal timing. Table 31. TDM AC Timing Specifications for 62.5 MHz1 timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).

1. Output values are based on 30 pF capacitive load.
2. Inputs are referenced to the sampling that the TDM is progr ammed to use. Outputs are referenced to the programming edge

shown using the rising edge.

1. All values are based on a maximum TDM interface frequency of 62.5 MHz.

Figure 20. TDM Receive Signals

MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 47 Figure 21 shows the TDM transmit signal timing. Figure 22 provides the AC test load for the TDM/SI.

2.6.4 Timers AC Timing Specifications

Table 32 lists the timer input AC timing specifications. Note: For recommended operating conditions, see Table 3. Figure 23 shows the AC test load for the timers. Figure 21. TDM Transmit Signals Figure 22. TDM AC Test Load Table 32. Timers Input AC Timing Specifications Notes: 1. The maximum allowed frequency of timer outputs is 125 MHz. Configure the timer modules appropriately.

1. Timer inputs and outputs are asynchronous to any visible clock. Timer outputs should be synchronized before use by any

external synchronous logic. Timer inputs are required to be valid for at least t TIWID ns to ensure proper operation. Figure 23. Timer AC Test Load

MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2

2.6.5 Ethernet Timing

This section describes the AC electrical characteristics for the Ethernet interface. There are programmable delay units (PDU) that should be programmed differently for each interface to meet timing. There is a general configuration register 4 (GCR4) used to configure the timing. For additional information, see the MSC8254 Reference Manual.

2.6.5.1 Management Interface Timing

Table 33 lists the timer input Ethernet controller management interface timing specifications shown in Table 24.

2.6.5.2 RGMII AC Timing Specifications

Table 34 presents the RGMII AC timing specifications for applications requiring an on-board delayed clock. Table 33. Ethernet Controller Management Interface Timing

1. The value depends on the source clock. For example, for a source clock of 267 MHz, the delay is 70 ns. For a source clock of

333 MHz, the delay is 58 ns. Figure 24. MII Management Interface Timing Table 34. RGMII at 1 GHz2 with On-Board Delay3 AC Timing Specifications Notes: 1. At recommended operating conditions with V DDIO of 2.5 V ± 5%.

1. RGMII at 100 MHz support is guaranteed by design.
2. This implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns and

less than 2.0 ns is added to the associated clock signal.

MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 49 Table 35 presents the RGMII AC timing specification for applications required non-delayed clock on board. Figure 25 shows the RGMII AC timing and multiplexing diagrams.

2.6.6 SPI Timing

Table 36 lists the SPI input and output AC timing specifications. Table 35. RGMII at 1 GHz2 with No On-Board Delay3 AC Timing Specifications Notes: 1. At recommended operating conditions with V DDIO of 2.5 V ± 5%.

1. RGMII at 100 MHz support is guaranteed by design.
2. GCR4 should be programmed as 0x000CC330.
3. This implies that PC board design requires clocks to be routed with no additional trace delay

Figure 25. RGMII AC Timing and Multiplexing Table 36. SPI AC Timing Specifications

2.6.7 Asynchronous Signal Timing

Table 35 lists the asynchronous signal timing specifications. MSC8254 device, that is, when the expected input value is read from the GPIO data register.  EE port. Signals EE0, EE1.  Boot function. Signal STOP_BS.  I2C interface. Signals I2C_SCL and I2C_SDA.  Interrupt inputs. Signals IRQ[15–0] and NMI.  Interrupt outputs. Signals INT_OUT and NMI_OUT (minimum pulse width is 32 ns).

2.6.8 JTAG Signals

Table 38 lists the JTAG timing specifications shown in Figure 29 through Figure 32. Table 37. Signal Timing Note: Input value relevant for EE0, IRQ[15–0 ], and NMI only. Table 38. JTAG Timing Note: All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port. Figure 29. Test Clock Input Timing

3 Hardware Design Considerations

The following sections discuss areas to consider when the MSC8254 device is designed into a system.

3.1 Power Supply Ramp-Up Sequence

The following subsections describe the required device initialization sequence.

3.1.1 Clock, Reset, and Supply Coordination

 PORESET and TRST must be asserted externally for the duration of the supply ramp-up, using the VDDIO supply. before normal operation begins to ensure correct functionality of the device. cycles should only be counted from the time after VDDIO reaches its nominal value (see timing 1 in Figure 33). swing within VDDIO range during VDDIO ramp-up, so its amplitude grows as VDDIO grows during ramp-up. Figure 33 shows a sequence in which VDDIO ramps-up after VDD and CLKIN begins to toggle with the raise of VDDIO supply. Note: For details on power-on reset flow and duration, see the Reset chapter in the MSC8254 Reference Manual. Figure 33. Supply Ramp-Up Sequence with VDD Ramping Before VDDIO and CLKIN Starting With VDDIO

3.1.2 Power-On Ramp Time

3.1.3 Power Supply Guidelines

 Couple M3VDD with the VDD power rail using an extremely low impedance path. the same time as or after their respective power rail. using an RC filter (see Figure 38). before power-up should be with slew rate less than 4 V/ns.

1. VDD (and all coupled supplies)
2. After the above rails rise to 90% of their nominal voltage, the following I/O power rails may rise in any sequence (see

Figure 34): QVDD, NVDD, GVDD1, and GVDD2. Table 39. Power Supply Ramp Rate might falsely trigger the ESD circuitry.

1. Required over the full recommended operating temperature range (see Table 3).

Figure 34. Supply Ramp-Up Sequence

Hardware Design Considerations MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 55 Notes: 1. If the M3 memory is not used, M3VDD can be tied to GND. 2. If the HSSI port1 is not used, SXCVDD1and SXPVDD1 must be connected to the designated power supplies. 3. If the HSSI port2 is not used, SXCVDD2 and SXPVDD2 must be connected to the designated power supplies. 4. If the DDR port 1 interface is not used, it is recommended that GVDD1 be left unconnected. 5. If the DDR port 2 interface is not used, it is recommended that GVDD2 be left unconnected.

3.1.4 Reset Guidelines

When a debugger is not used, implement the connection scheme shown in Figure 35. When a debugger is used, implement the connection scheme shown in Figure 36.

3.2 PLL Power Supply Design Considerations

C 1 = 1 0 µF ± 10%, 0603, X5R, with ESL ≤ 0.5 nH, low ESL Surface Mount Capacitor.  C2 = 1.0 µF ± 10%, 0402, X5R, with ESL ≤ 0.5 nH, low ESL Surface Mount Capacitor. Note: A higher capacitance value for C2 may be used to improve the filter as long as the other C2 parameters do not change. applied to each PLL separately. For optimal noise filtering, place the circuit as close as possible to its PLLn_A VDD inputs. Figure 35. Reset Connection in Functional Application Figure 36. Reset Connection in Debugger Application

self-resonant frequency. All trances should be kept short, wide, and direct.

3.3 Clock and Timing Signal Board Layout Considerations

 Keep clock and timing signal paths as short as possible and route with 50 Ω impedance. Rbuf = clock buffer internal impedance. Figure 37. PLL Supplies Figure 38. SerDes PLL Supplies

3.4 SGMII AC-Coupled Serial Link Connection Example

sales office or representative.

3.5 Connectivity Guidelines

connections in this discussion.

1. GND indicates using a 10 k Ω pull-down resistor (recommended) or a direct connection to the ground plane. Direct

DD indicates using a 10 kΩ pull-up resistor (recommended) or a direct connection to the appropriate power supply.

1. Mandatory use of a pull-up or pull-down resistor is clear ly indicated as “pull-up/pull-down.” For buses, each pin on

the bus should have its own resistor.

1. NC indicates “not connected” and mean s do not connect anything to the pin.
2. The phrase “in use” indicates a typical pin connection for the required function.

subset interface connection. Figure 39. 4-Wire AC-Coupled SGMII Serial Link Connection Example

3.5.1 DDR Memory Related Pins

This section discusses the various scenarios that can be used with either of the MSC8254 DDR ports.

3.5.1.1 DDR Interface Is Not Used

Table 40. Connectivity of DDR Related Pins When the DDR Interface Is Not Used Notes: 1. For the signals listed in this table, the initial M stand s for M1 or M2 depending on which DDR controller is not used.

1. If the DDR controller is not used, disable the internal DDR clock by setting the appropr iate bit in the System Clock Control

Clocks and General Configuration Registers chapters in the MSC8254 Reference Manual for details.

1. For MSC8254 Revision 1 silicon, these pins were connected to GND. For newer revisions of the MSC8254, connecting these

pins to GND increases device power consumption.

3.5.1.2 DDR Interface Is Used With 32-Bit DDR Memory Only

Table 41 lists unused pin connection when using 32-bit DDR memory. The 32 most significant data lines are not used.

3.5.1.3 ECC Unused Pin Connections

the correct pin connections. Table 41. Connectivity of DDR Related Pins When Using 32-bit DDR Memory Only Notes: 1. For the signals listed in this table, the initial M stand s for M1 or M2 depending on which DDR controller is not used.

1. For MSC8254 Revision 1 silicon, these pins were connected to GND (or VDD). For newer revisions of the MSC8254,

connecting these pins to GND incr eases device power consumption. Table 42. Connectivity of Unused ECC Mechanism Pins Notes: 1. For the signals listed in this table, the initial M stand s for M1 or M2 depending on which DDR controller is not used.

1. For MSC8254 Revision 1 silicon, these pins were connected to GND (or VDD). For newer revisions of the MSC8254,

connecting these pins to GND incr eases device power consumption.

3.5.1.4 DDR2 Unused MAPAR Pin Connections

When the MAPAR signals are not used, refer to Table 43 to determine the correct pin connections.

3.5.2 HSSI-Related Pins

3.5.2.1 HSSI Port Is Not Used

The signal names in Table 44 and Table 45 are generic names for a RapidIO interface. For actual pin names refer to Table 1.

3.5.2.2 HSSI Specific Lane Is Not Used

Table 43. Connectivity of MAPAR Pins for DDR2 Notes: 1. For the signals listed in this table, the initial M stands for M1 or M2 depending on which DDR controller is used for DDR2.

1. For MSC8254 Revision 1 silicon, these pins were connected to GND. For newer revisions of the MSC8254, connecting these

pins to GND increases device power consumption. Table 44. Connectivity of Serial RapidIO Interface Related Pins When the RapidIO Interface Is Not Used Note: All lanes in the HSSI SerDes should be powered down. Refer to the MSC8254 Reference Manual for details. Table 45. Connectivity of HSSI Related Pins When Specific Lane Is Not Used

3.5.3 RGMII Ethernet Related Pins

used, connect the pin as required to support that function. Table 47 lists the recommended management pin connections.

3.5.4 TDM Interface Related Pins

to support the selected function. Note: The n indicates the lane number {0,1,2,3} for all unused lanes. Table 46. Connectivity of RGMII Related Pins When the RGMII Interface Is Not Used Note: Assuming GE1 and GE2 are disabled in the reset configuration word. Table 47. Connectivity of GE Management Pins When GE1 and GE2 Are Not Used Table 48. Connectivity of TDM Related Pins When TDM Interface Is Not Used Table 45. Connectivity of HSSI Related Pins When Specific Lane Is Not Used (continued)

3.5.5 Miscellaneous Pins

of the specified pin is not used. If the alternate function is used, connect that pin as required to support the selected function. and MSC825x DSP Family Design Checklist.

1. In case of subset of TDM interface usage pleas e make sure to disable unused TDM modules. See TDM chapter in the

MSC8254 Reference Manual for details. Table 49. Connectivity of Individual Pins When They Are Not Required SCL See the GPIO connectivity guidelines in this table. SDA See the GPIO connectivity guidelines in this table. IRQ[15–0] See the GPIO connectivity guidelines in this table. TMR[4–0] See the GPIO connectivity guidelines in this table. See Section 3.1 for guidelines. URXD See the GPIO connectivity guidelines in this table. UTXD See the GPIO connectivity guidelines in this table. DDN[1–0] See the GPIO connectivity guidelines in this table. DRQ[1–0] See the GPIO connectivity guidelines in this table.

MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2

Ordering Information

3.6 Guide to Selecting Connections for Remote Power Supply

To assure consistency of input power levels, some applications use a practice of connecting the remote sense signal input of an on-board power supply to one of power supply pins of the IC device. The advantage of using this connection is the ability to compensate for the slow components of the IR drop caused by resistive supply current path from on-board power supply to the pins layer on the package. However, because of specific device requirements, not every ball connection can be selected as the remote sense pin. Some of these pins must be connected to the appropriate power supply or ground to ensure correct device functionality. Some connections supply critical power to a specific high usage area of the IC die; using such a connection as a non-supply pin could impact necessary supply current during high current events. The following balls can be used as the board supply remote sense output without degrading the power and ground supply quality:  VDD: W10, T19  VSS: J18, Y10  M3VDD: None Do not use any other connections for remote sensing. Use of any other connections for this purpose can result in application and device failure.

4 Ordering Information

Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order. Part Package Type Spheres Core Voltage Operating Temperature Core Frequency (MHz) Order Number MSC8254 Flip Chip Plastic Ball Grid Array (FC-PBGA) Lead-free 1.0 V 0° C to 105°C 1000 MSC8254SVT1000B –40° C to 105°C 1000 MSC8254TVT1000B 0° C to 105°C 800 MSC8254SVT800B –40° C to 105°C 800 MSC8254TVT800B

Package Information

MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 65

5 Package Information

NOTES: 1. ALL DIMENSIONS IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 3. MAXIMUM SOLDER BALL DIAMETER MEASURE PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE, IS DETERMINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. 6. ALL DIMENSIONS ARE SYMMETRIC ACROSS THE PACKAGE CENTER LINES, UNLESS DIMENSIONED OTHERWISE. 7. 29.2MM MAXIMUM PACKAGE ASSEMBLY (LID + LAMINATE) X AND Y . Figure 40. MSC8254 Mechanical Information, 783-ball FC-PBGA Package

6 Product Documentation

package and pinout, and electrical design considerations of the MSC8254 device. internal subsystems including configuration and programming information.  Application Notes. Cover various programming topics related to the StarCore DSP core and the MSC8254 device. regarding the QUICC Engine technology including functional description, registers, and programming information. control, and instruction set.

7 Revision History

Table 50 provides a revision history for this data sheet. Table 50. Document Revision History 0 Apr. 2010  Initial public release. 1 May 2010  Changed connection for pins K17, L14, L1 6, M15, M17, and N14 from VDD to VSS in Table 1.  Updated Section 3.1.2, Power-On Ramp Time. 2 Dec 2010  Updated Table 16.  Updated Section 3.1.2, Power-On Ramp Time.  Updated Section 4, Ordering Information.

Revision History

MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 67

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