MSC8144

MSC8144 FREESCALE | Alldatasheet

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Data Sheet: Product Preview Document Number: MSC8144 Rev. 1, 5/2007 © Freescale Semiconductor, Inc., 2007. All rights reserved. This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. MSC8144 FC-PBGA–783 29 mm × 29 mm

• Four StarCore™ SC3400 DSP subsystems, each with an SC3400 DSP core, 16 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, memory management unit (MMU), extended programmable interrupt controller (EPIC), two general-purpose 32-bit timers, debug and profiling support, and low-power Wait and Stop processing modes.  Chip-level arbitration and system (CLASS) that provides full fabric non-blocking arbitration between the processing elements and other initiators and the M2 memory, DDR SRAM controller, device configuration control and status registers, and other targets.  128 Kbyte L2 shared instruction cache.  512 Kbyte M2 memory for critical data and temporary data buffering.  10 Mbyte 128-b8t wide M3 memory.  96 Kbyte boot ROM.  Three input clocks (shared, global, and differential).  Four PLLs (system, core, global, and serial RapidIO).  DDR controller with up to a 200 MHz clock (400 MHz data rate), 16/32 bit data bus, supporting up to 1 Gbyte in up to two banks and support for DDR1 and DDR2.  DMA controller with 16 bidirectional channels with up to 1024 buffer descriptors, and programmable priority, buffer, and multiplexing configuration.  Up to eight independent TDM modules with programmable word size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion, up to 128 Mbps data rate for all channels, with glueless interface to E1 or T1 framers, and can interface with H-MVIP/H.110 devices, TSI, and codecs such as AC-97.  QUICC Engine™ technology subsystem with dual RISC processors, 48 Kbyte multi-master RAM, 48 Kbyte instruction RAM, supporting three communication controllers with one A TM and two Gigabit Ethernet interfaces, to offload scheduling tasks from the DSP cores. – The two Ethernet controllers support 10/100/1000 Mbps operations via MII/RMII/SMII/RGMII/SGMII and the SGMII protocol using a 4-pin SerDes interface at 1000 Mbps data rate only. – The ATM controller supports UTOPIA level II 8/16 bits at 25/50 MHz in UTOPIA/POS mode with adaptation layer support AAL0, AAL2, and AAL5.  PCI designed to comply with the PCI specification revision 2.2 at 33 MHz or 66 MHz with access to all PCI address spaces.  Serial RapidIO® 1x/4x endpoint corresponds to Specification 1.2 of the RapidIO trade association, and supports read, write, messages, doorbells, and maintenance accesses in inbound mode, and messages and doorbells in outbound mode.  I/O interrupt concentrator consolidates all chip maskable interrupt and non-maskable interrupt sources and routes them to INT_OUT , NMI_OUT, and the cores.  UART that permits full-duplex operation with a bit rate of up to 6.25 Mbps.  Serial peripheral interface (SPI).  Four timer modules, each with four configurable16-bit timers.  Four software watchdog timer (SWT) modules.  Up to 32 general-purpose input/output (GPIO) ports, 16 of which can be configured as maskable interrupt inputs. I 2C interface that allows booting from EEPROM devices.  Eight programmable hardware semaphores.  Thirty two virtual maskable interrupts and one virtual NMI that can be generated by a simple write access.  Optional booting via serial RapidIO port, PCI, I 2C, SPI, or Ethernet interfaces. Note: This document supports mask set M31H. Quad Core Digital Signal Processor

Figure 1. MSC8144 Block Diagram Figure 2. StarCore SC3400 DSP Core Subsystem Block Diagram Note: The arrow direction indicates master or slave.

8 TDMs

512 Kbytes

128 Kbyte

400 MHz

1 Pin Assignments and Reset States

1.1 FC-PBGA Ball Layout Diagrams

Top and bottom views of the FC-PBGA package are shown in Figure 3 and Figure 4 with their ball location index numbers. Figure 3. MSC8144 FC-PBGA Package, Top View

Figure 4. MSC8144 FC-PBGA Package, Bottom View

1.2 Signal List By Ball Location

Table 1. Signal List by Ball Number

Table 1. Signal List by Ball Number (continued)

Electrical Characteristics

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 25

2 Electrical Characteristics

This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications. For additional information, see the MSC8144 Reference Manual.

2.1 Maximum Ratings

In calculating timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. AH17 Reserved 1 — AH18 Reserved 1 — AH19 Reserved 1 — AH20 Reserved 1 — AH21 Reserved 1 — AH22 Reserved 1 — AH23 Reserved 1 — AH24 Reserved 1 — AH25 Reserved 1 — AH26 Reserved 1 — AH27 Reserved 1 — AH28 Reserved 1 — Notes: 1. Reserved signals should be disconnected for compatibility with future revisions of the device. 2. For signals with same functionality in all modes the appropriate cells are empty. 3. The choice between GPIO function and other function is by GPIO registers setup. For configuration details, see Chapter 23, GPIO in the MSC8144 Reference Manual. 4. Open-drain signal. 5. Internal 20 KΩ pull-up resistor. 6. For signals with GPIO functionality, the open-drain and internal 20 K Ω pull-up resistor can be configured by GPIO register programming. See Chapter 23, GPIO of the MSC8144 Reference Manual for configuration details. CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or V DD).

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Table 2 describes the maximum electrical ratings for the MSC8144. Table 2. Absolute Maximum Ratings Notes: 1. Functional operating conditions are given in Table 3.

1. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond

the listed limits may affect device reliability or cause permanent damage.

1. Section 3.5 , Thermal Considerations includes a formula for computing the chip junction temperature (T J).
2. PLL supply voltage is specified at input of the filter and not at pin of the MSC8144 (see Figure 46)

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 27

2.2 Recommended Operating Conditions

Table 3 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed.

2.3 Default Output Driver Characteristics

Table 4 provides information on the characteristics of the output driver strengths. The values are preliminary estimates. Table 3. Recommended Operating Conditions Note: PLL supply voltage is specified at input of the filter and not at pin of the MSC8144 (see Figure 46). Table 4. Output Drive Impedance

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1

2.4 Thermal Characteristics

Table 5 describes thermal characteristics of the MSC8144 for the FC-PBGA packages. Section 3.5, Thermal Considerations provides a detailed explanation of these characteristics.

2.5 Power Characteristics

The estimated typical power dissipation for MSC8144 versus the core frequency is shown in Table 6. Table 5. Thermal Characteristics for the MSC8144

1. Per JEDEC JESD51-2 with the single la yer board (JESD51-3) horizontal.
2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
3. Thermal resistance between the die and the printed circuit boar d per JEDEC JESD 51-8. Boar d temperature is measured on

the top surface of the board near the package.

1. Thermal resistance between the active surface of the die and the case top surface determined by the cold plate method (MIL

SPEC-883 Method 1012.1) with the calculated case temperature. Table 6. Power Dissipation

533 TBD

667 TBD

800 TBD

833 TBD

1000 TBD

600 TBD

750 TBD

Note: Measured for 1.0 V core at 25°C junction temperature.

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 29 The typical power values were measured using an EFR code with the device running at a junction temperature of 25°C. No peripherals were enabled and the ICache was not enabled. The source code was optimized to use all the ALUs and AGUs and all four cores. It was created using CodeWarrior ® 3.0. These values are provided as examples only. Power consumption is application dependent and varies widely. To assure proper board design with regard to thermal dissipation and maintaining proper operating temperatures, evaluate power consumption for your application and use the design guidelines in Section 3 of this document. At allowable voltage levels, Table 7 lists the estimated power dissipation on the 1.0-V A V DD supplies for the MSC8144 PLLs.

2.6 DC Electrical Characteristics

This section describes the DC electrical characteristics for the MSC8144.

2.6.1 DDR SDRAM DC Electr ical Characteristics

This section describes the DC electrical specifications for the DDR SDRAM interface of the MSC8144. Note: DDR SDRAM uses VDDDDR(typ) = 2.5 V and DDR2 SDRAM uses VDDDDR(typ) = 1.8 V. 2.6.1.1 DDR2 (1.8 V) SDRAM DC Electrical Characteristics Table 8 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the MSC8144 when VDDDDR(typ) = 1.8 V . Table 7. MSC8144 PLLs Power Dissipation Note: Typical value is based on VDD = 1.0 V, TA = 70°C, TJ = 105°C. Table 8. DDR2 SDRAM DC Electrical Characteristics for VDD(typ) = 1.8 V Notes: 1. VDDDDR is expected to be within 50 mV of the DRAM V DD at all times.

1. MVREF is expected to be equal to 0.5 × VDDDDR, and to track VDDDDR DC variations as measured at the receiver.

Peak-to-peak noise on MVREF may not exceed ±2% of the DC value.

1. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF. This rail should track variations in the DC level of V DDDDR.

1. Output leakage is measured with all outputs are disabled, 0 V ≤ VOUT ≤ VDDDDR.

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Table 9 provides the DDR capacitance when VDDDDR(typ) = 1.8 V . 2.6.1.2 DDR (2.5V) SDRAM DC Electrical Characteristics Table 10 provides the recommended operating conditions for the DDR SDRAM component(s) of the MSC8144 when VDDDDR(typ) = 2.5 V . Table 11 provides the DDR capacitance when VDDDDR (typ) = 2.5 V . Table 12 lists the current draw characteristics for MVREF. Table 9. DDR2 SDRAM Capacitance for VDDDDR(typ) = 1.8 V Table 10. DDR SDRAM DC Electrical Characteristics for VDDDDR (typ) = 2.5 V Notes: 1. VDDDDR is expected to be within 50 mV of the DRAM V DD at all times.

1. MVREF is expected to be equal to 0.5 × VDDDDR, and to track VDDDDR DC variations as measured at the receiver.

Peak-to-peak noise on MVREF may not exceed ±2% of the DC value.

1. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF. This rail should track variations in the DC level of V DDDDR.

1. Output leakage is measured with all outputs are disabled, 0 V ≤ VOUT ≤ VDDDDR.

Table 11. DDR SDRAM Capacitance for VDDDDR (typ) = 2.5 V Table 12. Current Draw Characteristics for MVREF Note: The voltage regulator for MVREF must be able to supply up to 500 μA current.

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 31

2.6.2 Serial RapidIO DC Electrical Characteristics

DC receiver logic levels are not defined since the receiver is AC-coupled.

2.6.2.1 DC Requirements for SerDes Reference Clocks

The SerDes reference clocks SRIO_REF_CLK and SRIO_REF_CLK are AC-coupled differential inputs. Each differential clock input has an internal 50 Ω termination to GNDSXC. The reference clock must be able to drive this termination. The recommended minimum operating voltage is –0.4 V; the recommended maximum operating voltage is 1.32 V; and the maximum absolute voltage is 1.72 V . The maximum average current allowed in each input is 8 mA. This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V/50 Ω = 8 mA) while the minimum common mode input level is GNDSXC. For example, a clock with a 50/50 duty cycle can be driven by a current source output that ranges from 0 mA to 16 mA (0–0.8 V). The input is AC-coupled internally, so, therefore, the exact common mode input voltage is not critical. Note: This internal AC-couple network does not function correctly with reference clock frequencies below 90 MHz. If the device driving the SRIO_REF_CLK inputs cannot drive 50 Ω to GNDSXC, or if it exceeds the maximum input current limitations, then it must use external AC-coupling. The minimum differential peak-to-peak amplitude of the input clock is 0.4 V (0.2 V peak-to-peak per phase). The maximum differential peak-to-peak amplitude of the input clock is 1.6 V peak-to-peak (see Figure 5. The termination to GND Figure 5. SerDes Reference Clocks Input Stage

2.6.2.2 Spread Spectrum Clock

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1

2.6.3 PCI DC Electrical Characteristics

The measurements in Table 13 assume the following system conditions: T A = 25 °C  GND = 0 VDC Note: The leakage current is measured for nominal conditions.

2.6.4 TDM DC Electrical Characteristics

The measurements in Table 14 assume the following system conditions: T A = 25 °C  GND = 0 VDC Note: The leakage current is measured for nominal conditions.

2.6.5 UART DC Electri cal Characteristics

Table 13. PCI DC Electrical Characteristics Notes: 1. See Figure 6 for undershoot and overshoot voltages.

1. Not tested. Guaranteed by design.

Table 14. TDM DC Electrical Characteristics Note: Not tested. Guaranteed by design.

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 33

2.6.6 Ethernet DC Electrical Characteristics

The measurements assume: T A = 25 °C  GND = 0 VDC

2.6.6.1 MII, SMII and RMII DC Electrical Characteristics

2.6.6.2 RGMII DC Electrical Characteristics

Table 15. MII, SMII and RMII DC Electrical Characteristics Note: Not tested. Guaranteed by design. Table 16. RGMII DC Electrical Characteristics Note: Not tested. Guaranteed by design.

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1

2.6.7 ATM/UTOPIA DC Electrical Characteristics

2.6.8 SPI DC Electrical Characteristics

Table 18 provides the SPI DC electrical characteristics.

2.6.9 GPIO, EE, CLKIN, JTAG Ports DC Electrical Characteristics

The measurements in Table 19 assume: T A = 25 °C  GND = 0 VDC Note: The leakage current is measured for nominal conditions. Table 17. ATM/UTOPI DC Electrical Characteristics Notes: 1. Not tested. Guaranteed by design. Table 18. SPI DC Electrical Characteristics Table 19. GPIO and CLKIN DC Electrical Characteristics

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 35

2.7 AC Timings

The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs.

2.7.1 Start-Up Timing

Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.7.2 describes the clocking characteristics. Section 2.7.3 describes the reset and power-up characteristics. You must use the following guidelines when starting up an MSC8144 device:  PORESET and TRST must be asserted externally for the duration of the power-up sequence using the VDDIO (3.3 V) supply. See Table 24 for timing. TRST deassertion does not have to be synchronized with PORESET deassertion. During functional operation when JTAG is not used, TRST can be asserted and remain asserted after the power ramp. Note: For applications that use M3 memory, M3_RESET should replicate the PORESET sequence timing, but using the  CLKIN should start toggling at least 32 cycles before the PORESET deassertion to guarantee correct device operation (see Figure 7). 32 cycles should be accounted only after VDDIO reaches its nominal value.  CLKIN and PCI_CLK_IN should either be stable low during the power-up of VDDIO supply and start their swings after power-up or should swing within VDDIO range during VDDIO power-up., so their amplitude grows as VDDIO grows during power-up. Figure 7 shows a sequence in which VDDIO is raised after VDD and CLKIN begins to toggle with the raise of VDDIO supply. Output low voltage, IOL= 3.2 mA V OL —0 . 4 V Notes: 1. See Figure 6 for undershoot and overshoot voltages. 2. Not tested. Guaranteed by design. Figure 6. Overshoot/Undershoot Voltage for VIH and VIL Table 19. GPIO and CLKIN DC Electrical Characteristics (continued)

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1

2.7.2 Clock and Timing Signals

The following sections include a description of clock signal characteristics. Table 20 shows the maximum frequency values for internal (Core, Reference, Bus and DSI) and external (CLKIN, PCI_CLK_IN and CLKOUT. The user must ensure that maximum frequency values are not exceeded.

2.7.3 Reset Timing

The MSC8144 has several inputs to the reset logic:  Power-on reset ( PORESET)  External hard reset ( HRESET)  External soft reset ( SRESET)  Software watchdog reset J T A G r e s e t  RapidIO reset  Software hard reset  Software soft reset All MSC8144 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset. The reset status register indicates the most recent sources to cause a reset. Table 22 describes the reset sources. Figure 7. Start-Up Sequence with V Table 20. Clock Frequencies Table 21. Clock Parameters

3.3 V VDDIO Nominal

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 37 Table 22. Reset Sources Table 23 summarizes the reset actions that occur as a result of the different reset sources. reset source and word are configured only when PORESET is asserted. driven, the extended cores are reset, and system configuration is maintained. soft reset signal and an internal soft reset sequence is generated. enabled software watchdog event then generates an internal hard reset sequence. Table 23. Reset Actions for Each Reset Source Section 2.7.3.2 for details).

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1

2.7.3.1 Power-On Reset (PORESET ) Pin

Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 32 CLKIN cycles after VDD and VDDIO are both at their nominal levels.

2.7.3.2 Reset Configuration

The MSC8144 has two mechanisms for writing the reset configuration:  Through the I 2C port  Through external pins  Through internal hard coded Twenty-three signals (see Section 1 for signal description details) are sampled during the power-on reset sequence to define the Reset Word Configuration Source and operating conditions:  RCW_SRC[2–0]  RC[16–0] The RCFG_CLKIN_RNG pin must be valid during power-on or hard reset sequence. The STOP_BS pin must be always valid and is also sampled during power-on reset sequence for RCW loading from an I2C EEPROM.

2.7.3.3 Reset Timing Tables

Table 24 and Figure 8 describe the reset timing for a reset configuration. Table 24. Timing for a Reset Configuration Write

1 Required external PORESET duration minimum

2 Delay from de-assertion of external PORESET

3 Delay from HRESET

Note: Timings are not tested, but are guaranteed by design.

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 39 See also Reset Errata for PLL lock and reset duration.

2.7.4 DDR SDRAM AC Timing Specifications

This section describes the AC electrical characteristics for the DDR SDRAM interface.

2.7.4.1 DDR SDRAM Input Timings

Table 22 provides the input AC timing specifications for the DDR SDRAM when VDD(typ) = 2.5 V. Table 23 provides the input AC timing specifications for the DDR SDRAM when VDD(typ) = 1.8 V. Table 24 provides the input AC timing specifications for the DDR SDRAM interface. Figure 8. Timing for a Reset Configuration Write Table 22. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface Note: At recommended operating conditions with V DD of 2.5 ± 5%. Table 23. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface Note: At recommended operating conditions with V DD of 1.8 ± 5%. Table 24. DDR SDRAM Input AC Timing Specifications captured with MDQS[n]. Subtract this value from the total timing budget.

1. At recommended operating conditions with V DD (1.8 V or 2.5 V) ± 5%

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1

2.7.4.2 DDR SDRAM Output AC Timing Specifications

Table 25 provides the output AC timing specifications for the DDR SDRAM interface. Table 25. DDR SDRAM Output AC Timing Specifications (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.

1. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
2. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK , MCS, and MDQ/MECC/MDM/MDQS. For the
3. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD)

enabled by use of these bits.

1. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC

(MECC), or data mask (MDM). The data strobe should be centered in side of the data eye at the pins of the microprocessor.

1. All outputs are referenced to the rising edge of MCK(n) at the pins of the microprocessor. Note that t DDKHMP follows the

symbol conventions described in note 1.

1. At recommended operating conditions with V DD (1.8 V or 2.5 V) ± 5%.

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Figure 11 provides the AC test load for the DDR bus.

2.7.5 Serial RapidIO Timing and SGMII Timing

2.7.5.1 AC Requirements for SRIO_REF_CLK and SRIO_REF_CLK

Table 26 lists AC requirements. Figure 11. DDR AC Test Load Table 26. SDn_REF_CLK and SDn_REF_CLK AC Requirements a 156.25 MHz reference clock.

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 43

2.7.5.2 Signal Definitions

LP-Serial links use differential signaling. This section defines terms used in the description and specification of differentia l signals. Figure 12 shows how the signals are defined. The figure shows waveforms for either a transmitter output (TD and TD) or a receiver input (RD and RD). Each signal swings between voltage levels A and B, where A > B. Note: This explanation uses generic TD/TD/RD/RD signal names. These correspond to SRIO_TXD/SRIO_TXD/ SRIO_RXD/SRIO_RXD respectively. Using these waveforms, the definitions are as follows: 1. The transmitter output signals and the receiver input signals TD, TD , RD and RD each have a peak-to-peak voltage (VPP) swing of A – B. 2. The differential output signal of the transmitter, V OD, is defined as VTD – VTD. 3. The differential input signal of the receiver, V ID, is defined as VRD – VRD. 4. The differential output signal of the transmitter and the differential input signal of the receiver each range from A – B to –(A – B). 5. The peak value of the differential transmitter output signal and the differential receiver input signal is A – B. 6. The value of the differential transmitter output si gnal and the differential receiver input signal is 2 × (A – B) VPP. To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5 V and 2.0 V . Using these values, the peak-to-peak voltage swing of the signals TD and TD is 500 mVPP. The differential output signal ranges between 500 mV and –500 mV . The peak differential voltage is 500 mV. The peak-to-peak differential voltage is 1000 mVPP. Note: AC electrical specifications are given for transmitter and receiver. Long run and short run interfaces at three baud rates (a total of six cases) are described. The parameters for the AC electrical specifications are guided by the XAUI electrical interface specified in Clause 47 of IEEE™ Std 802.3ae-2002™. XAUI has similar application goals to serial RapidIO. The goal of this standard is that electrical designs for serial RapidIO can reuse electrical designs for XAUI, suitably modified for applications at the baud intervals and reaches described herein.

2.7.5.3 Equalization

With the use of high speed serial links, the interconnect media will cause degradation of the signal at the receiver. Effects such as Inter-Symbol Interference (ISI) or data dependent jitter are produced. This loss can be large enough to degrade the eye opening at the receiver beyond what is allowed in the specification. To negate a portion of these effects, equalization can be used. The most common equalization techniques that can be used are:  A passive high pass filter network placed at the receiver. This is often referred to as passive equalization.  The use of active circuits in the receiver. Th is is often referred to as adaptive equalization. Figure 12. Differential V

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1

2.7.5.4 Transmitter Specifications

LP-Serial transmitter electrical and timing specifications are stated in the text and tables of this section. The differential return loss, S11, of the transmitter in each case shall be better than  –10 dB for (baud frequency)/10 < freq(f) < 625 MHz, and  –10 dB + 10log(f/625 MHz) dB for 625 MHz ≤ freq(f) ≤ baud frequency The reference impedance for the differential return loss measurements is 100 Ω resistive. Differential return loss includes contributions from internal circuitry, packaging, and any external components related to the driver. The output impedance requirement applies to all valid output levels. It is recommended that the 20–80% rise/fall time of the transmitter, as measured at the transmitter output, have a minimum value 60 ps in each case. It is also recommended that the timing skew at the output of an LP-Serial transmitter between the two signals comprising a differential pair not exceed 25 ps at 1.25 GB, 20 ps at 2.50 GB, and 15 ps at 3.125 GB. Table 27. Short Run Transmitter AC Timing Specifications—1.25 GBaud Table 28. Short Run Transmitter AC Timing Specifications—2.5 GBaud Table 29. Short Run Transmitter AC Timing Specifications—3.125 GBaud

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 45 For each baud rate at which an LP-Serial transmitter is specified to operate, the output eye pattern of the transmitter shall f all entirely within the unshaded portion of the transmitter output compliance mask shown in Figure 13 with the parameters specified in Table 33 when measured at the output pins of the device and the device is driving a 100 Ω ±5% differential resistive load. The output eye pattern of an LP-Serial transmitter that implements pre-emphasis (to equalize the link and reduce inter-symbol interference) need only comply with the transmitter output compliance mask when pre-emphasis is disabled or minimized. Table 30. Long Run Transmitter AC Timing Specifications—1.25 GBaud Table 31. Long Run Transmitter AC Timing Specifications—2.5 GBaud Table 32. Long Run Transmitter AC Timing Specifications—3.125 GBaud

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1

2.7.5.5 Receiver Specifications

LP-Serial receiver electrical and timing specifications are stated in the text and tables of this section. Receiver input impedance shall result in a differential return loss better that 10 dB and a common mode return loss better than 6 dB from 100 MHz to 0.8 × baud frequency. This includes contributions from internal circuitry, the package, and any external components related to the receiver. AC coupling components are included in this requirement. The reference impedance for return loss measurements is 100 Ω resistive for differential return loss and 25 Ω resistive for common mode. Figure 13. Transmitter Output Compliance Mask Table 33. Transmitter Differential Output Eye Diagram Parameters Table 34. Receiver AC Timing Specifications—1.25 GBaud

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 47 Total Jitter Tolerance J T 0.65 UI PP Measured at receiver. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 14. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. Multiple Input Skew S MI 24 ns Skew at the receiver input between lanes of a multilane link Bit Error Rate BER 10 –12 Unit Interval UI 800 800 ps ±100 ppm Table 35. Receiver AC Timing Specifications—2.5 GBaud Table 36. Receiver AC Timing Specifications—3.125 GBaud Table 34. Receiver AC Timing Specifications—1.25 GBaud (continued)

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1

2.7.5.6 Receiver Eye Diagrams

For each baud rate at which an LP-Serial receiver is specified to operate, the receiver shall meet the corresponding bit error rate specification (Table 34, Table 35, and Table 36) when the eye pattern of the receiver test signal (exclusive of sinusoidal jitter) falls entirely within the unshaded portion of the receiver input compliance mask shown in Figure 15 with the parameters specified in Table 37. The eye pattern of the receiver test signal is measured at the input pins of the receiving device with the device replaced with a 100 Ω ±5% differential resistive load. Bit Error Rate BER 10 –12 Unit Interval UI 320 320 ps ±100 ppm Figure 14. Single Frequency Sinusoidal Jitter Limits Table 36. Receiver AC Timing Specifications—3.125 GBaud (continued)

8.5 UI p-p

0.10 UI p-p

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 49

2.7.5.7 Measurement and Test Requirements

Since the LP-Serial electrical specification are guided by the XAUI electrical interface specified in Clause 47 of IEEE Std. 802.3ae-2002™, the measurement and test requirements defined he re are similarly guided by Clause 47. In addition, the CJPAT test pattern defined in Annex 48A of IEEE Std. 802.3ae-2002 is specified as the test pattern for use in eye pattern and jitter measurements. Annex 48B of IEEE Std. 802.3ae-2002 is recommended as a reference for additional information on jitter test methods.

2.7.5.8 Eye Template Measurements

For the purpose of eye template measurements, the effects of a single-pole high pass filter with a 3 dB point at (baud frequency)/1667 is applied to the jitter. The data pattern for template measurements is the continuous jitter test pattern (CJPAT) defined in Annex 48A of IEEE Std. 802.3ae. All lanes of the LP-Serial link shall be active in both the transmit and receive directions, and opposite ends of the links shall use asynchronous clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane implementations shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. The amount of data represented in the eye shall be adequate to ensure that the bit error ratio is less than 10 –12. The eye pattern shall be measured with AC coupling and the compliance template centered at 0 V olts differential. The left and right edges of the template shall be aligned with the mean zero crossing points of the measured data eye. The load for this test shall be 100 Ω resistive ±5% differential to 2.5 GHz. Figure 15. Receiver Input Compliance Mask Table 37. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1

2.7.5.9 Jitter Test Measurements

For the purpose of jitter measurement, the effects of a single-pole high pass filter with a 3 dB point at (baud frequency)/1667 is applied to the jitter. The data pattern for jitter measurements is the Continuous Jitter Test Pattern (CJPAT) pattern defined in Annex 48A of IEEE Std. 802.3ae. All lanes of the LP-Serial link shall be active in both the transmit and receive directions, and opposite ends of the links shall use asynchronous clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane implementations shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. Jitter shall be measured with AC coupling and at 0 V differential. Jitter measurement for the transmitter (or for calibration of a jitter tolerance setup) shall be performed with a test procedure resulting in a BER curve such as that described in Annex 48B of IEEE Std. 802.3ae.

2.7.5.10 Transmit Jitter

Transmit jitter is measured at the driver output when terminated into a load of 100 Ω resistive ±5% differential to 2.5 GHz.

2.7.5.11 Jitter Tolerance

Jitter tolerance is measured at the receiver using a jitter tolerance test signal. This signal is obtained by first producing the sum of deterministic and random jitter defined in Section 2.7.5.9 and then adjusting the signal amplitude until the data eye contacts the 6 points of the minimum eye opening of the receive template shown in Figure 15 and Table 37. Note that for this to occur, the test signal must have vertical waveform symmetry about the average value and have horizontal symmetry (including jitter) about the mean zero crossing. Eye template measurement requirements are as defined above. Random jitter is calibrated using a high pass filter with a low frequency corner at 20 MHz and a 20 dB/decade roll-off below this. The required sinusoidal jitter specified in Section 8.6 is then added to the signal and the test load is replaced by the receiver being tested.

2.7.6 PCI Timing

This section describes the general AC timing parameters of the PCI bus. Table 38 provides the PCI AC timing specifications. Table 38. PCI AC Timing Specifications

33 MHz 66 MHz

Notes: 1. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications .

1. All PCI signals are measured from OV DD/2 of the rising edge of PCI_SYNC_IN to 0.4 × OVDD of the signal in question for
2. For purposes of active/float timing meas urements, the Hi-Z or off state is defin ed to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

1. Input timings are measured at the pin.
2. The reset assertion timing requirement for HRESET is in Table 24 and Figure 8

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1

2.7.7 TDM Timing

Figure 19 shows the TDM input AC timing. Note: For some TDM modes receive data and receive sync are being input on other pins. This timing is valid for them as well. See the MSC8144 Reference Manual. Figure 20 shows TDMxTSYN AC timing in TSO=0 mode. Figure 21 shows the TDM Output AC timing Table 39. TDM Timing

1. Values are based on 20 pF capacitive load.
2. Values are based on 10 pF capacitive load.

Figure 19. TDM Inputs Signals Figure 20. TDMxTSYN in TSO=0 mode

2.7.8 UART Timing

Figure 21. TDM Output Signals Table 40. UART Timing Note: TUREFCLK = TREFCLK is guaranteed by design. Figure 22. UART Input Timing Figure 23. UART Output Timing

2.7.9 Timer Timing

2.7.10 Ethernet Timing

This section describes the AC electrical characteristics for the Ethernet interface.

2.7.10.1 Management Interface Timing

Table 41. Timer Timing Figure 24. Timer Timing Table 42. Ethernet Controller Management Interface Timing 375 MHz clock, the maximum frequency is 11.7 MHz and the minimum frequency is 1.7 MHz.

1. The value depends on the source clock. For example, for a source clock of 267 MHz, the delay is 70 ns. For a source clock of

333 MHz, the delay is 58 ns.

2.7.10.2 MII Transmit AC Timing Specifications

Table 43 provides the MII transmit AC timing specifications. Figure 26 shows the MII transmit AC timing diagram.

2.7.10.3 MII Receive AC Timing Specifications

Table 44 provides the MII receive AC timing specifications. Figure 25. MII Management Interface Timing Table 43. MII Transmit AC Timing Specifications Notes: 1. Typical TX_CLK period (tMTX) for 10 Mbps is 400 ns and for 100 Mbps is 40 ns.

1. Program GCR4 as 0x00030CC3.

Figure 26. MII Transmit AC Timing Table 44. MII Receive AC Timing Specifications

Figure 27 provides the AC test load. Figure 28 shows the MII receive AC timing diagram.

2.7.10.4 RMII Transmit and Receive AC Timing Specifications

Table 45 provides the RMII transmit and receive AC timing specifications. Notes: 1. Typical RX_CLK period (tMRX) for 10 Mbps is 400 ns and for 100 Mbps is 40 ns.

1. Program GCR4 as 0x00030CC3.

Figure 27. AC Test Load Figure 28. MII Receive AC Timing Table 45. RMII Transmit and Receive AC Timing Specifications Table 44. MII Receive AC Timing Specifications (continued)

Figure 29 shows the RMII transmit and receive AC timing diagram. Figure 30 provides the AC test load.

2.7.10.5 SMII AC Timing Specification

Figure 31 provides the AC test load. Figure 29. RMII Transmit and Receive AC Timing Figure 30. AC Test Load Table 46. SMII Mode Signal Timing

1. Measured using a 5 pF load.
2. Measured using a 15 pF load
3. REF_CLK duty cycle is TBD.

Figure 31. SMII Mode Signal Timing

2.7.10.6 RGMII AC Timing Specifications

Table 47 presents the RGMII AC timing specifications for applications requiring an on-board delayed clock. Table 48 presents the RGMII AC timing specification for applications required non-delayed clock on board. Table 47. RGMII with On-Board Delay AC Timing Specifications Notes: 1. At recommended operating conditions with LV DD of 2.5 V +/- 5%.

1. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns will

be added to the associated clock signal.

1. For 10 and 100 Mbps, tRGT scales to 400 ns +/- 40 ns and 40 ns +/- 4 ns, respectively.
2. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long
3. Duty cycle reference is LVdd/2.
4. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.
5. GCR4 should be programmed as 0x00001004.

Table 48. RGMII with No On-Board Delay AC Timing Specifications

2.7.11 ATM/UTOPIA Timing

Table 49 provides the UTOPIA input and output AC timing specifications. Figure 33 provides the AC test load for the UTOPIA. Figure 34 shows the UTOPIA timing with external clock. Figure 35 shows the UTOPIA timing with internal clock. Table 49. UTOPIA AC Timing Specifications apply when the falling edge is the active edge. Figure 33. UTOPIA AC Test Load Figure 34. UTOPIA AC Timing (External Clock) Figure 35. UTOPIA AC Timing (Internal Clock)

2.7.12 SPI Timing

Table 49 provides the SPI input and output AC timing specifications. Figure 36 provides the AC test load for the SPI. Figure 36. SPI AC Test Load the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. Figure 37 shows the SPI timings in slave mode (external clock). Figure 37. SPI AC Timing in Slave Mode (External Clock) Figure 38 shows the SPI timings in master mode (internal clock). Table 50. SPI AC Timing Specifications 1

1. Output specifications are measured from the 50 percent level of the rising edge of CLKIN to the 50 percent level of the signal.

Timings are measured at the pin.

1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs

(NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X). Note: The clock edge is selectable on SPI.

Figure 38. SPI AC Timing in Master Mode (Internal Clock)

2.7.13 GPIO Timing

Figure 39 shows the GPIO timing. Table 51. GPIO Timing Figure 39. GPIO Timing Note: The clock edge is selectable on SPI.

2.7.14 EE Signals

Figure 40 shows the signal behavior of the EE pins.

2.7.14.1 JTAG Signals

Table 52. EE Pin Timing Notes: 1. The ratio between the core clock and CLKOUT is configured during power-on-reset.

1. Refer to Table 1-4 on page 1-6 for details on EE pin functionality.

Figure 40. EE Pin Timing Table 53. JTAG Timing Note: All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port. Figure 41. Test Clock Input Timing

3 Hardware Design Considerations

The following sections discuss areas to consider when the MSC8144 device is designed into a system.

3.1 Start-up Sequencing Recommendations

3.1.1 Power-on Sequence

 There are no dependencies in power-on/power-off sequence between V DDM3 and VDD supplies. VDDRIOPLL and other MSC8144 supplies. V DDPLL should be coupled with the VDD power rail with extremely low impedance path. power-up should be with slew rate less than 4V/ns.  VDDDDR and MVREF coupled one to another. MVREF should be either at same time or after VDDDDR. Note: 1. This recommended power sequencing is different from the MSC8122/MSC8126.

1. If no pins that require VDDGE1 as a reference supply are used (see Table 1), VDDGE1 can be tied to GND.
2. If no pins that require VDDGE2 as a reference supply are used (see Table 1), VDDGE2 can be tied to GND.
3. If the DDR interface is not used, VDDDDR and MVREF can be tied to GND.
4. If the M3 memory is not used, VDDM3, VDDM3IO, and V25M3 can be tied to GND.
5. If the RapidIO interface is not used, VDDSX, VDDSXP, and VDDRIOPLL can be tied to GND.

Figure 45. VDDM3, VDDM3IO and V25M3 Power-on Sequence

3.1.2 Start-Up Timing

Section 2.7.1 describes the start-up timing.

3.2 Power Supply Design Considerations

3.2.1 PLL Supplies

DDPLL inputs. These traces should be short and direct. Figure 46. PLL Supplies

3.2.2 Other Supplies

3.3 Connectivity Guidelines

connections in this discussion.

1. GND indicates using a 10 k Ω pull-down resistor (recommended) or a direct connection to the ground plane. Direct

1. V DD indicates using a 10 kΩ pull-up resistor (recommended) or a direct connection to the appropriate power supply.
2. Mandatory use of a pull-up or pull-down resistor it is clearly indicated as “pull-up/pull-down”.
3. NC indicates “not connected” and mean s do not connect anything to the pin.
4. The phrase “in use” indicates a typical pin connection for the required function.

subset interface connection.

3.3.1 DDR Memory Related Pins

This section discusses the various scenarios that can be used with DDR1 and DDR2 memory. of strobes in DDR1), please refer to Table 54.

3.3.1.1 DDR Interface Is Not Used

Table 54. Connectivity of DDR Related Pins When the DDR Interface Is Not Used Register (SCCR[CLK!11DIS]). See Chapter 7, Clocks, in the MSC8144 Reference Manual for details.

Table 55 lists unused pin connection when using 16-bit DDR memory. The 16 most significant data lines are not used.

3.3.1.3 ECC Unused Pin Connections

the correct pin connections. Table 55. Connectivity of DDR Related Pins When Using 16-bit DDR Memory Only Table 56. Connectivity of Unused ECC Mechanism Pins

3.3.2 Serial RapidIO Interface Related Pins

3.3.2.1 Serial RapidIO interface Is Not Used

3.3.2.2 Serial RapidIO Specific Lane Is Not Used

Table 57. Connectivity of Serial RapidIO Interface Related Pins When the RapidIO Interface Is Not Used Table 58. Connectivity of Serial RapidIO Related Pins When Specific Lane Is Not Used Note: The x indicates the lane number {0,1,2,3} for all unused lanes.

3.3.3 M3 Memory Related Pins

Table 59. Connectivity of M3 Related Pins When M3 Memory Is Not Used

3.3.4 Ethernet Related Pins

3.3.4.1 Ethernet Controller 1 (GE1) Related Pins

used, connect the pin as required to support that function.

3.3.4.1.1 GE1 Interface Is Not Used

3.3.4.1.2 Subset of GE1 Pins Required

that VDDGE1 is tied to either 2.5 V or 3.3 V . Table 60. Connectivity of GE1 Related Pins When the GE1 Interface Is Not Used Table 61. Connectivity of GE1 Related Pins When only a subset of the GE1 Interface Is required

3.3.4.2 Ethernet Controller 2 (GE2) Related Pins

used, connect the pin as required to support that function.

3.3.4.2.1 GE2 interface Is Not Used

3.3.4.2.2 Subset of GE2 Pins Required

and that VDDGE2 is tied to either 2.5 V or 3.3 B. Table 62. Connectivity of GE2 Related Pins When the GE2 Interface Is Not Used Table 63. Connectivity of GE1 Related Pins When only a subset of the GE1 Interface Is required Table 61. Connectivity of GE1 Related Pins When only a subset of the GE1 Interface Is required (continued)

3.3.4.3 GE1 and GE2 Management Pins

is, VDDGE2 is connected to GND), Table 64 lists the recommended management pin connections.

3.3.5 UTOPIA Related Pins

the alternate function is used, connect that pin as required to support the selected function. Table 64. Connectivity of GE Management Pins When GE1 and GE2 Are Not Used Table 65. Connectivity of UTOPIA Related Pins When UTOPIA Interface Is Not Used Table 63. Connectivity of GE1 Related Pins When only a subset of the GE1 Interface Is required (continued)

3.3.6 TDM Interface Related Pins

to support the selected function.

3.3.7 PCI Related Pins

specified pin is not used. If the alternate function is used, connect that pin as required to support the selected function. Table 66. Connectivity of TDM Related Pins When TDM Interface Is Not Used

1. In case of subset of TDM interface usage pleas e make sure to disable unused TDM modules. See Chapter 20, TDM, in the

MSC8144 Reference Manual for details. Table 67. Connectivity of PCI Related Pins When PCI Is Not Used

3.3.8 Miscellaneous Pins

3.4 External DDR SDRAM Selection

Table 68. Connectivity of Individual Pins When They Are Not Required SCL See the GPIO connectivity guidelines in this table. SDA See the GPIO connectivity guidelines in this table. IRQ[0–15] See the GPIO connectivity guidelines in this table. TMR[0–4] See the GPIO connectivity guidelines in this table. URXD See the GPIO connectivity guidelines in this table. UTXD See the GPIO connectivity guidelines in this table. Note: When using I/O multiplexing mode 5 or 6, tie the TD M7TSYN/PCI_AD4 signal (ball number AC9) to GND.

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1

Ordering Information

3.5 Thermal Considerations

An estimation of the chip-junction temperature, TJ, in °C can be obtained from the following: TJ = TA + (RθJA × PD) Equation 1 where TA = ambient temperature near the package (°C) RθJA = junction-to-ambient thermal resistance (°C/W) PD = PINT + PI/O = power dissipation in the package (W) PINT = IDD × VDD = internal power dissipation (W) PI/O = power dissipated from device on output pins (W) The power dissipation values for the MSC8144 are listed in Table 5. The ambient temperature for the device is the air temperature in the immediate vicinity that would cool the device. The junction-to-ambient thermal resistances are JEDEC standard values that provide a quick and easy estimation of thermal performance. There are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. The value that more closely approximates a specific application depends on the power dissipated by other components on the printed circuit board (PCB). The value obtained using a single layer board is appropriate for tightly packed PCB configurations. The value obtained using a board with internal planes is more appropriate for boards with low power dissipation (less than 0.02 W/cm 2 with natural convection) and well separated components. Based on an estimation of junction temperature using this technique, determine whether a more detailed thermal analysis is required. Standard thermal management techniques can be used to maintain the device thermal junction temperature below its maximum. If TJ appears to be too high, either lower the ambient temperature or the power dissipation of the chip. You can verify the junction temperature by measuring the case temperature using a small diameter thermocouple (40 gauge is recommended) or an infrared temperature sensor on a spot on the device case that is painted black. The MSC8144 device case surface is too shiny (low emissivity) to yield an accurate infrared temperature measurement. Use the following equation to determine T TJ = TT + (θJA × PD) Equation 2 where TT = thermocouple (or infrared) temperature on top of the package ( °C) θJA = thermal characterization parameter (°C/W) PD = power dissipation in the package (W)

4 Ordering Information

Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order. Part Package Type Spheres Core Voltage Operating Temperature Core Frequency (MHz) Order Number MSC8144 Flip Chip Plastic Ball Grid Array (FC-PBGA) Lead-free 1.0 V –40° to 105°C 800 TBD 0° to 90°C 1000 TBD

Package Information

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 77

5 Package Information

6 Product Documentation

 MSC8144 Technical Data Sheet (MSC8144). Details the signals, AC/DC characteristics, clock signal characteristics, package and pinout, and electrical design considerations of the MSC8144 device.  MSC8144 Reference Manual (MSC8144RM). Includes functional descriptions of the extended cores and all the internal subsystems including configuration and programming information.  Application Notes. Cover various programming topics related to the StarCore DSP core and the MSC8144 device.  SC3400 DSP Core Reference Manual. Covers the SC3400 core architecture, control registers, clock registers, program control, and instruction set.  MSC8144 SC3400 DSP Core Subsystem Reference Manual. Covers core subsystem architecture, functionality, and registers. Figure 47. MSC8144 Mechanical Information, 783-ball FC-PBGA Package

1. All dimensions in millimeters.
2. Dimensioning and tolerancing
3. Maximum solder ball diameter

measured parallel to Datum A.

1. Datum A, the seating plane, is
2. Capacitors may not be present
3. Caution must be taken not to

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1

Revision History

7 Revision History

Table 69 provides a revision history for this data sheet. Table 69. Document Revision History 0 Feb. 2007  Initial public release. 1 Apr. 2007  Adds new I/O multiplexing mode 7 that supports POS functionality.  Updates reference voltage supply for pins G5, H7, and H8 in Table 1.  Updates start-up timing recommendations with regard to TRST and M3_RESET in Section 2.7.1.  Adds input clock duty cycles in Table 20.  Updates PCI AC timings in Table 38.  Removes UTOPIA internal clock specifications in Table 49.  Updates JTAG timings in Table 53.  Clarifies connectivity guidelines for Ethernet pins in Section 3.3.4.  Miscellaneous pin connectivity guidelines were updated in Table 68.  Updates name of core subsystem reference manual.

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 79

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