MSC8126VT8000

MSC8126 FREESCALE | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 48

Technical content

Data Sheet: Document Number: MSC8126 Rev. 13, 12/2007 © Freescale Semiconductor, Inc., 2004, 2007. All rights reserved. MSC8126 FC PBGA–431 20 mm × 20 mm

• Four StarCore™ SC140 DSP extended cores, each with an SC140 DSP core, 224 Kbyte of internal SRAM M1 memory (1436 Kbyte total), 16 way 16 Kbyte instruction cache (ICache), four-entry write buffer, external cache support, programmable interrupt controller (PIC), local interrupt controller (LIC), and low-power Wait and Stop processing modes.  475 Kbyte M2 memory for critical data/temporary data buffering.  4 Kbyte boot ROM.  M2-accessible multi-core MQBus connecting the M2 memory with all four cores, operating at the core frequency, with data bus access of up to 128-bit reads and up to 64-bit writes, central efficient round-robin arbiter for core access to the bus, and atomic control of M2 memory access by the cores and local bus.  Internal PLL configured are reset by configuration signal values.  60x-compatible system bus with 64 or 32 bit data and 32-bit address bus, support for multi-master designs, four-beat burst transfers (eight-beat in 32-bit data mode), port size of 64/32/16/8 bits controlled by the internal memory controller,.access to external memory or peripherals, access by an external host to internal resources, slave support with direct access to internal resources including M1 and M2 memories, and on-device arbitration for up to four master devices.  Direct slave interface (DSI) using a 32/64-bit slave interface with 21–25 bit addressing and 32/64-bit data transfers, direct access by an external host to internal/external resources, synchronous or asynchronous accesses with burst capability in synchronous mode, dual or single strobe mode, write and read buffers to improve host bandwidth, byte enable signals for 1/2/4/8-byte write granularity, sliding window mode for access using a reduced number of address pins, chip ID decoding to allow one CS signal to control multiple DSPs, broadcast mode to write to multiple DSPs, and big-endian/little-endian/munged support.  Three mode signal multiplexing: 64-bit DSI/32-bit system bus, 32-bit DSI/64-bit system bus, or 32-bit DSI/32-bit system bus.  Flexible memory controller with three UPMs, a GPCM, a page-mode SDRAM machine, glueless interface to a variety of memories and devices, byte enables for 64-/32-bit bus widths, 8 memory banks for external memories, and 2 memory banks for IPBus peripherals and internal memories.  Multi-channel DMA controller with 16 time-multiplexed single channels, up to four external peripherals, DONE or DRACK protocol for two external peripherals,.service for up to 16 internal requests from up to 8 internal FIFOs per channel, FIFO generated watermarks and hungry requests, priority-based time-multiplexing between channels using 16 internal priority levels or round-robin time-multiplexing between channels, flexible channel configuration with connection to local bus or system bus, and flyby transfer support that bypasses the FIFO.  Up to four independent TDM modules with programmable word size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion, up to 128 Mbps data rate for all channels, with glueless interface to E1 or T1 framers, and can interface with H-MVIP/H.110 devices, TSI, and codecs such as AC-97.  Ethernet controller: support for 10/100 Mbps MII/RMII/SMII including full- and half-duplex operation, full-duplex flow controls, out-of-sequence transmit queues, programmable maximum frame length including jumbo frames and VLAN tags and priority, retransmission after collision, CRC generation and verification of inbound/outbound packets, address recognition (including exact match, broadcast address, individual hash check, group hash check, and promiscuous mode), pattern matching, insertion with expansion or replacement for transmit frames, VLAN tag insertion, RMON statistics, local bus master DMA for descriptor fetching and buffer access, and optional multiplexing with GPIO (MII/RMII/SMII) or DSI/system bus signals lines (MII/RMII).  UART with full-duplex operation up to 6.25 Mbps.  Up to 32 general-purpose input/output (GPIO) ports. 2C interface that allows booting from EEPROM devices.  Two timer modules, each with sixteen configurable 16-bit timers.  Eight programmable hardware semaphores.  Global interrupt controller (GIC) with interrupt consolidation and routing to INT_OUT, NMI_OUT, and the cores; thirty-two virtual maskable interrupts (8 per core) and four virtual NMI (one per core) that can be generated by a simple write access.  Boot options: external memory, external host, UART, TDM, or I2C.  VCOP with fully programmable feed-forward channel decoding, feed-forward channel equalization and traceback sessions. Up to 400 3GPP 12.2 kbps AMR channels (channel decoding, number of channels linear to frequency). Up to 200 blind transport format detect (BTFD) channels according to the 3GPP standard. Number of channels linear to frequency.  TCOP with full support for 3GPP and CDMA2000 standards in Turbo decode; up to 20 turbo-coding 384 kbps channels; 8 state PCCC with polynomial as supported by the 3G standards; iterative decoding structure based on Maximum A-Posteriori probability (MAP), with calculations performed in the LOG domain. Quad Digital Signal Processor

Figure 1. MSC8126 Block Diagram Figure 2. StarCore SC140 DSP Extended Core Block Diagram

32 Timers

4 TDMs

8 Hardware

Notes: 1. The arrows show the data transfer direction.

1. The QBus interface includes a bus switch, write buffer, fetch unit, and a control unit that defines

four QBus banks. In addition, the QBC handles internal memory contentions.

MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Pin Assignments Freescale Semiconductor4

1 Pin Assignments

This section includes diagrams of the MSC8126 package ball grid array layouts and pinout allocation tables.

1.1 FC-PBGA Ball Layout Diagrams

Top and bottom views of the FC-PBGA package are shown in Figure 3 and Figure 4 with their ball location index numbers.

Figure 3. MSC8126 Package, Top View

31 BM0 ABB VDD

27 VDD CLKIN BM2 DBG VDD GND VDD TT3 PSDA10 BCTL1 GPIO23 GND GPIO25 A30

29 GND GND GND VDDH GND GND CS3 VDDH A27 A25 A22

0 HBCS GND GND HRDS BG HCS CS0 PSDWE GPIO26 A23 A20

1 HCLKIN GND GNDSYN VCCSYN GND GND TA BR TEA PSD

4 TSZ1 TSZ3 GBL VDD VDD VDD TT0 DP7 DP6 DP3 TS DP2 A17 A18 A16

5 TSZ0 TSZ2 TBST VDD D16 TT1 D21 D23 DP5 DP4 DP1 D30 GND A15 A14

Figure 4. MSC8126 Package, Bottom View

31 VDD VDD PWE0 HA17 HA23 HA25 HA27 HA24

30 POE PWE1 PWE3 HA16 HA21 HA15

28 VDDH VDDH HA11 HA14 HA12

0 VDDH PWE2 HD24 HD29 HD30 HD26

3 HD23 HD25 HD27 HD20

6 HD22 GND VDDH HD18

7 HD0 HD1 HD21 HD17

1.2 Signal List By Ball Location

Table 1. MSC8126 Signal Listing by Ball Designator

Table 1. MSC8126 Signal Listing by Ball Designator (continued)

Electrical Characteristics

MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Freescale Semiconductor 13

2 Electrical Characteristics

This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications. For additional information, see the MSC8126 Reference Manual.

2.1 Maximum Ratings

In calculating timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. Table 2 describes the maximum electrical ratings for the MSC8126. CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or V DD). Table 2. Absolute Maximum Ratings Notes: 1. Functional operating conditions are given in Table 3.

1. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond

the listed limits may affect device reliability or cause permanent damage.

1. Section 3.5 , Thermal Considerations includes a formula for computing the chip junction temperature (T J).

MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13

2.2 Recommended Operating Conditions

Table 3 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed.

2.3 Thermal Characteristics

Table 4 describes thermal characteristics of the MSC8126 for the FC-PBGA packages. Section 3.5, Thermal Considerations provides a detailed explanation of these characteristics. Table 3. Recommended Operating Conditions Table 4. Thermal Characteristics for the MSC8126

1. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
2. Per JEDEC JESD51-6 with the board horizontal.
3. Thermal resistance between the die and the printed circuit boar d per JEDEC JESD 51-8. Boar d temperature is measured on

the top surface of the board near the package.

1. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
2. Thermal characterization parameter indi cating the temperature difference between package top and the junction temperature

MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Freescale Semiconductor 15

2.4 DC Electrical Characteristics

This section describes the DC electrical characteristics for the MSC8126. The measurements in Table 5 assume the following system conditions: T A = 25 °C  VDD = — 400 MHz = 1.14–1.26 V DC — 500 MHz = 1.16–1.24 V DC  VDDH = 3.3 V ± 5% VDC  GND = 0 VDC Note: The leakage current is measured for nominal VDDH and VDD. Table 5. DC Electrical Characteristics Notes: 1. See Figure 5 for undershoot and overshoot voltages.

1. Not tested. Guaranteed by design.
2. Measured for 1.2 V core at 25°C junction temperature.
3. The typical power values were measured using an EFR code with the device running at a junction temperature of 25°C. No

this document and in MSC8102, MSC8122, and MSC8126 Thermal Management Design Guidelines (AN2601).

MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13

2.5 AC Timings

The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs. When systems such as DSP farms are developed using the DSI, use a device loading of 4 pF per pin. AC timings are based on a 20 pF load, except where noted otherwise, and a 50 Ω transmission line. For loads smaller than 20 pF, subtract 0.06 ns per pF down to 10 pF load. For loads larger than 20 pF, add 0.06 ns for SIU/Ethernet/DSI delay and 0.07 ns for GPIO/TDM/timer delay. When calculating overall loading, also consider additional RC delay.

2.5.1 Output Buffer Impedances

2.5.2 Start-Up Timing

Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.5.3 describes the clocking characteristics. Section 2.5.4 describes the reset and power-up characteristics. You must use the following guidelines when starting up an MSC8126 device:  PORESET and TRST must be asserted externally for the duration of the power-up sequence. See Table 11 for timing.  If possible, bring up the VDD and VDDH levels together. For designs with separate power supplies, bring up the VDD levels and then the VDDH levels (see Figure 7).  CLKIN should start toggling at least 16 cycles (starting after VDDH reaches its nominal level) before PORESET deassertion to guarantee correct device operation (see Figure 6 and Figure 7).  CLKIN must not be pulled high during VDDH power-up. CLKIN can toggle during this period. Note: See Section 3.1 for start-up sequencing recommendations and Section 3.2 for power supply design recommendations. The following figures show acceptable start-up sequence examples. Figure 6 shows a sequence in which VDD and VDDH are raised together. Figure 7 shows a sequence in which VDDH is raised after VDD and CLKIN begins to toggle as VDDH rises. Figure 5. Overshoot/Undershoot Voltage for VIH and VIL Table 6. Output Buffer Impedances Note: These are typical values at 65°C. The impedance may vary by ±25% depending on device proce ss and operating temperature.

MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 In all cases, the power-up sequence must follow the guidelines shown in Figure 8. The following rules apply: 1. During time interval A, VDDH should always be equal to or less than the VDD/VCCSYN voltage level. The duration of interval A should be kept below 10 ms. 2. The duration of timing interval B should be kept as small as possible and less than 10 ms.

2.5.3 Clock and Timing Signals

The following sections include a description of clock signal characteristics. Table 7 shows the maximum frequency values for internal (Core, Reference, Bus, and DSI) and external (CLKIN and CLKOUT) clocks. The user must ensure that maximum frequency values are not exceeded. Figure 8. Power-Up Sequence for VDDH and VDD/VCCSYN Table 7. Maximum Frequencies Table 8. Clock Frequencies

400 MHz Device 500 MHz Device

MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Freescale Semiconductor 19

2.5.4 Reset Timing

The MSC8126 has several inputs to the reset logic:  Power-on reset ( PORESET)  External hard reset ( HRESET)  External soft reset ( SRESET)  Software watchdog reset  Bus monitor reset  Host reset command through JTAG All MSC8126 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset. The reset status register indicates the most recent sources to cause a reset. Table 10 describes the reset sources. Table 11 summarizes the reset actions that occur as a result of the different reset sources. Table 9. System Clock Parameters

1. Not tested. Guaranteed by design.

Table 10. Reset Sources bits port or a System Bus 64 bits port are configured only when PORESET is asserted. driven, the SC140 extended cores are reset, and system configuration is maintained. enabled software watchdog event then generates an internal hard reset sequence. enabled bus monitor event then generates an internal hard reset sequence. soft reset signal and an internal soft reset sequence is generated.

MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13

2.5.4.1 Power-On Reset (PORESET ) Pin

Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 16 CLKIN cycles after VDD and VDDH are both at their nominal levels.

2.5.4.2 Reset Configuration

The MSC8126 has two mechanisms for writing the reset configuration:  Through the direct slave interface (DSI)  Through the system bus. When the reset configuration is written through the system bus, the MSC8126 acts as a configuration master or a configuration slave. If configuration slave is selected, but no special configuration word is written, a default configuration word is applied. Fourteen signal levels (see Chapter 1 for signal description details) are sampled on PORESET deassertion to define the Reset Configuration Mode and boot and operating conditions:  RSTCONF  CNFGS  DSISYNC  DSI64  CHIP_ID[0–3]  BM[0–2]  SWTE  MODCK[1–2] Table 11. Reset Actions for Each Reset Source Section 2.5.4.1 for details).

MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Freescale Semiconductor 21

2.5.4.3 Reset Timing Tables

Table 12 and Figure 9 describe the reset timing for a reset configuration write through the direct slave interface (DSI) or through the system bus. Table 12. Timing for a Reset Configuration Write through the DSI or System Bus

1 Required external PORESET duration minimum

2 Delay from deassertion of external PORESET

3 Delay from de-assertion of internal PORESET to SPLL lock

5 Delay from SPLL to HRESET

6 Delay from SPLL lock to SRESET deassertion

7 Setup time from assertion of RSTCONF, CNFGS, DSISYNC, DSI64,

8 Hold time from deassertion of PORESET to deassertion of RSTCONF,

Note: Timings are not tested, but are guaranteed by design. Figure 9. Timing Diagram for a Reset Configuration Write

MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13

2.5.5 System Bus Access Timing

2.5.5.1 Core Data Transfers

Generally, all MSC8126 bus and system output signals are driven from the rising edge of the reference clock (REFCLK). The REFCLK is the CLKIN signal. Memory controller signals, however, trigger on four points within a REFCLK cycle. Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge of REFCLK (and T3 at the falling edge), but the spacing of T2 and T4 depends on the PLL clock ratio selected, as Table 13 shows. Figure 10 is a graphical representation of Table 13. Table 13. Tick Spacing for Memory Controller Signals Figure 10. Internal Tick Spacing for Memory Controller Signals

MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Freescale Semiconductor 23 The UPM machine and GPCM machine outputs change on the internal tick selected by the memory controller configuration. The AC timing specifications are relative to the internal tick. SDRAM machine outputs change only on the REFCLK rising edge. Table 14. AC Timing for SIU Inputs

12 Data bus set-up time before REFCLK rising edge in Normal mode

1 Data bus set-up time before the 50% level of the REFCLK rising edge

141 DP set-up time before the 50% level of the REFCLK rising edge

16 PUPMWAIT signal set-up time before the 50% level of the REFCLK

17 IRQx

Notes: 1. Timings specifications 13 and 14 in non-pipeline mode are more restrictive than MSC8102 timings.

1. Values are measured from the 50% TTL transition level relative to the 50% level of the REFCLK rising edge.

MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Table 15. AC Timing for SIU Outputs

31 PSDVAL /TEA/TA max delay from the 50% level of the REFCLK

34 Memory controller signals/ALE/CS[0–4]

1. The load for specification 30 is 10 pF. The load for the other specifications in this table is 20 pF. For a 15 pF load, subtract 0.3
2. The maximum bus frequency depends on the mode:
3. In 60x-compatible mode connected to another MSC8126 device , the frequency is determined by adding the input and output

influences that can affect timing, such as on- board clock skews, on-board noise delays, and so on.  In single-master mode, the frequency depends on t he timing of the devices connected to the MSC8126. SIUMCR[BDD] bit. See the SIU chapter in the MSC8122 Reference Manual for details.

MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Freescale Semiconductor 25 Figure 11. SIU Timing Diagram

MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13

2.5.5.2 CLKIN to CLKOUT Skew

Table 17 describes the CLKOUT-to-CLKIN skew timing. For designs that use the CLKOUT synchronization mode, use the skew values listed in Table 16 to adjust the rise-to-fall timing values specified for CLKIN synchronization. Figure 12 shows the relationship between the CLKOUT and CLKIN timings. Table 16. CLKOUT Skew Notes: 1. A positive number indicates that CLKOUT precedes CLKIN, A negative number indicates that CLKOUT follows CLKIN.

1. Skews are measured in clock mode 29, with a CLKIN:CLKOUT ratio of 1:1. The same skew is valid for all clock modes.
2. CLKOUT skews are measured using a load of 10 pF.
3. CLKOUT skews and phase are not measured for 500/166 Mh z parts because these parts only use CLKIN mode.

Figure 12. CLKOUT and CLKIN Signals.

MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Freescale Semiconductor 27

2.5.5.3 DMA Data Transfers

Table 17 describes the DMA signal timing. The DREQ signal is synchronized with REFCLK. To achieve fast response, a synchronized peripheral should assert DREQ according to the timings in Table 17. Figure 13 shows synchronous peripheral interaction. Table 17. DMA Signals

39 DONE

Figure 13. DMA Signals

MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13

2.5.6 DSI Timing

The timings in the following sections are based on a 20 pF capacitive load.

2.5.6.1 DSI Asynchronous Mode

Table 18. DSI Asynchronous Mode Timing

102 Read/Write data strobe deassertion width:

106 Read/Write data strobe assertion to HTA

108 Read/Write data strobe assertion to HTA valid2

109 Read/Write data strobe deassertion to output HTA high impedance. 110 Read/Write data strobe deassertion to output HTA deassertion. 111 Read/Write data strobe deassertion to output HTA high impedance.

202 Host data input hold time after write data strobe deassertion

Notes: 1. Attributes refers to the following signals: HCS , HA[11–29], HCID[0–4], HDST, HRW, HRDS , and HWBSn.

1. This specification is tested in dual-strobe mode. Timing in single -strobe mode is guaranteed by design.
2. All values listed in this table are tested or guaranteed by design.

MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Freescale Semiconductor 31

2.5.6.2 DSI Synchronous Mode

Table 19. DSI Inputs—Synchronous Mode Notes: 1. Values are based on a frequency range of 18–100 MHz.

1. Refer to Table 7 for HCLKIN frequency limits.

Table 20. DSI Outputs—Synchronous Mode Figure 17. DSI Synchronous Mode Signals Timing Diagram

MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13

2.5.7 TDM Timing

Table 21. TDM Timing

300 TDMxRCLK/TDMxTCLK TC 1 16 — ns

305 TDMxTCLK high to TDMxTDAT/TDMxRCLK output active

1. Values are based on 20 pF capacitive load.
2. When configured as an output, TDMxRCLK acts as a second data link. See the MSC8126 Reference Manual for details.
3. CLKOUT synchronization is not supported for cores operating at above 400 MHz.
4. Values are based on 10 pF capacitive load.

Figure 18. TDM Inputs Signals Figure 19. TDM Output Signals

2.5.8 UART Timing

Table 22. UART Timing

401 URXD and UTXD inputs rise/fall time 10 ns

402 UTXD output rise/fall time 10 ns

Figure 20. UART Input Timing Figure 21. UART Output Timing

2.5.9 Timer Timing

2.5.10 Ethernet Timing

2.5.10.1 Management Interface Timing

Table 23. Timer Timing

503 TIMERx Propagations delay from its clock input

Figure 22. Timer Timing Table 24. Ethernet Controller Management Interface Timing

801 ETHMDIO to ETHMDC rising edge set-up time 10 — ns

802 ETHMDC rising edge to ETHMDIO hold time 10 — ns

Figure 23. MDIO Timing Relationship to MDC

2.5.10.2 MII Mode Timing

2.5.10.3 RMII Mode

Table 25. MII Mode Signal Timing

805 ETHTX_CLK to ETHTX_EN, ETHTXD[0–3], ETHTX_ER output delay

Figure 24. MII Mode Signal Timing Table 26. RMII Mode Signal Timing

806 ETHTX_EN,ETHRXD[0–1], ETHCRS_DV, ETHRX_ER to ETHREF_CLK rising

807 ETHREF_CLK rising edge to ETHRXD[0–1], ETHCRS_DV, ETHRX_ER hold

Figure 25. RMII Mode Signal Timing

2.5.10.4 SMII Mode

2.5.11 GPIO Timing

Table 27. SMII Mode Signal Timing

810 ETHCLOCK rising edge to ETHSYNC, ETHTXD output delay

Notes: 1. Measured using a 5 pF load.

1. Measured using a 15 pF load.

Figure 26. SMII Mode Signal Timing Table 28. GPIO Timing

2.5.12 EE Signals

Figure 28 shows the signal behavior of the EE pins.

2.5.13 JTAG Signals

Figure 27. GPIO Timing Table 29. EE Pin Timing

65 EE0 (input) Asynchronous 4 core clock periods

66 EE1 (output) Synchronous to Core clock 1 core clock period

Notes: 1. The core clock is the SC140 core clock. The ratio between t he core clock and CLKOUT is configured during power-on-reset.

1. Refer to Table 1-4 on page 1-6 for details on EE pin functionality.

Figure 28. EE Pin Timing Table 30. JTAG Timing

712 TRST

Note: All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port. Figure 29. Test Clock Input Timing Diagram Figure 30. Boundary Scan (JTAG) Timing Diagram Table 30. JTAG Timing (continued)

MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Hardware Design Considerations Freescale Semiconductor40

3 Hardware Design Considerations

The following sections discuss areas to consider when the MSC8126 device is designed into a system.

3.1 Start-up Sequencing Recommendations

Use the following guidelines for start-up and power-down sequences: A s s e r t PORESET and TRST before applying power and keep the signals driven low until the power reaches the required minimum power levels. This can be implemented via weak pull-down resistors.  CLKIN can be held low or allowed to toggle during the beginning of the power-up sequence. However, CLKIN must start toggling before the deassertion of PORESET and after both power supplies have reached nominal voltage levels.  If possible, bring up VDD/VCCSYN and VDDH together. If it is not possible, raise VDD/VCCSYN first and then bring up VDDH. VDDH should not exceed VDD/VCCSYN until VDD/VCCSYN reaches its nominal voltage level. Similarly, bring both voltage levels down together. If that is not possible reverse the power-up sequence, with VDDH going down first and then VDD/VCCSYN. Note: This recommended power sequencing for the MSC8126 is different from the MSC8102. See Section 2.5.2 for start-up timing specifications. External voltage applied to any input line must not exceed the I/O supply VDDH by more than 0.8 V at any time, including during power-up. Some designs require pull-up voltages applied to selected input lines during power-up for configuration purposes. This is an acceptable exception to the rule. However, each such input can draw up to 80 mA per input pin per device in the system during start-up. During the power-up sequence, if V DD rises before VDDH (see Figure 6), current can pass from the VDD supply through the device ESD protection circuits to the VDDH supply. The ESD protection diode can allow this to occur when VDD exceeds VDDH by more than 0.8 V . Design the power supply to prevent or minimize this effect using one of the following optional methods:  Never allow V DD to exceed VDDH + 0.8V .  Design the V DDH supply to prevent reverse current flow by adding a minimum 10 Ω resistor to GND to limit the current. Such a design yields an initial VDDH level of VDD – 0.8 V before it is enabled. After power-up, VDDH must not exceed VDD/VCCSYN by more than 2.6 V .

3.2 Power Supply Design Considerations

When used as a drop-in replacement in MSC8102 applications or when implementing a new design, use the guidelines described in Migrating Designs from the MSC8102 to the MSC8122 (AN2716) and the MSC8126 Design Checklist (AN3374 for optimal system performance. MSC8122 and MSC8126 Power Circuit Design Recommendations and Examples (AN2937) provides detailed design information. See Section 2.5.2 for start-up timing specifications. Figure 33 shows the recommended power decoupling circuit for the core power supply. The voltage regulator and the decoupling capacitors should supply the required device current without any drop in voltage on the device pins. The voltage on the package pins should not drop below the minimum specified voltage level even for a very short spikes. This can be achieved by using the following guidelines:  For the core supply, use a voltage regulator rated at 1.2 V with nominal rating of at least 3 A. This rating does not reflect actual average current draw, but is recommended because it resists changes imposed by transient spikes and has better voltage recovery time than supplies with lower current ratings.

MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Hardware Design Considerations Freescale Semiconductor42

3.3 Connectivity Guidelines

Unused output pins can be disconnected, and unused input pins should be connected to the non-active value, via resistors to VDDH or GND, except for the following:  If the DSI is unused (DDR[DSIDIS] is set), HCS and HBCS must pulled up and all the rest of the DSI signals can be disconnected.  When the DSI uses synchronous mode, HTA must be pulled up. In asynchronous mode, HTA should be pulled either up or down, depending on design requirements.  HDST can be disconnected if the DSI is in big-endian mode, or if the DSI is in little-endian mode and the DCR[DSRFA] bit is set.  When the DSI is in 64-bit data bus mode and DCR[BEM] is cleared, pull up HWBS[1–3]/HDBS[1–3]/HWBE[1–3]/ HDBE[1–3] and HWBS[4–7]/HDBS[4–7]/HWBE[4–7]/HDBE[4–7]/PWE[4–7]/PSDDQM[4–7]/PBS[4–7].  When the DSI is in 32-bit data bus mode and DCR[BEM] is cleared, HWBS[1–3]/HDBS[1–3]/HWBE[1–3]/HDBE[1–3] must be pulled up.  When the DSI is in asynchronous mode, HBRST and HCLKIN should either be disconnected or pulled up.  When the DSI uses sliding window address mode (DCR[SLDWA] = 1), the external HA[11–13] signals must be connected (tied) to the correct voltage levels so that the host can perform the first access to the DCR. After reset, the DSI expects full address mode (DCR[SLDWA] = 0). The DCR address in the DSI memory map is 0x1BE000, which requires the following connections: — HA11 must be pulled high (1) — HA12 must be pulled high (1) — HA13 must be pulled low (0)  The following signals must be pulled up: HRESET, SRESET, ARTRY, TA, TEA, PSDVAL, and AACK.  In single-master mode (BCR[EBM] = 0) with internal arbitration (PPC_ACR[EARB] = 0): — BG, DBG, and TS can be left unconnected. — EXT_BG[2–3], EXT_DBG[2–3], and GBL can be left unconnected if they are multiplexed to the system bus functionality. For any other functionality, connect the signal lines based on the multiplexed functionality. — BR must be pulled up. — EXT_BR[2–3] must be pulled up if multiplexed to the system bus functionality.  If there is an external bus master (BCR[EBM] = 1): — BR, BG, DBG, and TS must be pulled up. — EXT_BR[2–3], EXT_BG[2–3], and EXT_DBG[2–3] must be pulled up if multiplexed to the system bus functionality.  In single-master mode, ABB and DBB can be selected as IRQ inputs and be connected to the non-active value. In other modes, they must be pulled up. Note: The MSC8126 does not support DLL-enabled mode. For the following two clock schemes, ensure that the DLL is disabled (that is, the DLLDIS bit in the Hard Reset Configuration Word is set).  If no system synchronization is required (for example, the design does not use SDRAM), you can use any of the available clock modes. I n t h e CLKIN synchronization mode, use the following connections: — Connect the oscillator output through a buffer to CLKIN. — Connect the CLKIN buffer output to the slave device (for example, SDRAM) making sure that the delay path between the clock buffer to the MSC8126 and the SDRAM is equal (that is, has a skew less than 100 ps). — Valid clock modes in this scheme are: 0, 7, 15, 19, 21, 23, 28, 29, 30, and 31. I n CLKOUT synchronization mode (for 1.2 V devices), CLKOUT is the main clock to SDRAM. Use the following connections: — Connect the oscillator output through a buffer to CLKIN. — Connect CLKOUT through a zero-delay buffer to the slave device (for example, SDRAM) using the following guidelines: – The maximum delay between the slave and CLKOUT must not exceed 0.7 ns.

Hardware Design Considerations MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Freescale Semiconductor 43 – The maximum load on CLKOUT must not exceed 10 pF. – Use a zero-delay buffer with a jitter less than 0.3 ns. — All clock modes are valid in this clock scheme. Note: See the Clock chapter in the MSC8122 Reference Manual for details.  If the 60x-compatible system bus is not used and SIUMCR[PBSE] is set, PPBS can be disconnected. Otherwise, it should be pulled up.  The following signals: SWTE, DSISYNC, DSI64, MODCK[1–2], CNFGS, CHIPID[0–3], RSTCONF and BM[0–2] are used to configure the MSC8126 and are sampled on the deassertion of the PORESET signal. Therefore, they should be tied to GND or VDDH or through a pull-down or a pull-up resistor until the deassertion of the PORESET signal.  When they are used, INT_OUT (if SIUMCR[INTODC] is cleared), NMI_OUT, and IRQxx (if not full drive) signals must be pulled up.  When the Ethernet controller is enab led and the SMII mode is selected, GPIO10 and GPIO14 must not be connected externally to any signal line. Note: For details on configuration, see the MSC8126 User’s Guide and MSC8126 Reference Manual. For additional information, refer to the MSC8126 Design Checklist (AN2903).

3.4 External SDRAM Selection

The external bus speed implemented in a system determines the speed of the SDRAM used on that bus. However, because of differences in timing characteristics among various SDRAM manufacturers, you may have use a faster speed rated SDRAM to assure efficient data transfer across the bus. For example, for 166 MHz operation, you may have to use 183 or 200 MHz SDRAM. Always perform a detailed timing analysis using the MSC8126 bus timing values and the manufacturer specifications for the SDRAM to ensure correct operation within your system design. The output delay listed in SDRAM specifications is usually given for a load of 30 pF. Scale the number to your specific board load using the typical scaling number provided by the SDRAM manufacturer.

MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13

Ordering Information

3.5 Thermal Considerations

An estimation of the chip-junction temperature, TJ, in °C can be obtained from the following: TJ = TA + (RθJA × PD) Eqn. 1 where TA = ambient temperature near the package (°C) RθJA = junction-to-ambient thermal resistance (°C/W) PD = PINT + PI/O = power dissipation in the package (W) PINT = IDD × VDD = internal power dissipation (W) PI/O = power dissipated from device on output pins (W) The power dissipation values for the MSC8126 are listed in Table 2-3. The ambient temperature for the device is the air temperature in the immediate vicinity that would cool the device. The junction-to-ambient thermal resistances are JEDEC standard values that provide a quick and easy estimation of thermal performance. There are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. The value that more closely approximates a specific application depends on the power dissipated by other components on the printed circuit board (PCB). The value obtained using a single layer board is appropriate for tightly packed PCB configurations. The value obtained using a board with internal planes is more appropriate for boards with low power dissipation (less than 0.02 W/cm2 with natural convection) and well separated components. Based on an estimation of junction temperature using this technique, determine whether a more detailed thermal analysis is required. Standard thermal management techniques can be used to maintain the device thermal junction temperature below its maximum. If T J appears to be too high, either lower the ambient temperature or the power dissipation of the chip. You can verify the junction temperature by measuring the case temperature using a small diameter thermocouple (40 gauge is recommended) or an infrared temperature sensor on a spot on the device case that is painted black. The MSC8126 device case surface is too shiny (low emissivity) to yield an accurate infrared temperature measurement. Use the following equation to determine TJ: TJ = TT + (θJA × PD) Eqn. 2 where TT = thermocouple (or infrared) temperature on top of the package (°C) θJA = thermal characterization parameter (°C/W) PD = power dissipation in the package (W) Note: See MSC8102, MSC8122, and MSC8126 Thermal Management Design Guidelines (AN2601/D).

4 Ordering Information

Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order. Part Package Type Spheres Core Voltage Operating Temperature Core Frequency (MHz) Order Number MSC8126 Flip Chip Plastic Ball Grid Array (FC-PBGA) Lead-free 1.2 V –40° to 105°C 400 MSC8126TVT6400 Lead-bearing MSC8126TMP6400 Lead-free 0° to 90°C 500 MSC8126VT8000 Lead-bearing MSC8126MP8000

Package Information

MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Freescale Semiconductor 45

5 Package Information

6 Product Documentation

 MSC8126 Technical Data Sheet (MSC8126). Details the signals, AC/DC characteristics, clock signal characteristics, package and pinout, and electrical design considerations of the MSC8126 device.  MSC8126 Reference Manual (MSC8126RM). Includes functional descriptions of the extended cores and all the internal subsystems including configuration and programming information.  Application Notes. Cover various programming topics related to the StarCore DSP core and the MSC8126 device.  SC140 DSP Core Reference Manual. Covers the SC3400 core architecture, control registers, clock registers, program control, and instruction set. Figure 35. MSC8126 Mechanical Information, 431-pin FC-PBGA Package

1. All dimensions in millimeters.
2. Dimensioning and tolerancing
3. Features are symmetrical about
4. Maximum solder ball diameter

measured parallel to Datum A.

1. Datum A, the seating plane, is
2. Parallelism measurement shall
3. Capacitors may not be present
4. Caution must be taken not to
5. FC CBGA (Ceramic) package

MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13

Revision History

7 Revision History

Table 31 provides a revision history for this data sheet. Table 31. Document Revision History 0 May 2004  Initial release. 1 Jun. 2004  Updated timing number 32b.  Updated DSI timing specifications. 2 Sep 2004  New orderable parts added with other core voltage and temperature options.  Updated thermal characteristics.  In Table 2-14, removed references to 30 pF.  Design guidelines and layout recommendations updated. 3 Nov. 2004  Added 500 MHz core and 166 MHz bus speed options.  Definitions of GPIO[27–28] updated. 2C timing changed to GPIO timing.  GPIO[27–28] connections updated. MWBEn replaced with correct name HWBEn. 4 Jan. 2005  Package type changed to FC-PBGA for all frequencies.  Low-voltage 300 MHz power changed to 1.1 V . H R E S E T and SRESET definitions updated.  Undershoot and overshoot values added for V DDH.  Design guidelines updated and reorganized. 5 May 2005  Multiple AC timing specifications updated. 6 May 2005  Multiple AC timing specifications updated. 7 Jul. 2005  Multiple AC timing specifications updated. 8 Jul. 2005  AC specification table layout modified. 9 Sep. 2005  ETHTX_EN type and TRST description updated.  Clock specifications updated.  Start-up sequence updated. 10 Oct 2005 V DDH + 10% changed to VDDH + 8% in Figure 2-1. V DDH +20% changed to VDDH + 17% in Figure 2-1. 11 Apr 2006  Reset timing updated to reflect actual values in Table 2-11. 13 Dec. 2007  Converted to new data sheet format.  Added PLL supply current to Table 5 in Section 2.4.  Added power-sequence guidelines to Sections 2.5.2.  Added CLKIN jitter characteristic specifications to Table 9.  Added additional guidelines to prevent reverse current to Section 3.1.  Added connectivity guidelines for DSI in sliding windows mode to Section 3.3.

MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Freescale Semiconductor 47

Document Number: MSC8126 Rev. 13 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale’s Environmental Products program, go to http://www.freescale.com/epp. Freescale™, the Freescale logo, CodeWarrior, StarCore, and QUICC Engine are trademarks of Freescale Semiconductor, Inc. RapidIO is a registered trademark of the RapidIO Trade Association. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2004, 2007. All rights reserved. How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516

2100 East Elliot Road

Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center

2 Dai King Street

Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 +1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com