MSC8101 FREESCALE | Alldatasheet
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© Freescale Semiconductor, Inc., 2004, 2005. All rights reserved. and the corresponding versions of the MSC8101 device. Table 1. MSC8101 Mask Numbers and Revisions Table 2. Silicon Errata timer advances N*1024 cycles.
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Workaround: Clear the SWRI bit in SYPCR to get data errors indication. parity, and for both PowerPC and Local buses. Bus Monitor Asserts Spurious TEA After Address Retry. and will assert TEA if there is no bus activity for a time equal to the expiration time. tems which include PowerSpan). Workaround: Use only a compliant external arbiter or the internal MSC8101 arbiter. memory access and the chip is programmed to single-MSC8101 mode (BCR[EBM]=0). Table 2. Silicon Errata (Continued)
- If the external master supports the ABB signal, do not use the bus busy disable
- If the external master does not support the ABB signal do one of the following:
externally. The DBB signal can either be connected or can be pulled up. ABB to VDD for half a clock cycle and then stop driving it (HIGH-Z). connected or can be pulled up. serted. Therefore the Internal (60x) slave will not assert AACK since TA was not asserted.
- Use pipeline depth of zero (BCR[PLDP]=1) when using an external 60x bus slave.
- Disable 60X bus monitor, SYPCR[PBME]=0.
- If the external 60x bus slave is another 810x or 826x device, connect the PSDV AL
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clock for even clock ratios, such as 1:4 and 1:6 (bus clock: core clock). Do not use even bus clock to core clock ratios. es during a split transaction. Workaround: Enable Bus Monitor. combinations of consecutive reads and writes. Workaround: Do not use Extended mode on the local bus.
- Read transaction with DACK before AACK.
- Failed atomic write transaction
Description: INOUT pin IRQ7_INTOUT should be open-drain but not implemented as one. Workaround: Buffer INTOUT on the board when it is wire ORed.
Description: The PPC Bus and Local Bus are limited to 50 MHz operation. may result in a spurious TEA. The write to the SIU register file is successful despite the TEA. Extended Core/Bus clock domain boundary in certain MODCK configurations. quently enabled because the SYPCR can only be written once. Workaround: When global transactions are used, 60x compatible mode cannot be used.
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accesses. ALE recovers with the first access after reset. Description: Data transferred by the DMA on either the PPC Bus or Local Bus may be corrupted. BCR[PLDP]=1. For DMA accesses on the Local Bus the UPMC programming patch is available. Use only DMA 32-bit maximum transfer size for both input and output channels. Fix Plan: Not currently scheduled. Description: The host bootload calculates erroneous checksum.
of one processor with another. Workaround: For up to 4 MSC8101’s including the configuration master.
- Clear all external requestors from the Arbitration Level Register (ALR) of the arbi -
- Reprogram the UPM of the DSPRAM bank to unique address (see programming
- Set priority for the next configuration slave in the Arbitration Level Register
(ALR) of the arbitration master.
- Enable external bus requests by clearing SIUMCR MMR field (bits [16:17]).
- Repeat stages 2,3 for consecutive slaves.
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quirement of 100V. All pins guaranteed to withstand 75V MM. Description: D[32:60] outputs may behave indeterminately during boundary scan. PORESET throughout boundary scan. an asynchronous interrupt, the core enters Debug mode, but the PC cannot be updated. static cases. A detailed description was sent by StarCore and can be resent upon request. programmed to write both event counters (ECNT_VAL and ECNT_EXT). SC140 May Hang After Write To PCTL0 Register. busy (e.g. pre-fetch transactions), the core may not exit the freeze state.
- Make sure the EFCOP is not working.
- Make sure the local bus to L1 memory is not working.
- The program that writes to PCTL0 is in internal memory.
- Write to PCTL0 immediately after reset before any external data accesses.
Option B: Do not write to PCTL0.
that can only be released by reset. Workaround: No workaround available. Description: After writing data to the Trace Buffer, the TB is disabled, in order to read from it.
- Reading the TB by software.
- Reading the TB from the JTAG .
a. The program will be in internal memory. b. Make sure the EFCOP is not working. c. Make sure the local bus to L1 memory is not working. d. The Write-Buffer is empty. e. There are no other move commands except for the TB read. a. Read the TB from JTAG only when the core is in DEBUG mode. b. Before reading the TB, flush the Write-Buffer.
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and is not needed for the trace. there is a destination which came before its source. Delete the source and the previous data. quest is asserted and negated during core freeze, the request will be discarded. ecuted. After that, a new JTAG instruction can be written. is negated during the same core freeze, the event is not enabled.
- After a stop transmit command is issued.
- Following a CTS lost condition.
- Late collision under ethernet.
an overrun error may occur and the FCC may have to be reset. Description: The TODR mechanism may freeze serial channels. Workaround: Do not use TODR. ATM receiver in UTOPIA slave mode. lates the UTOPIA standard requirements: transmits data without CLA V). Transmitter changed selected PHY number. FIFO full condition ended (CPM read some data from FIFO). higher-level protocol software.
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cations controller, the TIRU bit may be set as expected when the error should be reported. frame. In most of cases, a CRC error is generated and the frame is discarded. associated frames have been transmitted (assuming a frame per BD). Workaround: Use microcode patch provided by Freescale. AAL1 with UDC in which the user-defined header size is 9 to 12 octets and PM is not used. ing any of the elements (e.g., using cell header of 8 octets) eliminates it.
bits not being written may be corrupted. PIA error condition when SOC and CLAV are not asserted simultaneously. amble of the previous frame. Workaround: S/W should ignore COL indications when the CRC of the frame is correct. late collision, a false defer indication is indicated for the next frame. mitted back-to-back in case there is valid data in the transmitter’s FIFO. always before the next edge of the serial clock.
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Description: The heartbeat checking in FCC transmit ethernet 10Mbps does not work properly. once at exactly 4usec (10 serial clocks) after the falling edge of the carrier sense signal. terrupts on the receive side after a programmable number of frames. Workaround: RFTHR should be programed to 1. (MAXD1 and MAXD2 < MFLR) does not work. Ethernet, HDLC, Transparent. is completely corrupted, not just the last byte. Workaround: The bug can be worked around with a microcode patch.
(Sync sampled with rising edge -> Sync should not change on falling edge). device that generates the sync signal and the MSC8101 that uses it. also reported on an adjacent frame.
- Use the available microcode patch from the web site.
- When working with AAL0 SAR, place the TCELL_TMP_BASE 64 byte align plus 4.
For example use TCELL_TMB_BASE = 0x2d04 not 0x2d00.
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Idle_BASE = 0x2cfc not 0x2d00. limitation has no workaround. one TDM slot uses 7 bits of contiguous data. flow of cells by negating TxCLAV. Note that this bug affects Rev A.1 chips only.
at the last bit before the flag fails to occur. Workaround: There is a microcode patch which fixes the problem. is possible since the cell length is constant and the number of PHY to poll is also constant. service to the CPM with different priorities in order to receive the necessary assistance in time. when disabling TDMd, TDMb is affected. when disabling TDMb, TDMc is affected. when disabling TDMc, No TDM is affected. only non supported slots in its entries.
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Description: External CAM address recognition in Fast Ethernet controller does not function. Workaround: Use microcode patch available from Freescale. es the value of the RCVSYNC parameter. Workaround: Write to RCVSYNC a pattern which cannot appear in the Rx data line. Error in switching to and from shadow SI ram. Description: Dynamic switching in SIRAM may not be executed properly. Error in ATM_Transmit command.
Workaround: Use microcode patch. buffer contents for the PDU are correct. Workaround: Receive AAL5 PDU less than 65512 bytes or use microcode patch. Description: The SS7 microcode in ROM does not function correctly and should not be used. Workaround: Use the Enhanced SS7 microcode package. CPM does not snoop MCC buffer descriptors. the GBL/TC2 and the bus performance issue. the MCC transmitter relative to FCC1 receiver and transmitter as well as the MCC receiver.
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TDM is active may result in data corruption within the SI RAM. it. Once the accesses has been made, the SI RAM bank should be re-assigned to the active TDM. HDLC controller will get stuck and stop transmission. frame is affected separately. =0xffff, it sets a zero delay instead of maximum delay. transmitter will continue to send bytes 4-7 of the pattern continuously until the counter reaches 0. Any bytes defined in the pattern after byte 7 are never transmitted. Workaround: Use a template size of 8 bytes. ber of BSY events that are generated.
troller in Single PHY Master mode. PHY Addr input, the Output will be as for PHY 0. mand. This GUN can happen unrelated to internal CPM loading or other external factors.
- Use shadow RAM and dynamically remove the desired MCC RX channel entry
ing procedure should be utilized, using an extra redundant shadow RAM switch. a. Re-program shadow SIRAM to remove channel to be stopped. register to change to indicate switch complete. d. Switch to active RAM, again wait for switch to complete. cause ATM cells to be treated as mis-inserted cells and therefore be discarded. Workaround: Use microcode patch available from Freescale.
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when performance monitoring is enabled in the receiver.
- Disable Receive Performance Monitoring RCT[PMT]=0.
- Use microcode patch available from Freescale.
clock spikes that may be misinterpreted as clock pulses. cells, an erroneous value in this field could have a detrimental effect on the network performance. will be incorrect with a high chance of the access resulting in a CPM crash. Workaround: Use the microcode patch available from Freescale.
diagram are with respect to the master, so the Tx interface is shown.
- The master should not poll RxClav or pause a cell transfer 4 cycles before the end of a cell
than one cell transfer time. If this can be achieved, the impact on performance is minimal.
- Configuring ATM only on FCC1 and setting FPSMR[TPRI] ensures the highest priority to
guarantee that the RxFIFO does not fill up. the highest priority excluding emergency status of other peripherals) . and requires higher CPM usage than the other FCCs, disable its emergency status.
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the associated frames have been transmitted (assuming a frame per BD). Workaround: Use microcode patch provided by Freescale. associated frames have been transmitted (assuming a frame per BD). Workaround: Use microcode patch provided by Freescale. sometimes read as 0, even though it has some bits set. APC tables when there are cells available in lower priority APC scheduling table for transmission. channels that are not located in the highest-priority APC scheduling table. wise, use the microcode patch available from Freescale. which causes a loss of data and the resynchronization routine. Workaround: Use microcode patch provided by Freescale.
Description: Internal connectivity between TIN3 and TIN4 is switched.
- Please note that for timer4 using external clock (TIN3) and TOUT4 is impossible.
have been received beforehand. Workaround: Use the microcode patch supplied by Freescale. may contain the data of the aborted frame followed by the data of the good frame. Workaround: Use the microcode patch provided by Freescale. tion of TX_EN and 123 clocks. Workaround: Use the microcode patch provided by Freescale.
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FISUs. Regardless of the value of this field, one flag will be present between back-to-back FISUs. Workaround: Use the latest SS7 microcode package provided by Freescale. Fix Plan: None at this time. one or more TDMs are working, one data frame of a working TDM may become corrupted.
Silicon Errata for the MSC8101 Processor, Mask 0K40A, Rev. 5 Freescale Semiconductor 27
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