MSC7116

MSC7116 FREESCALE | Alldatasheet

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Technical content

Document Number: MSC7116 Rev. 11, 7/2007 © Freescale Semiconductor, Inc., 2004, 2007. All rights reserved. MSC7116 MAP-BGA–400 17 mm × 17 mm

• S t a r C o r e® SC1400 DSP extended core with one SC1400 DSP core, 192 Kbyte of internal SRAM M1 memory, 16 way 16 Kbyte instruction cache (ICache), four-entry write buffer, programmable interrupt controller (PIC), and low-power Wait and Stop processing modes.  192 Kbyte M2 memory for critical data and temporary data buffering.  8 Kbyte boot ROM.  AHB-Lite crossbar switch that allows parallel data transfers between four master ports and six slave ports, where each port connects to an AHB-Lite bus; fixed or round robin priority programmable at each slave port; programmable bus parking at each slave port; low power mode.  Internal PLL generates up to 266 MHz clock for the SC1400 core and up to 133 MHz for the crossbar switch, DMA channels, M2 memory, and other peripherals.  Clock synthesis module provides predivision of PLL input clock; independent clocking of the internal timers and DDR module; programmable operation in the SC1400 low power Stop mode; independent shutdown of different regions of the device.  Enhanced 16-bit wide host interface (HDI16) provides a glueless connection to industry-standard microcomputers, microprocessors, and DSPs and can also operate with an 8-bit host data bus, making if fully compatible with the DSP56300 HI08 from the external host side.  DDR memory controller that supports byte enables for up to a 32-bit data bus; glueless interface to 133 MHz 14-bit page mode DDR-RAM; 14-bit external address bus supporting up to 1 Gbyte; and 16-bit or 32-bit external data bus.  Programmable memory interface with independent read buffers, programmable predictive read feature for each buffer, and a write buffer.  System control unit performs software watchdog timer function; includes programmable bus time-out monitors on AHB-Lite slave buses; includes bus error detection and programmable time-out monitors on AHB-Lite master buses; and has address out-of-range detection on each crossbar switch buses.  Event port collects and counts important signal events including DMA and interrupt requests and trigger events such as interrupts, breakpoints, DMA transfers, or wake-up events; units operate independently, in sequence, or triggered externally; can be used standalone or with the OCE10.  Multi-channel DMA controller with 32 time-multiplexed unidirectional channels, priority-based time-multiplexing between channels using 32 internal priority levels, fixed- or round-robin-priority operation, major-minor loop structure, and DONE or DRACK protocol from requesting units.  Two independent TDM modules with independent receive and transmit, programmable sharing of frame sync and clock, programmable word size (8 or 16-bit), hardware-base A-law/μ-law conversion, up to 50 Mbps data rate per TDM, up to 128 channels, with glueless interface to E1/T1 frames and MVIP , SCAS, and H.110 buses.  Ethernet controller with support for 10/100 Mbps MII/RMII designed to comply with IEEE Std. 802.3™, 802.3u™, 802.3x™, and 802.3ac™; with internal receive and transmit FIFOs and a FIFO controller; direct access to internal memories via its own DMA controller; full and half duplex operation; programmable maximum frame length; virtual local area network (VLAN) tag and priority support; retransmission of transmit FIFO following collision; CRC generation and verification for inbound and outbound packets; and address recognition including promiscuous, broadcast, individual address. hash/exact match, and multicast hash match.  UART with full-duplex operation up to 5.0 Mbps.  Up to 41 general-purpose input/output (GPIO) ports. 2C interface that allows booting from EEPROM devices up to 1 Mbyte.  Two quad timer modules, each with sixteen configurable 16-bit timers.  fieldBIST™ unit detects and provides visibility into unlikely field failures for systems with high availability to ensure structural integrity, that the device operates at the rated speed, is free from reliability defects, and reports diagnostics for partial or complete device inoperability.  Standard JTAG interface allows easy integration to system firmware and internal on-chip emulation (OCE10) module.  Optional booting external host via 8-bit or 16-bit access through the HDI16, I 2C, or SPI using in the boot ROM to access serial SPI Flash/EEPROM devices; different clocking options during boot with the PLL on or off using a variety of input frequency ranges. Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC

Figure 1. MSC7116 Block Diagram

2 TDMs

32 Events32

MII/RMIIdirection of the transfer.

1 Pin Assignments

This section includes diagrams of the MSC7116 package ball grid array layouts and pinout allocation tables.

1.1 FC-PBGA Ball Layout Diagrams

Top and bottom views of the MAP-BGA package are shown in Figure 2 and Figure 3 with their ball location index numbers. Figure 2. MSC7116 Molded Array Process-Ball Grid Array (MAP-BGA), Top View

Figure 3. MSC7116 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View

1.2 Signal List By Ball Location

Table 1 lists the signals sorted by ball number and configuration. Table 1. MSC7116 Signals by Ball Designator

Table 1. MSC7116 Signals by Ball Designator (continued)

Electrical Characteristics

MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11 Freescale Semiconductor 17

2 Electrical Characteristics

This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications. For additional information, see the MSC711x Reference Manual.

2.1 Maximum Ratings

In calculating timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. Y14 GPIA2 IRQ9 GPOA2 T1TCK Y15 GPIA29 IRQ16 GPOA29 TXD3 reserved Y16 GPID5 GPOD5 RXCLK reserved Y17 GPIA20 IRQ20 GPOA20 TXD0 Y18 GPIA21 IRQ21 GPOA21 RXD1 Y19 GND Y20 GPIA25 IRQ25 GPOA25 RX_DV or CRS_DV CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or V DD).

MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11 Table 2 describes the maximum electrical ratings for the MSC7116.

2.2 Recommended Operating Conditions

Table 3 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed. Table 2. Absolute Maximum Ratings Notes: 1. Functional operating conditions are given in Table 3.

1. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond

the listed limits may affect device reliability or cause permanent damage.

1. Section 3.1 , Thermal Design Considerations includes a formula for computing the chip junction temperature (T J).

Table 3. Recommended Operating Conditions

MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11 Freescale Semiconductor 19

2.3 Thermal Characteristics

Table 4 describes thermal characteristics of the MSC7116 for the MAP-BGA package. Section 3.1, Thermal Design Considerations explains these characteristics in detail.

2.4 DC Electrical Characteristics

This section describes the DC electrical characteristics for the MSC7116. Note: The leakage current is measured for nominal voltage values must vary in the same direction (for example, both VDDIO and VDDC vary by +2 percent or both vary by –2 percent). Table 4. Thermal Characteristics for MAP-BGA Package

1. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
2. Per JEDEC JESD51-6 with the board horizontal.
3. Thermal resistance between the die and the printed circuit boar d per JEDEC JESD 51-8. Board temperature is measured on

the top surface of the board near the package.

1. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
2. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature

Table 5. DC Electrical Characteristics

MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11 Table 6 lists the DDR DRAM capacitance. Tri-state (high impedance off state) leakage current, VIN = VDDIO IOZ –1.0 0.09 1 µA Signal low input current, VIL = 0.4 V I L –1.0 0.09 1 µA Signal high input current, VIH = 2.0 V I H –1.0 0.09 1 µA Output high voltage, IOH = –2 mA, except open drain pins V OH 2.0 3.0 — V Output low voltage, IOL= 5 mA V OL —0 0 . 4 V Typical power at 266 MHz5 P — 293.0 — mW Notes: 1. The value of VDDM at the MSC7116 device must remain within 50 mV of V DDM at the DRAM device at all times. 2. VREF must be equal to 50% of VDDM and track VDDM variations as measured at the receiver. Peak-to-peak noise must not exceed ±2% of the DC value. 3. VTT is not applied directly to the MSC7116 device. It is the level measured at the far end signal termination. It should be equal to VREF. This rail should track variations in the DC level of V REF. 4. Output leakage for the memory interface is measured with all outputs disabled, 0 V ≤ VOUT ≤ VDDM. 5. The core power values were measured.using a standard EFR pat tern at typical conditions (25°C, 300 MHz, 1.2 V core). Table 6. DDR DRAM Capacitance Table 5. DC Electrical Characteristics (continued)

MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11 Freescale Semiconductor 21

2.5 AC Timings

This section presents timing diagrams and specifications for individual signals and parallel I/O outputs and inputs. All AC timings are based on a 30 pF load, except where noted otherwise, and a 50 Ω transmission line. For any additional pF, use the following equations to compute the delay: — Standard interface: 2.45 + (0.054 × Cload) ns — DDR interface: 1.6 + (0.002 × Cload) ns

2.5.1 Clock and Timing Signals

The following tables describe clock signal characteristics. Table 6 shows the maximum frequency values for internal (core, reference, and peripherals) and external (CLKO) clocks. You must ensure that maximum frequency values are not exceeded (see Section 2.5.2 for the allowable ranges when using the PLL). Table 6. Maximum Frequencies Table 7. Clock Frequencies in MHz Table 8. System Clock Parameters

MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11

2.5.2 Configuring Clock Frequencies

This section describes important requirements for configuring clock frequencies in the MSC7116 device when using the PLL block. To configure the device clocking, you must program four fields in the Clock Control Register (CLKCTL):  PLLDVF field. Specifies the PLL division factor (PLLDVF + 1) to divide the input clock frequency FCLKIN. The output of the divider block is the input to the multiplier block.  PLLMLTF field. Specifies the PLL multiplication factor (PLLMLTF + 1). The output from the multiplier block is the loop frequency FLOOP.  RNG field. Selects the available PLL frequency range for FVCO, either FLOOP when the RNG bit is set (1) or FLOOP/2 when the RNG bit is cleared (0).  CKSEL field. Selects FCLKIN, FVCO, or FVCO/2 as the source for the core clock. There are restrictions on the frequency range permitted at the beginning of the multiplication portion of the PLL that affect the allowable values for the PLLDVF and PLLMLTF fields. The following sections define these restrictions and provide guidelines to configure the device clocking when using the PLL. Refer to the Clock and Power Management chapter in the MSC711x Reference Manual for details on the clock programming model.

2.5.2.1 PLL Multiplier Restrictions

There are two restrictions for correct usage of the PLL block:  The input frequency to the PLL multiplier block (that is, the output of the divider) must be in the range 10–25 MHz.  The output frequency of the PLL multiplier must be in the range 266–532 MHz. When programming the PLL for a desired output frequency using the PLLDVF, PLLMLTF, and RNG fields, you must meet these constraints.

2.5.2.2 Input Division Factors and Corresponding CLKIN Frequency Range

The value of the PLLDVF field determines the allowable CLKIN frequency range, as shown in Table 9. Table 9. CLKIN Frequency Ranges by Divide Factor Value Note: The maximum CLKIN frequency is 100 MHz. Therefore, the PLLDVF value must be in the range from 1–10.

MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11 Freescale Semiconductor 23

2.5.2.3 Multiplication Factor Range

The multiplier block output frequency ranges depend on the divided input clock frequency as shown in Table 10.

2.5.2.4 Allowed Core Clock Frequency Range

The frequency delivered to the core, extended core, and peripherals depends on the value of the CLKCTRL[RNG] bit as shown in Table 11. This bit along with the CKSEL determines the frequency range of the core clock.

2.5.2.5 Core Clock Frequency Range When Using DDR Memory

The core clock can also be limited by the frequency range of the DDR devices in the system. Table 13 summarizes this restriction. Table 10. PLLMLTF Ranges frequency of the Divided Input Clock. Table 11. Fvco Frequency Ranges Note: This table results from the allowed range for F vco, which is FLoop modified by CLKCTRL[RNG]. Table 12. Resulting Ranges Permitted for the Core Clock Note: This table results from the allowed range for F OUT, which depends on clock selected via CLKCTRL[CKSEL]. Table 13. Core Clock Ranges When Using DDR

MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11

2.5.3 Reset Timing

The MSC7116 device has several inputs to the reset logic. All MSC7116 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset. The reset status register indicates the most recent sources to cause a reset. Table 14 describes the reset sources. Table 15 summarizes the reset actions that occur as a result of the different reset sources.

2.5.3.1 Power-On Reset (PORESET ) Pin

Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 16 CLKIN cycles after external power to the MSC7116 reaches at least 2/3 VDD. Table 14. Reset Sources system is configured only when PORESET is asserted. enabled software watchdog event then gener ates an internal hard reset sequence. enabled bus monitor event then generates an internal hard reset sequence. asserts an internal reset signal that generates an internal soft reset sequence. Table 15. Reset Actions for Each Reset Source

MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11 Freescale Semiconductor 25

2.5.3.2 Reset Configuration

The MSC7116 has two mechanisms for writing the reset configuration:  From a host through the host interface (HDI16)  From memory through the I 2C interface Five signal levels (see Chapter 1 for signal description details) are sampled on PORESET deassertion to define the boot and operating conditions:  BM[0–1]  SWTE H 8 B I T  HDSP

2.5.3.3 Reset Timing Tables

Table 16 and Figure 4 describe the reset timing for a reset configuration write. Table 16. Timing for a Reset Configuration Write

1 Required external PORESET duration minimum 16/F CLKIN clocks

2 Delay from PORESET deassertion to HRESET deassertion 521/F CLKIN clocks

Note: Timings are not tested, but are guaranteed by design. Figure 4. Timing Diagram for a Reset Configuration Write

MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11

2.5.4 DDR DRAM Controller Timing

This section provides the AC electrical characteristics for the DDR DRAM interface.

2.5.4.1 DDR DRAM Input AC Timing Specifications

Table 17 provides the input AC timing specifications for the DDR DRAM interface.

2.5.4.2 DDR DRAM Output AC Timing Specifications

Table 18 and Table 19 list the output AC timing specifications and measurement conditions for the DDR DRAM interface. Table 17. DDR DRAM Input AC Timing

201 Maximum Dn input setup skew relative to DQSn input — — 900 ps

202 Maximum Dn input hold skew relative to DQSn input — — 900 ps

1. Dn should be driven at the same time as DQSn. This is nec essary because the DQSn centering on the DQn data tenure is

Figure 5. DDR DRAM Input Timing Diagram Table 18. DDR DRAM Output AC Timing

200 CK cycle time, (CK/CK crossing)1

208 CK to DQSn 2 tDDKHMH –600 600 ps

Note: DQS centering is done internally.

MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11 Freescale Semiconductor 27 Figure 6 shows the DDR DRAM output timing diagram.

209 Dn/DQMn output setup with respect to DQSn 3 tDDKHDS,

0.25 × tCK – 750 — ps

210 Dn/DQMn output hold with respect to DQSn 3 tDDKHDX,

0.25 × tCK – 750 — ps 211 DQSn preamble start 4 tDDKHMP –0.25 × tCK —p s

212 DQSn epilogue end 5 tDDKHME –600 600 ps

Notes: 1. All CK/CK referenced measurements are made from the crossing of the two signals ±0.1 V. 2. tDDKHMH can be modified through the TCFG2[WRDD] DQSS override bi ts. The DRAM requires that the first write data strobe arrives 75–125% of a DRAM cycle after the write command is issued. Any skew between DQSn and CK must be considered when trying to achieve this 75%–125% goal. The TCFG2[WRDD] bits can be used to shift DQSn by 1/4 DRAM cycle increments. The skew in this case refers to an internal skew existing at the signal connections. By default, the CK/CK crossing occurs in the middle of the control signal (An/RAS /CAS/WE/CKE) tenure. Setting TCFG2[ACSM] bit shifts the control signal assertion 1/2 DRAM cycle earlier than the default timing. This m eans that the signal is asserted no earlier than 600 ps before the CK/CK crossing and no later than 600 ps after the crossing time; the device uses 1200 ps of the skew budget (the interval from –600 to +600 ps). Timing is verified by refer encing the falling edge of CK. See Chapter 10 of the MSC711x Reference Manual for details. 3. Determined by maximum possible skew between a data strobe (DQS) and any corresponding bit of data. The data strobe should be centered inside of the data eye. 4. Please note that this spec is in reference to the DQSn first rising edge. It could also be referenced from CK(r), but due to programmable delay of the write strobes (TCFG2[WRDD]), ther e pre-amble may be extended for a full DRAM cycle. For this reason, we reference from DQSn. 5. All outputs are referenced to the rising edge of CK. Note that th is is essentially the CK/DQSn skew in spec 208. In addition there is no real “maximum” time for the epilogue end. JEDEC does not require this is as a device limitation, but simply for the chip to guarantee fast enough write-to-read turn-around times. This is already guaranteed by the memory controller operation. Figure 6. DDR DRAM Output Timing Diagram Table 18. DDR DRAM Output AC Timing (continued)

MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11 Figure 7 provides the AC test load for the DDR DRAM bus.

2.5.5 TDM Timing

Figure 7. DDR DRAM AC Test Load Table 19. DDR DRAM Measurement Conditions Notes: 1. Data input threshold measurement point.

1. Data output measurement point.

Table 20. TDM Timing Notes: 1. Output values are based on 30 pF capacitive load.

1. Inputs are referenced to the sampling that the TDM is program med to use. Outputs are referenced to the programming edge

Reference Manual for details. TDMxTCK and TDMxRCK are shown using the rising edge. Figure 8. TDM Receive Signals

MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11 Freescale Semiconductor 29

2.5.6 Ethernet Timing

2.5.6.1 Receive Signal Timing

Figure 9. TDM Transmit Signals Table 21. Receive Signal Timing

800 Receive clock period:

801 Receive clock pulse width high—as a percent of clock period

802 Receive clock pulse width low—as a percent of clock period:

803 RXDn, RX_DV, CRS_DV, RX_ER to receive clock rising edge setup time 4 — ns

804 Receive clock rising edge to RXDn, RX_DV, CRS_DV, RX_ER hold time 2 — ns

Figure 10. Ethernet Receive Signal Timing

MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11

2.5.6.2 Transmit Signal Timing

2.5.6.3 Asynchronous Input Signal Timing

Table 22. Transmit Signal Timing

800 Transmit clock period:

801 Transmit clock pulse width high—as a percent of clock period

802 Transmit clock pulse width low—as a percent of clock period:

805 Transmit clock to TXDn, TX_EN, TX_ER invalid 4 — ns

806 Transmit clock to TXDn, TX_EN, TX_ER valid — 14 ns

Figure 11. Ethernet Receive Signal Timing Table 23. Asynchronous Input Signal Timing Figure 12. Asynchronous Input Signal Timing

MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11 Freescale Semiconductor 31

2.5.6.4 Management Interface Timing

Table 24. Ethernet Controller Management Interface Timing

808 MDC period 400 — ns

809 MDC pulse width high 160 — ns

810 MDC pulse width low 160 — ns

811 MDS falling edge to MDIO output invalid (minimum propagation delay) 0 — ns

812 MDS falling edge to MDIO output valid (maximum propagation delay) — 15 ns

813 MDIO input to MDC rising edge setup time 10 — ns

814 MDC rising edge to MDIO input hold time 10 — ns

Figure 13. Serial Management Channel Timing

MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11

2.5.7 HDI16 Signals

Table 25. Host Interface (HDI16) Timing1, 2

40 Host Interface Clock period T CORE Note 1 ns

45 Write data strobe minimum assertion width 8

46 Write data strobe minimum deassertion width 8

47 Host data input minimum setup time before write data strobe deassertion 8

48 Host data input minimum hold time after write data strobe deassertion 8

49 Read data strobe minimum assertion to output data active from high

50 Read data strobe maximum assertion to output data valid 4

51 Read data strobe maximum deassertion to output data high impedance 4

52 Output data minimum hold time after read data strobe deassertion 4

61 Maximum delay from read data strobe deassertion to host request

62 Maximum delay from write data strobe deassertion to host request

63 Minimum delay from DMA HACK (OAD=0) or Read/Write data

64 Maximum delay from DMA HACK (OAD=0) or Read/Write data

Notes: 1. TCORE = core clock period. At 300 MHz, T CORE = 3.333 ns.

1. In the timing diagrams below, the controls pins are dr awn as active low. The pin polarity is programmable.
2. VDD = 3.3 V ± 0.15 V; TJ = –40°C to +105 °C, CL = 30 pF for maximum delay timings and CL = 0 pF for minimum delay timings.
3. The read data strobe is HRD/HRD in the dual data strobe mode and HDS /HDS in the single data strobe mode.
4. For 64-bit transfers, the “last data register” is the register at address 0x7, which is the last location to be read or written in data

transfers. This is RX0/TX0 in the little endian mode (H BE = 0), or RX3/TX3 in the big endian mode (HBE = 1).

1. This timing is applicable only if a read from the “last data register” is followed by a read from the RX[0–3] registers without first

polling RXDF or HREQ bits, or waiting for the assertion of the HREQ /HREQ signal.

1. This timing is applicable only if two consecutive reads from one of these registers are executed.
2. The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.
3. The data strobe is host read (HRD /HRD) or host write (HWR/HWR) in the dual data strobe mode and host data strobe

(HDS/HDS) in the single data strobe mode.

1. The host request is HREQ/HREQ in the single host request mode and HRRQ /HRRQ and HTRQ/HTRQ in the double host
2. Compute the value using the expression.
3. The read and write data strobe minimum deassertion width for non-”last data register” accesses in single and dual data strobe

modes is based on timings 57 and 58.

2.5.8 I 2C Timing

Table 26. I2C Timing

450 SCL clock frequency 0 400 kHz

454 Repeated START set-up time (not shown in figure) 2 × 1/FBCK — μs

455 Data hold time 0 — μs

456 Data set-up time 250 — ns

457 SDA and SCL rise time — 700 ns

458 SDA and SCL fall time — 300 ns

Figure 20. I2C Timing Diagram

2.5.9 UART Timing

2.5.10 EE Timing

Figure 24 shows the signal behavior of the EE pin. Table 27. UART Timing

401 URXD and UTXD inputs rise/fall time — 5 ns

402 UTXD output rise/fall time — 5 ns

Figure 21. UART Input Timing Figure 22. UART Output Timing Table 28. EE0 Timing

65 EE0 input to the core Asynchronous 4 core clock periods

66 EE0 output from the core Synchronous to core clock 1 core clock period

Notes: 1. The core clock is the SC1400 core clock. The ratio between t he core clock and CLKOUT is configured during power-on-reset.

1. Configure the direction of the EE pin in the EE_CTRL register (see the SC140/SC1400 Core Reference Manual for details.
2. Refer to Table 1-11 on page 1-16 for details on EE pin functionality.

Figure 23. EE Pin Timing

2.5.11 Event Timing

Figure 24 shows the signal behavior of the EVNT pins.

2.5.12 GPIO Timing

Figure 25 shows the signal behavior of the GPI/GPO pins. Table 29. EVNT Signal Timing

68 EVNT as output Synchronous to core clock 1 APBCLK period

Notes: 1. Refer to Table 27 for a definition of the APBCLK period.

1. Direction of the EVNT signal is configur ed through the GPIO and Event port registers.
2. Refer to the signal chapter in the MSC711x Reference Manual for details on EVNT pin functionality.

Figure 24. EVNT Pin Timing Table 30. GPIO Signal Timing1,2,3

602 GPO 5 Synchronous to core clock 1 APBCLK period

604 Port A level-sensitive interrupt Asynchronous 3 × APBCLK periods6

Notes: 1. Refer to Table 27 for a definition of the APBCLK period.

1. Direction of the GPIO signal is conf igured through the GPIO port registers.
2. Refer to Section 1.5 for details on GPIO pin functionality.
3. GPI data is synchronized to the APBCLK internally and the minimum listed is the capability of the hardware to capture data

dependence on the state of the DSP core. It is guaranteed by design.

1. The output signals cannot toggle faster than 75 MHz.
2. Level-sensitive interrupts should be held low until the system dete rmines (via the service routine) that the interrupt is

Figure 25. GPI/GPO Pin Timing

2.5.13 JTAG Signals

Table 31. JTAG Timing

700 TCK frequency of operation (1/(T C × 3)

702 TCK clock pulse width measured at V

712 TRST

Note: All timings apply to OCE module data transfers as t he OCE module uses the JTAG port as an interface. Figure 26. Test Clock Input Timing Diagram

Hardware Design Considerations MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11 Freescale Semiconductor 41

3 Hardware Design Considerations

This section described various areas to consider when incorporating the MSC7116 device into a system design.

3.1 Thermal Design Considerations

An estimation of the chip-junction temperature, TJ, in °C can be obtained from the following: TJ = TA + (RθJA × PD)E q n . 1 where TA = ambient temperature near the package (°C) RθJA = junction-to-ambient thermal resistance (°C/W) PD = PINT + PI/O = power dissipation in the package (W) PINT = IDD × VDD = internal power dissipation (W) PI/O = power dissipated from device on output pins (W) The power dissipation values for the MSC7116 are listed in Table 4. The ambient temperature for the device is the air temperature in the immediate vicinity that would cool the device. The junction-to-ambient thermal resistances are JEDEC standard values that provide a quick and easy estimation of thermal performance. There are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. The value that more closely approximates a specific application depends on the power dissipated by other components on the printed circuit board (PCB). The value obtained using a single layer board is appropriate for tightly packed PCB configurations. The value obtained using a board with internal planes is more appropriate for boards with low power dissipation (less than 0.02 W/cm2 with natural convection) and well separated components. Based on an estimation of junction temperature using this technique, determine whether a more detailed thermal analysis is required. Standard thermal management techniques can be used to maintain the device thermal junction temperature below its maximum. If T J appears to be too high, either lower the ambient temperature or the power dissipation of the chip. You can verify the junction temperature by measuring the case temperature using a small diameter thermocouple (40 gauge is recommended) or an infrared temperature sensor on a spot on the device case. Use the following equation to determine TJ: TJ = TT + (ΨJT × PD)E q n . 2 where TT = thermocouple (or infrared) temperature on top of the package (°C) ΨJT = thermal characterization parameter (°C/W) PD = power dissipation in the package (W)

3.2 Power Supply Design Considerations

consumption. For information on AC/DC electrical specifications and thermal characteristics, refer to Section 2.  Power Supply. The MSC7116 requires four input voltages, as shown in Table 32. voltage supply requirements. — Turn on the highest supply first (3.3 V). — Turn on the lowest supply last (1.2 V). — Turn off the lowest supply first (1.2 V). — Turn off the 2.5 V supply. — Turn off the highest supply last (3.3 V). 2.5 V supply, as shown in Figure 30. The power-down sequence is not as critical as the power-up sequence. Table 32. MSC7116 Voltages

— Extended core. Use the SC1400 Stop and Wait modes by issuing a stop or wait instruction. — Clock synthesis module. Disable the PLL, timer, watchdog, or DDR clocks or disable the CLKO pin. — AHB subsystem. Freeze or shut down the AHB subsystem using the GPSCTL[XBR_HRQ] bit. MAC, HDI16, TDM, UART, I2C, and timer modules. For details, see the “Clocks and Power Management” chapter of the MSC711x Reference Manual. are available that take care of all DDR power requirements.

3.3 Estimated Power Usage Calculations

3.3.1 Core Power

This equation allows for adjustments to voltage and frequency if necessary. Table 33. Recommended Power Supply Ratings

Hardware Design Considerations MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11 Freescale Semiconductor 45

3.3.2 Peripheral Power

Peripherals include the DDR memory controller, Ethernet controller, DMA controller, HDI16, TDM, UART, timers, GPIOs, and the I2C module. Basic power consumption by each module is assumed to be the same and is computed by using the following equation which assumes an effective load of 20 pF, core voltage swing of 1.2 V , and a switching frequency of 133 MHz. This yields: PPERIPHERAL = 20 pF × (1.2 V)2 × 133 MHz × 10–3 = 3.83 mW per peripheral Eqn. 6 Multiply this value by the number of peripherals used in the application to compute the total peripheral power consumption.

3.3.3 External Memory Power

Estimation of power consumption by the DDR memory system is complex. It varies based on overall system signal line usage, termination and load levels, and switching rates. Because the DDR memory includes terminations external to the MSC7116 device, the 2.5 V power source provides the power for the termination, which is a static value of 16 mA per signal driven high. The dynamic power is computed, however, using a differential voltage swing of ±0.200 V , yielding a peak-to-peak swing of 0.4 V . The equations for computing the DDR power are: PDDRIO = PSTATIC + PDYNAMIC Eqn. 7 PSTATIC = (unused pins × % driven high) × 16 mA × 2.5 V Eqn. 8 PDYNAMIC = (pin activity value) × 20 pF × (0.4 V)2 × 266 MHz × 10–3 mW Eqn. 9 pin activity value = (active data lines × % activity × % data switching) + (active address lines × % activity) Eqn. 10 As an example, assume the following: unused pins = 16 (DDR uses 16-pin mode) % driven high = 50% active data lines = 16 % activity = 60% % data switching = 50% active address lines = 3 In this example, the DDR memory power consumption is: P

3.3.4 External I/O Power

The estimation of the I/O power is similar to the computation of the peripheral power estimates. The power consumption per signal line is computed assuming a maximum load of 20 pF, a voltage swing of 3.3 V , and a switching frequency of 33 MHz, which yields: PIO = 20 pF × (3.3 V)2 × 33 MHz × 10–3 = 7.19 mW per I/O line Eqn. 12 Multiply this number by the number of I/O signal lines used in the application design to compute the total I/O power. Note: The signal loading depends on the board routing. For systems using a single DDR device, the load could be as low as 7 pF.

3.3.5 Leakage Power

The leakage power is for all power supplies combined at a specific temperature. The value is temperature dependent. The observed leakage value at room temperature is 64 mW.

3.3.6 Example Total Power Consumption

3.4 Reset and Boot

This section describes the recommendations for configuring the MSC7116 at reset and boot.

3.4.1 Reset Circuit

current, the pull-up value should not be too small (a 1 KΩ pull-up resistor is used in the MSC711xADS reference design).

3.4.2 Reset Configuration Pins

PORESET. For details, refer to the Reset chapter of the MSC711x Reference Manual. Table 34. Reset Configuration Signals BM[3–0] Determines boot mode. See Table 35 for details. SWTE Determines watchdog functionality. 0 Watchdog timer disabled. HDSP Configures HDI16 strobe polarity. 0 Host Data strobes active low. 1 Host Data strobes active high. H8BIT Configures HDI16 operation mode. 0 HDI 16 port configured for 16-bit operation. 1 HDI16 port configured for 8-bit operation.

3.4.3 Boot

boot operating mode is set by configuring the BM[0–3] signals sampled at the rising edge of PORESET, as shown in Table 35. See the MSC711x Reference Manual for details of boot program operation.

3.4.3.1 HDI16 Boot

 Operate in polled mode on the device side.  Operate in polled mode on the external host side. Table 35. Boot Mode Source Selection 0000 HDI16 < Fmax N/A N/A 00 0 < Fmax Not clocked by the PLL. Can boot as 8- or 16-bit HDI.

0111 HDI16 33-66 MHz 3 12 11 1 132–264 MHz

1000 SPI (SW) < F

1010 SPI (SW) 33-50 MHz 2 16 11 0 132–200 MHz

1100 SPI (SW) < F

0001 I 2C < 100 MHz N/A N/A 00 0 < 100 MHz Not clocked by the PLL. Notes: 1. The clock divider determines the value used in the clock module CLKCTRL[PLLDVF] field.

1. The clock multiplier determines the value used in the clock module CLKCTRL[PLLMLTF] field.

max is determined by the maximum frequency of the peripheral and of the SC1400 core as specified in the data sheet.

MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11 Hardware Design Considerations Freescale Semiconductor48 When booting from a power-on reset, the HDI16 is additionally configurable as follows:  8- or 16-bit mode as specified by the H8BIT pin.  Data strobe as specified by the HDSP and HDDS pins. These pins are sampled only on the deassertion of power-on reset. During a boot from a hard reset, the configuration of these pins is unaffected. Note: When the HDI16 is used for booting or other purposes, bit 0 is the least significant bit and not the most significant bit as for other DSP products.

3.4.3.2 I 2C Boot

When the MSC7116 device is configured to boot from the I2C port, the boot program configures the GPIO pins for I2C operation. Then the MSC7116 device initiates accesses to the I2C module, downloading data to the MSC7116 device. The I2C interface is configured as follows:  PLL is disabled and bypassed so that the I 2C module is clocked with the IPBus clock. I 2C interface operates in master mode and polling is used.  EPROM operates in slave mode.  Clock divider is set to 128.  Address of slave during boot is 0xA0. The IPBus clock is internally divided to generate the bit clock, as follows:  CLKIN must be a maximum of 100 MHz  PLL is bypassed.  IPBus clock = CLKIN/2 is a maximum of 50 MHz. 2C bit clock must be less than or equal to: — IPBus clock/I 2C clock divider — 50 MHz (max)/128 — 390.6 KHz This satisfies the maximum clock rate requirement of 400 kbps for the I2C interface. For details on the boot procedure, see the “Boot Program” chapter of the MSC711x Reference Manual.

3.4.3.3 SPI Boot

When the MSC7116 device is configured to boot from the SPI port, the boot program configures the GPIO pins for SPI operation. Then the MSC7116 device initiates accesses to the SPI module, downloading data to the MSC7116 device. When the SPI routines run in the boot ROM, the MSC7116 is always configured as the SPI master. Booting through the SPI is supported for serial EEPROM devices and serial Flash devices. When a READ_ID instruction is issued to the serial memory device and the device returns a value of 0x00 or 0xFF, the routines for accessing a serial EEPROM are used, at a maximum frequency of 4 Mbps. Otherwise, the routines for accessing a serial Flash are used, and they can run at faster speeds. Booting is performed through one of two sets of pins:  Main set: BM[2–3], HA3, and HCS2, which allow use of the PLL.  Alternate set: UTXD, URXD, SDA, and SCL, which cannot be used with the PLL. In either configuration, an error during SPI boot is flagged on the EVNT3 pin. For details on the boot procedure, see the “Boot Program” chapter of the MSC711x Reference Manual.

3.5 DDR Memory System Guidelines

in Figure 32. Technique B is the most popular termination technique. Figure 32. SSTL Termination Techniques

3.5.1 V REF and VTT Design Constraints

 Minimize the noise on both rails. single IC to generate both signals.  Both references should have minimal drift over temperature and source supply. — Isolate V REF and shield it with a ground trace. — Use 20–30 mm clearance between other traces for isolating. — Use the outer layer route when possible.  Max source/sink transient currents of up to 1.8 A for a 32-bit data bus. — Place the island at the end of the bus. — Decouple both ends of the bus. — Use distributed decoup ling across the island. TT island and ensure a good, solid connection.  Place the V TT regulator as closely as possible to the termination island. — Reduce inductance and return path. — Tie current sense pin at the midpoint of the island.

3.5.2 Decoupling

 DDR memory requires significantly more burst current than previous SDRAMs.  In the worst case, up to 64 drivers may be switching states.  Pay special attention and decouple disc rete ICs per manufacturer guidelines. (http://download.micron.com/pdf/pubs/designline/3Q00dl1-4.pdf). Figure 33. SSTL Power Value

Hardware Design Considerations MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11 Freescale Semiconductor 51

3.5.3 General Routing

The general routing considerations for the DDR are as follows:  All DDR signals must be routed next to a solid reference: — For data, next to solid ground planes. — For address/command, power planes if necessary.  All DDR signals must be impedance controlled. This is system dependent, but typical values are 50–60 ohm.  Minimize other cross-talk opportunities. As possible, mainta in at least a four times the trace width spacing between all DDR signals to non-DDR signals.  Keep the number of vias to a minimum to eliminate additional stubs and capacitance.  Signal group routing priorities are as follows: — DDR clocks. — Route MVTT/MVREF. — Data group. — Command/address.  Minimize data bit jitter by trace matching.

3.5.4 Routing Clock Distribution

The DDR clock distribution considerations are as follows:  DDR controller supports six clock pairs: — 2 DIMM modules. — Up to 36 discrete chips.  For route traces as for any other differential signals: — Maintain proper difference pair spacing. — Match pair traces within 25 mm.  Match all clock traces to within 100 mm.  Keep all clocks equally loaded in the system.  Route clocks on inner critical layers.

3.5.5 Data Routing

The DDR data routing considerations are as follows:  Route each data group (8-bits data + DQS + DM) on the same layer. Avoid switching layers within a byte group.  Take care to match trace lengths, which is extremely important.  To make trace matching easier, let adjacent groups be routed on alternate critical layers.  Pin swap bits within a byte group to facilitate routing (discrete case).  Tight trace matching is recommended with in the DDR data group. Keep each 8-bit datum and its DM signal within ± 25 mm of its respective strobe.  Minimize lengths across the entire DDR channel: — Between all groups maintain a delta of no more than 500 mm. — Allows greater flexibility in the design for readjustments as needed.  DDR data group separation: — If stack-up allows, keep DDR data groups away from the address and control nets. — Route address and control on separate critical layers. — If resistor networks (RNs) are used, attempt to k eep data and command lines in separate packages.

MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11

Ordering Information

3.6 Connectivity Guidelines

This section summarizes the connections and special conditions, such as pull-up or pull-down resistors, for the MSC7116 device. Following are guidelines for signal groups and configuration settings:  Clock and reset signals. — SWTE is used to configure the MSC7116 device and is sampled on the deassertion of PORESET, so it should be tied to VDDC or GND either directly or through pull-up or pull-down resistors until PORESET is deasserted. After PORESET, this signal can be left floating. — BM[0–1] configure the MSC7116 device and are sampled until PORESET is deasserted, so they should be tied to VDDIO or GND either directly or through pull-up or pull-down resistors. — HRESET should be pulled up.  Interrupt signals. When used, IRQ pins must be pulled up.  HDI16 signals. — When they are configured for open-drain, the HREQ/HREQ or HTRQ/HTRQ signals require a pull-up resistor. However, these pins are also sampled at power-on reset to determine the HDI16 boot mode and may need to be pulled down. When these pins must be pulled down on reset and pulled up otherwise, a buffer can be used with the HRESET signal as the enable. — When the device boots through the HDI16, the HDDS, HDSP and H8BIT pins should be pulled up or down, depending on the required boot mode settings.  Ethernet MAC/TDM2 signals. The MDIO signal requires an external pull-up resistor.  I2C signals. The SCL and SDA signals, when programmed for I2C, requires an external pull-up resistor.  General-purpose I/O (GPIO) signals. An unused GPIO pin can be disconnected. After boot, program it as an output pin.  Other signals. —T h e TEST0 pin must be connected to ground. —T h e TPSEL pin should be pulled up to enable debug access via the EOnCE port and pulled down for boundary scan. — Pins labelled NO CONNECT (NC) must not be connected. — When a 16-pin double data rate (DDR) interface is used, th e 16 unused data pins should be no connects (floating) if the used lines are terminated. — Do not connect DBREQ to DONE (as you would for the MSC8101 device). Connect DONE to one of the EVNT pins, and DBREQ to HRRQ.

4 Ordering Information

Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order. Part Supply Voltage Package Type Pin Count Core Frequency (MHz) Solder Spheres Order Number MSC7116 1.2 V core

2.5 V memory

3.3 V I/O

Molded Array Process-Ball Grid Array (MAP-BGA) 400 266 Lead-free MSC7116VM1000 Lead-bearing MSC7116VF1000

Package Information

MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11 Freescale Semiconductor 53

5 Package Information

6 Product Documentation

 MSC711x Reference Manual (MSC711xRM). Includes functional descriptions of the extended cores and all the internal subsystems including configuration and programming information.  Application Notes. Cover various programming topics related to the StarCore DSP core and the MSC7116 device.  SC140/SC1400 DSP Core Reference Manual. Covers the SC140 and SC1400 core architecture, control registers, clock registers, program control, and instruction set. Figure 34. MSC7116 Mechanical Information, 400-pin MAP-BGA Package

1. All dimensions in millimeters.
2. Dimensioning and tolerancing
3. Maximum solder ball diameter

measured parallel to Datum A.

1. Datum A, the seating plane, is
2. Parallelism measurement shall

MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11

Revision History

7 Revision History

Table 36 provides a revision history for this data sheet. Table 36. Document Revision History 0 Sep. 2005  Initial public release. 1 May 2004  Added ordering information and new package options. 2 Aug. 2004  Updated clock parameter values.  Updated DDR timing specifications.  Updated I 2C timing specifications. 3 Sep. 2004  Updated Figures 1-2 and 1-2 to correct HDSP and DBREQ.  Corrected EE0 port reference.  Updated ball location for HDSP. 4 Jan. 2005  Added signal HA3.  Added note for timing reference for I 2C interface.  Expanded GPIO timing information.  Corrected pin T20 and K20 signal designation.  Corrected signal names to GPAO15 and IRQ2 .  Expanded design guidelines in Chapter 4. 5 Mar. 2005  Updated features list.  Updated power specifications.  Changed CLKIN frequency range.  Added clock configuration information. 6 Apr. 2005  Added recommended power supply ratings and updated equations to estimate power consumption. 7 Oct. 2005  Updated core and total power consumption examples. 8 Dec. 2005  Added information about the new mask set 1M88B. Affected all sections. 9 Nov. 2006  Updated arrows in Host DMA Writing Timing figure.  Updated boot overview in Section 4.4.3. 11 Jul. 2007  Updated to new data sheet format. Reorganized and renumbered sections, figures, and tables.  Removed all references to obsolete mask set 1L44X and corresponding specification values.  Added a note to clarify the definition of TCK timing 700 in new Table 31.  Reworked reset and boot sections. 2C boot information and added SPI boot information.  Removed obsolete part numbers.

MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11 Freescale Semiconductor 55

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