MSC1210Y4PAGR.B

MSC1210Y5 TI | Alldatasheet

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Technical content

FEATURES

/C006824 Bits No Missing Codes /C006822 Bits Effective Resolution at 10Hz − Low Noise: 75nV /C0068PGA From 1 to 128 /C0068Precision On-Chip Voltage Reference /C00688 Differential/Single-Ended Channels /C0068On-Chip Offset/Gain Calibration /C0068Offset Drift: 0.1ppm/°C /C0068Gain Drift: 0.5ppm/°C /C0068On-Chip Temperature Sensor /C0068Burnout Sensor Detection /C0068Single-Cycle Conversion /C0068Selectable Buffer Input DIGITAL FEATURES Microcontroller Core /C00688051-Compatible /C0068High-Speed Core − 4 Clocks per Instruction Cycle /C0068DC to 33MHz /C0068Single Instruction 121ns /C0068Dual Data Pointer Memory /C0068Up To 32kB Flash Memory /C0068Flash Memory Partitioning /C0068Endurance 1M Erase/Write Cycles,

100 Year Data Retention

/C0068In-System Serially Programmable /C0068External Program/Data Memory (64kB) /C00681,280 Bytes Data SRAM /C0068Flash Memory Security /C00682kB Boot ROM /C0068Programmable Wait State Control Peripheral Features /C006834 I/O Pins /C0068Additional 32-Bit Accumulator /C0068Three 16-Bit Timer/Counters /C0068System Timers /C0068Programmable Watchdog Timer /C0068Full-Duplex Dual USARTs /C0068Master/Slave SPI /C006816-Bit PWM /C0068Power Management Control /C0068Idle Mode Current < 1mA /C0068Stop Mode Current < 1/C0109A /C0068Programmable Brownout Reset /C0068Programmable Low Voltage Detect /C006824 Interrupt Sources /C0068Two Hardware Breakpoints GENERAL FEATURES /C0068Pin-Compatible with MSC1211/12/13/14 /C0068Package: TQFP-64 /C0068Low Power: 4mW /C0068Industrial Temperature Range: −40°C to +125°C /C0068Power Supply: 2.7V to 5.25V

APPLICATIONS

/C0068Industrial Process Control /C0068Instrumentation /C0068Liquid/Gas Chromatography /C0068Blood Analysis /C0068Smart Transmitters /C0068Portable Instruments /C0068Weigh Scales /C0068Pressure Transducers /C0068Intelligent Sensors /C0068Portable Applications /C0068DAS Systems MSC1210 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Precision Analog-to-Digital Converter (ADC) with 8051 Microcontroller and Flash Memory /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 www.ti.com Copyright  2002−2008, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com PACKAGE/ORDERING INFORMATION (1) PRODUCT FLASH MEMORY PACKAGE MARKING MSC1210Y2 4k MSC1210Y2MSC1210Y2 4k MSC1210Y2 MSC1210Y3 8k MSC1210Y3MSC1210Y3 8k MSC1210Y3 MSC1210Y4 16k MSC1210Y4MSC1210Y4 16k MSC1210Y4 MSC1210Y5 32k MSC1210Y5MSC1210Y5 32k MSC1210Y5 (1)For the most current package and ordering information, see the Package Option Addendum at the end of this datasheet, or refer to our web site at www.ti.com. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS (1) MSC1210Yx UNITS Analog Inputs Input current Momentary 100 mA Input current Continuous 10 mA Input voltage AGND − 0.3 to AVDD + 0.3 V Power Supply DV DD to DGND −0.3 to +6 V AVDD to AGND −0.3 to +6 V AGND to DGND −0.3 to +0.3 V VREF to AGND −0.3 to AVDD + 0.3 V Digital input voltage to DGND −0.3 to DVDD + 0.3 V Digital output voltage to DGND −0.3 to DVDD + 0.3 V Maximum junction temperature 150 °C Operating temperature range −40 to +125 °C Storage temperature range −65 to +150 °C Package power dissipation (TJ Max − TAMBIENT )//C0113JA W Output current, all pins 200 mA Output pin short-circuit 10 s Junction to ambient (/C0113JA) High K (2s 2p) 62.9 °C/W Thermal Resistance Junction to ambient (/C0113JA) Low K (1s) 78.2 °C/WThermal Resistance Junction to case (/C0113JC) 13.8 °C/W Digital Outputs Output current Continuous 100 mA I/O source/sink current 100 mA Power pin maximum 300 mA (1)Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. MSC1210YX FAMILY FEATURES FEATURES (1) MSC1210Y2 (2) MSC1210Y3 (2) MSC1210Y4 (2) MSC1210Y5 (2) Flash Program Memory (Bytes) Up to 4k Up to 8k Up to 16k Up to 32k Flash Data Memory (Bytes) Up to 4k Up to 8k Up to 16k Up to 32k Internal Scratchpad RAM (Bytes) 256 256 256 256 Internal MOVX RAM (Bytes) 1024 1024 1024 1024 Externally Accessible Memory (Bytes)64k Program, 64k Data 64k Program, 64k Data 64k Program, 64k Data 64k Program, 64k Data (1)All peripheral features are the same on all devices; the flash memory size is the only difference. (2)The last digit of the part number (N) represents the onboard flash size = (2N )kBytes.

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com ELECTRICAL CHARACTERISTICS: AV DD = 5V All specifications from TMIN to TMAX , DVDD = +2.7V to 5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise noted. MSC1210Yx PARAMETER CONDITIONS MIN TYP MAX UNITS Analog Input (AIN0-AIN7, AINCOM) Analog Input Range Buffer OFF AGND − 0.1 AVDD + 0.1 V Analog Input Range Buffer ON AGND + 50mV AVDD − 1.5 V Full-Scale Input Voltage Range (In+) − (In−) ±VREF /PGA V Differential Input Impedance Buffer OFF 7/PGA(5) M Ω Input Current Buffer ON 0.5 nA Fast Settling Filter −3dB 0.469 • fDATA Bandwidth Sinc2 Filter −3dB 0.318 • fDATABandwidth Sinc3 Filter −3dB 0.262 • fDATA Programmable Gain Amplifier User-Selectable Gain Range 1 128 Input Capacitance Buffer On 9 pF Input Leakage Current Multiplexer channel OFF, T = +25°C 0.5 pA Burnout Current Sources Buffer On 2 µA Offset DAC Offset DAC Range ±VREF /(2•PGA) V Offset DAC Monotonicity 8 Bits Offset DAC Gain Error ±1.5 % of Range Offset DAC Gain Error Drift 1 ppm/°C System Performance Resolution 24 Bits ENOB See Typical Characteristics Output Noise See Typical Characteristics No Missing Codes Sinc3 Filter, Decimation > 360 24 Bits Integral Nonlinearity End Point Fit, Differential Input ±0.0015 % of FSR Offset Error After Calibration 7.5 ppm of FS Offset Drift(1) Before Calibration 0.1 ppm of FS/°C Gain Error(2) After Calibration 0.002 % Gain Error Drift(1) Before Calibration 0.5 ppm/°C System Gain Calibration Range 80 120 % of FS System Offset Calibration Range −50 50 % of FS At DC 100 115 dB ADC Common-Mode Rejection fCM = 60Hz, fDATA = 10Hz 130 dB ADC Common-Mode Rejection fCM = 50Hz, fDATA = 50Hz 120 dB fCM = 60Hz, fDATA = 60Hz 120 dB Normal-Mode Rejection fSIG = 50Hz, fDATA = 50Hz 100 dB Normal-Mode Rejection fSIG = 60Hz, fDATA = 60Hz 100 dB Power-Supply Rejection At DC, dB = −20log(∆VOUT /∆VDD )(3) 80 88 dB (1) Calibration can minimize these errors. (2) The self-gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF. (3) ∆VOUT is change in digital result. (4) 9pF switched capacitor at fSAMP clock frequency (see Figure 14). (5) The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64).

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com ELECTRICAL CHARACTERISTICS: AV DD = 5V (continued) All specifications from TMIN to TMAX , DVDD = +2.7V to 5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise noted. MSC1210Yx PARAMETER UNITSMAXTYPMINCONDITIONS Voltage Reference Input Reference Input Range REF IN+, REF IN− AGND AVDD (2) V VREF VREF ≡ (REF IN+) − (REF IN−) 0.1 2.5 AVDD V VREF Common-Mode Rejection At DC 130 dB VREF Common-Mode Rejection fCM = 60Hz, fDATA = 60Hz 120 dB Input Current(4) VREF = 2.5V 3 µA On-Chip Voltage Reference Output Voltage VREFH = 1 at +25°C, ACLK = 1MHz 2.495 2.5 2.505 V Output Voltage VREFH = 0 at +25°C, ACLK = 1MHz 1.25 V Power-Supply Rejection Ratio 65 dB Short-Circuit Current Source 8 mA Short-Circuit Current Sink 50 µA Short-Circuit Duration Sink or Source Indefinite Drift 5 ppm/°C Output Impedance Sourcing 100µA 3 Ω Startup Time from Power On C REF = 0.1µF 8 ms Temperature Sensor Voltage T = +25°C 115 mV Temperature Sensor Coefficient 375 µV/°C Analog Power-Supply Requirements Analog Power-Supply Voltage AVDD 4.75 5.0 5.25 V Analog Current (IADC + IVREF ) PDADC = 1, ALVDIS = 1, DAB = 1 < 1 nA PGA = 1, Buffer OFF 200 µA Analog Power-Supply ADC Current PGA = 128, Buffer OFF 500 µA Power-Supply Current ADC Current (IADC ) PGA = 1, Buffer ON 240 µACurrent ADC PGA = 128, Buffer ON 850 µA VREF Supply Current (IVREF ) ADC ON, VREF = 2.5V 250 µA (1) Calibration can minimize these errors. (2) The self-gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF. (3) ∆VOUT is change in digital result. (4) 9pF switched capacitor at fSAMP clock frequency (see Figure 14). (5) The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64).

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com ELECTRICAL CHARACTERISTICS: AV DD = 3V All specifications from TMIN to TMAX , DVDD = +2.7V to 5.25V , fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and VREF ≡ (REF IN+) − (REF IN−) = +1.25V, unless otherwise noted. MSC1210Yx PARAMETER CONDITIONS MIN TYP MAX UNITS ANALOG INPUT (AIN0-AIN7, AINCOM) Analog Input Range Buffer OFF AGND − 0.1 AVDD + 0.1 V Analog Input Range Buffer ON AGND + 50mV AVDD − 1.5 V Full-Scale Input Voltage Range (In+) − (In−) ±VREF /PGA V Differential Input Impedance Buffer OFF 7/PGA(5) M Ω Input Current Buffer ON 0.5 nA Fast Settling Filter −3dB 0.469 • fDATA Bandwidth Sinc2 Filter −3dB 0.318 • fDATABandwidth Sinc3 Filter −3dB 0.262 • fDATA Programmable Gain Amplifier User-Selectable Gain Range 1 128 Input Capacitance 9 pF Input Leakage Current Multiplexer channel OFF, T = +25°C 0.5 pA Burnout Current Sources Sensor Input Open Circuit 2 µA OFFSET DAC Offset DAC Range ±VREF /(2•PGA) V Offset DAC Monotonicity 8 Bits Offset DAC Gain Error ±1.5 % of Range Offset DAC Gain Error Drift 1 ppm/°C SYSTEM PERFORMANCE Resolution 24 Bits ENOB See Typical Characteristics Output Noise See Typical Characteristics No Missing Codes Sinc3 Filter 24 Bits Integral Nonlinearity End Point Fit, Differential Input ±0.0015 % of FSR Offset Error After Calibration 7.5 ppm of FS Offset Drift(1) Before Calibration 0.1 ppm of FS/°C Gain Error(2) After Calibration 0.005 % Gain Error Drift(1) Before Calibration 0.5 ppm/°C System Gain Calibration Range 80 120 % of FS System Offset Calibration Range −50 50 % of FS At DC 100 115 dB ADC Common-Mode Rejection fCM = 60Hz, fDATA = 10Hz 130 dB ADC Common-Mode Rejection fCM = 50Hz, fDATA = 50Hz 120 dB fCM = 60Hz, fDATA = 60Hz 120 dB Normal-Mode Rejection fSIG = 50Hz, fDATA = 50Hz 100 dB Normal-Mode Rejection fSIG = 60Hz, fDATA = 60Hz 100 dB Power-Supply Rejection At DC, dB = −20log(∆VOUT/ ∆VDD )(3) 85 dB (1) Calibration can minimize these errors. (2) The self-gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF. (3) ∆VOUT is change in digital result. (4) 9pF switched capacitor at fSAMP clock frequency (see Figure 14). (5) The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64).

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com ELECTRICAL CHARACTERISTICS: AV DD = 3V (continued) All specifications from TMIN to TMAX , DVDD = +2.7V to 5.25V , fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and VREF ≡ (REF IN+) − (REF IN−) = +1.25V, unless otherwise noted. MSC1210Yx PARAMETER UNITSMAXTYPMINCONDITIONS VOLTAGE REFERENCE INPUT Reference Input Range REF IN+, REF IN− AGND AVDD (2) V VREF VREF ≡ (REF IN+) − (REF IN−) 0.1 1.25 AVDD V VREF Common-Mode Rejection At DC 130 dB VREF Common-Mode Rejection fCM = 60Hz, fDATA = 60Hz 120 dB Input Current(4) VREF = 1.25V 1.5 µA ON-CHIP VOLT AGE REFERENCE Output Voltage VREFH = 0 at +25°C, ACLK = 1MHz 1.245 1.25 1.255 V Power-Supply Rejection Ratio 65 dB Short-Circuit Current Source 8 mA Short-Circuit Current Sink 50 µA Short-Circuit Duration Sink or Source Indefinite Drift 5 ppm/°C Output Impedance Sourcing 100µA 3 Ω Startup Time from Power OFF C REF = 0.1µF 8 ms Temperature Sensor Voltage T = +25°C 115 mV Temperature Sensor Coefficient 375 µV/°C ANALOG POWER-SUPPLY REQUIREMENTS Analog Power-Supply Voltage AVDD 2.7 3.6 V Analog Current (IADC + IVREF ) PDADC = 1, ALVDIS = 1, DAB = 1 < 1 nA PGA = 1, Buffer OFF 200 µA Analog Power-Supply ADC Current PGA = 128, Buffer OFF 500 µA Power-Supply Current ADC Current (IADC ) PGA = 1, Buffer ON 240 µACurrent ADC PGA = 128, Buffer ON 850 µA VREF Supply Current (IVREF ) ADC ON, , VREF = 1.25V 240 µA (1) Calibration can minimize these errors. (2) The self-gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF. (3) ∆VOUT is change in digital result. (4) 9pF switched capacitor at fSAMP clock frequency (see Figure 14). (5) The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64).

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com DIGITAL CHARACTERISTICS: DV DD = 2.7V to 5.25V All specifications from TMIN to TMAX , fOSC = 1MHz, unless otherwise specified. MSC1210Yx PARAMETER CONDITIONS MIN TYP MAX UNITS DIGITAL POWER-SUPPL Y REQUIREMENTS Digital Power-Supply Voltage DV DD 2.7 3.0 3.6 V Normal Mode, fOSC = 1MHz 1.4 1.6 mA Normal Mode, fOSC = 8MHz 8 9 mA Stop Mode(1) 0.5 µA Digital Power-Supply Current DV DD 4.75 5.0 5.25 VDigital Power-Supply Current Normal Mode, fOSC = 1MHz 2 2.2 mA Normal Mode, fOSC = 8MHz 17 18 mA Stop Mode(1) 0.5 µA DIGITAL INPUT/OUTPUT (CMOS) Logic Level VIH (except XIN pin) 0.6 • DV DD DV DD V Logic Level VIL (except XIN pin) DGND 0.2 • DV DD V I/O Pin Hysteresis 700 mV Ports 0−3, Input Leakage Current, Input ModeVIH = DVD D or VIH = 0V < 1 pA Pins EA, XIN Input Leakage Current < 1 pA VOL , ALE, PSEN, Ports 0−3, All Output Modes IOL = 1mA DGND 0.4 V VOL , ALE, PSEN, Ports 0−3, All Output Modes IOL = 30mA 1.5 V VOH , ALE, PSEN, Ports 0−3, Strong Drive Output IOH = 1mA DV DD − 0.4 DV DD − 0.1 DV DD V VOH , ALE, PSEN, Ports 0−3, Strong Drive Output IOH = 30mA DV DD − 1.5 V Ports 0−3, Pull-Up Resistors 9 kΩ Pins ALE, PSEN, Pull-Up Resistors Flash Programming Mode Only 9 kΩ Pin RST, Pull-Down Resistor 500 kΩ (1) Digital Brownout Detect disabled (HCR1.2 = 1), Low Voltage Detect disabled (LVDCON.3 =1). Ports configured for CMOS output low. If in External Oscillation mode, the oscillator must be disabled. FLASH MEMORY CHARACTERISTICS: DV DD = 2.7V to 5.25V MSC1210Yx PARAMETER CONDITIONS MIN TYP MAX UNITS Flash Memory Endurance 100,000 1,000,000 cycles Flash Memory Data Retention 100 years Mass and Page Erase Time Set with FER in FTCON 10 ms Flash Memory Write Time Set with FWR in FTCON 30 40 µs Flash Programming Current DV DD = 3.0V 10 mA Flash Programming Current DV DD = 5.0V 25 mA

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com AC ELECTRICAL CHARACTERISTICS (1)(2): DVDD = 2.7V to 5.25V 2.7V to 3.6V 4.75V to 5.25V SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNITS System Clock External Crystal Frequency (fOSC ) 1 18 1 33 MHz 1/tCLK (4) 4 External Clock Frequency (fOSC ) 0 18 0 33 MHz1/tCLK (4) 4 External Ceramic Resonator Frequency (fOSC ) 1 16 1 16 MHz Program Memory tLHLL 1 ALE Pulse Width 1.5tCLK − 5 1.5tCLK − 5 ns tAVLL 1 Address Valid to ALE LOW 0.5tCLK − 10 0.5tCLK − 7 ns tLLAX 1 Address Hold After ALE LOW 0.5tCLK 0.5tCLK ns tLLIV 1 ALE LOW to Valid Instruction In 2.5tCLK − 35 2.5tCLK − 25 ns tLLPL 1 ALE LOW to PSEN LOW 0.5tCLK 0.5tCLK ns tPLPH 1 PSEN Pulse Width 2tCLK − 5 2tCLK − 5 ns tPLIV 1 PSEN LOW to Valid Instruction in 2tCLK − 40 2tCLK − 30 ns tPXIX 1 Input Instruction Hold After PSEN 5 −5 ns tPXIZ 1 Input Instruction Float After PSEN tCLK − 5 tCLK ns tAVIV 1 Address to Valid Instruction In 3tCLK − 40 3tCLK − 25 ns tPLAZ 1 PSEN LOW to Address Float 0 0 ns Data Memory tRLRH 2 RD Pulse Width (tMCS = 0)(5) 2tCLK − 5 2tCLK − 5 ns tRLRH 2 RD Pulse Width (tMCS > 0)(5) tMCS − 5 tMCS − 5 ns tWLWH 3 WR Pulse Width (tMCS = 0)(5) 2tCLK − 5 2tCLK − 5 ns tWLWH 3 WR Pulse Width (tMCS > 0)(5) tMCS − 5 tMCS − 5 ns tRLDV 2 RD LOW to Valid Data In (tMCS = 0)(5) 2tCLK − 40 2tCLK − 30 ns tRLDV 2 RD LOW to Valid Data In (tMCS > 0)(5) tMCS − 40 tMCS − 30 ns tRHDX 2 Data Hold After Read −5 −5 ns tRHDZ 2 Data Float After Read (tMCS = 0)(5) tCLK tCLK ns tRHDZ 2 Data Float After Read (tMCS > 0)(5) 2tCLK 2tCLK ns tLLDV 2 ALE LOW to Valid Data In (tMCS = 0)(5) 2.5tCLK − 40 2.5tCLK − 25 ns tLLDV 2 ALE LOW to Valid Data In (tMCS > 0)(5) tCLK + tMCS − 40 tCLK + tMCS − 25 ns tAVDV 2 Address to Valid Data In (tMCS = 0)(5) 3tCLK − 40 3tCLK − 25 ns tAVDV 2 Address to Valid Data In (tMCS > 0)(5) 1.5tCLK + tMCS − 40 1.5tCLK + tMCS − 25 ns tLLWL 2, 3 ALE LOW to RD or WR LOW (tMCS = 0)(5) 0.5tCLK − 5 0.5tCLK + 5 0.5tCLK − 5 0.5tCLK + 5 ns tLLWL 2, 3 ALE LOW to RD or WR LOW (tMCS > 0)(5) tCLK − 5 tCLK + 5 tCLK − 5 tCLK + 5 ns tAVWL 2, 3 Address to RD or WR LOW (tMCS = 0)(5) tCLK − 5 tCLK − 5 ns tAVWL 2, 3 Address to RD or WR LOW (tMCS > 0)(5) 2tCLK − 5 2tCLK − 5 ns tQVWX 3 Data Valid to WR Transition −8 −5 ns tWHQX 3 Data Hold After WR tCLK − 8 tCLK − 5 ns tRLAZ 2 RD LOW to Address Float −0.5tCLK − 5 −0.5tCLK − 5 ns tWHLH 2, 3 RD or WR HIGH to ALE HIGH (tMCS = 0)(5) −5 5 −5 5 ns tWHLH 2, 3 RD or WR HIGH to ALE HIGH (tMCS > 0)(5) tCLK − 5 tCLK + 5 tCLK − 5 tCLK + 5 ns External Clock tHIGH 4 HIGH Time(3) 15 10 ns tLOW 4 LOW Time (3) 15 10 ns tR 4 Rise Time(3) 5 5 ns tF 4 Fall Time(3) 5 5 ns (1)Parameters are valid over operating temperature range, unless otherwise specified. (2)Load capacitance for Port 0, ALE, and PSEN = 100pF; load capacitance for all other outputs = 80pF. (3)These values are characterized but not 100% production tested. (4)In the MSC1210, fOSC = fCLK. tCLK = 1/fosc = one oscillator clock period. (5)tMCS is a time period related to the Stretch MOVX selection. The following table shows the value of tMCS for each stretch selection: MD2 MD1 MD0 MOVX DURATION tMCS 0 0 0 2 Machine Cycles 0 0 0 1 3 Machine Cycles (default) 4tCLK 0 1 0 4 Machine Cycles 8tCLK 0 1 1 5 Machine Cycles 12tCLK 1 0 0 6 Machine Cycles 16tCLK 1 0 1 7 Machine Cycles 20tCLK 1 1 0 8 Machine Cycles 24tCLK 1 1 1 9 Machine Cycles 28tCLK

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com PIN ASSIGNMENTS PAG PACKAGE TQFP-64 (TOP VIEW) EA P0.6/AD6 P0.7/AD7 ALE PSEN/OSCCLK/MODCLK P2.7/A15 DV DD DGND P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A09 P2.0/A08 NC (1) XOUT XIN P3.0/RxD0 P3.1/TxD0 P3.2/INT0 P3.3/INT1/TONE/PWM P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD DV DD DGND RST DV DD DV DD NOTE: (1) NC pin must be left unconnected. P1.7/INT5/SCLK P1.6/INT4/MISO P1.5/INT3/MOSI P1.4/INT2/SS P1.3/TxD1 P1.2/RxD1 DV DD DGND P1.1/T2EX P1.0/T2 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 AGND AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6/EXTD AIN7/EXTA AINCOM AGND AV DD REF IN− REF IN+ REF OUT NC (1) 64 63 62 61 60 59 58 57 56 55 54 17 18 19 20 21 22 23 24 25 26 27 53 52 51 50 49 28 29 30 31 32 MSC1210 NC (1)

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com PIN DESCRIPTIONS PIN # NAME DESCRIPTION 1 XOUT The crystal oscillator pin XOUT supports parallel resonant AT cut fundamental frequency crystals and ceramic resonators. XOUT serves as the output of the crystal amplifier. 2 XIN The crystal oscillator pin XIN supports parallel resonant AT cut fundamental frequency crystals and ceramic resonators. XIN can also be an input if there is an external clock source instead of a crystal. PORT 3.x Alternate Name(s) Alternate Use P3.0 RxD0 Serial port 0 input P3.1 TxD0 Serial port 0 output P3.2 INT0 External interrupt 0 P3.3 INT1/TONE/PWM External interrupt 1/TONE/PWM output P3.4 T0 Timer 0 external input P3.5 T1 Timer 1 external input P3.6 WR External data memory write strobe P3.7 RD External data memory read strobe 11, 14, 15, 42, 58 DV DD Digital power supply 12, 41, 57 DGND Digital ground 13 RST A HIGH on the reset input for two tOSC periods resets the device. 16, 32, 33 NC No connection. This pin must be left unconnected. 17, 27 AGND Analog ground

18 AIN0 Analog input channel 0

19 AIN1 Analog input channel 1

20 AIN2 Analog input channel 2

21 AIN3 Analog input channel 3

22 AIN4 Analog input channel 4

23 AIN5 Analog input channel 5

24 AIN6, EXTD Analog input channel 6, digital low-voltage detect input, generates DLVD interrupt

25 AIN7, EXTA Analog input channel 7, analog low-voltage detect input, generates ALVD interrupt

26 AINCOM Analog common for single-ended inputs or analog input for differential inputs

28 AVDD Analog power supply. AVDD must rise above 2.0V to disable Analog Brownout Reset function.

29 REF IN– Voltage reference negative input (must be tied to AGND for internal VREF )

30 REF IN+ Voltage reference positive input

31 REF OUT Internal voltage reference output (tie to REF IN+ for internal VREF use)

PORT 2.x Alternate Name Alternate Use P2.0 A8 Address bit 8 P2.1 A9 Address bit 9 P2.2 A10 Address bit 10 P2.3 A11 Address bit 11 P2.4 A12 Address bit 12 P2.5 A13 Address bit 13 P2.6 A14 Address bit 14 P2.7 A15 Address bit 15

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com PIN DESCRIPTIONS (continued) PIN # DESCRIPTIONNAME

44 PSEN ,

OSCCLK, MODCLK Program store enable. Connected to optional external memory as a chip enable. PSEN provides an active low pulse. In programming mode, PSEN is used as an input along with ALE to define serial or parallel programming mode. PSEN is held HIGH for parallel programming mode and LOW for serial programming. This pin can also be selected (when not using external memory) to output the oscillator clock, modulator clock, HIGH, or LOW. Care should be taken so that loading on this pin does not inadvertently cause the device to enter programming mode. ALE PSEN Program Mode Selection(1) NC or DVDD NC or DVDD Normal operation (User Application mode)

0 NC or DVDD Parallel programming

NC or DVDD 0 Serial programming 0 0 Reserved 45 ALE Address Latch Enable: Used for latching the low byte of the address during an access to external memory. ALE is emitted at a constant rate of 1/4 the oscillator frequency, and can be used for external timing or clocking. One ALE pulse is skipped during each access to external data memory. In programming mode, ALE is used as an input along with PSEN to define serial or parallel programming mode. ALE is held HIGH for serial programming mode and LOW for parallel programming. This pin can also be selected (when not using external memory) to output HIGH or LOW. Care should be taken so that loading on this pin does not inadvertently cause the device to enter programming mode. 48 EA External Access Enable: EA must be externally held LOW at the end of RESET to enable the device to fetch code from external program memory locations starting with 0000h. No internal pull-up on this pin. PORT 0.x Alternate Name Alternate Use P0.0 AD0 Address/Data bit 0 P0.1 AD1 Address/Data bit 1 P0.2 AD2 Address/Data bit 2 P0.3 AD3 Address/Data bit 3 P0.4 AD4 Address/Data bit 4 P0.5 AD5 Address/Data bit 5 P0.6 AD6 Address/Data bit 6 P0.7 AD7 Address/Data bit 7 PORT 0.x Alternate Name(s) Alternate Use P1.0 T2 T2 input P1.1 T2EX T2 external input P1.2 RxD1 Serial port input P1.3 TxD1 Serial port output P1.4 INT2/SS External Interrupt / Slave Select P1.5 INT3/MOSI External Interrupt / Master Out−Slave In P1.6 INT4/MISO External Interrupt / Master In−Slave Out P1.7 INT5/SCK External Interrupt / Serial Clock (1)The program mode is changed during the falling edge of the reset signal.

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com TYPICAL CHARACTERISTICS AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625Hz, Bipolar, Buffer ON, and VREF = (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. EFFECTIVE NUMBER OF BITS vs DATA RATE ENOB (rms) Data Rate (SPS) 1 10 100 1000 Sinc3 Filter, Buffer OFF PGA1 PGA8 PGA32 PGA64 PGA128 EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO Decimation Ratio =fMOD fDATA 0 500 1000 1500 2000 PGA4 ENOB (rms) PGA1 PGA2 PGA16 PGA8 PGA32 PGA64 PGA128 Sinc3 Filter, Buffer OFF EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 0 500 1000 1500 2000 ENOB (rms) PGA4 PGA8 PGA1 PGA2 PGA16 PGA32 PGA64 PGA128 Decimation Ratio = fMOD fDATA Sinc3 Filter, Buffer ON EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 0 500 1000 1500 2000 ENOB (rms) PGA4 PGA8PGA1 PGA2 PGA16 PGA32 PGA64 PGA128 Decimation Ratio = fMOD fDATA AV DD =3 V ,S i n c3 Filter, VREF = 1.25V, Buffer OFF EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 0 500 1000 1500 2000 ENOB (rms) PGA4 PGA8 PGA1 PGA2 PGA16 PGA32 PGA64 PGA128 Decimation Ratio = fMOD fDATA AV DD =3 V ,S i n c3 Filter, VREF = 1.25V, Buffer ON EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 0 500 1000 1500 2000 ENOB (rms) PGA4 PGA8 PGA1 PGA2 PGA32 PGA128PGA16 PGA64 Decimation Ratio = fMOD fDATA Sinc2 Filter

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com TYPICAL CHARACTERISTICS (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625Hz, Bipolar, Buffer ON, and VREF = (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. FAST SETTLING FILTER EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 0 500 1000 Gain 1 Gain 16 Gain 128 1500 2000 ENOB 1500 Decimation Value EFFECTIVE NUMBER OF BITS vs fMOD (set with ACLK) ENOB (rms) Data Rate (SPS) 1 10 100 1k 10k 100k fMOD = 15.6kHz fMOD =6 2 . 5 k H z fMOD = 203kHz fMOD = 110kHz fMOD = 31.25kHz EFFECTIVE NUMBER OF BITS vs fMOD (set with ACLK) WITH FIXED DECIMATION ENOB (rms) Data Rate (SPS) 10 100 1k 10k 100k DEC = 2020 DEC = 255 DEC = 500 DEC = 50 DEC = 20 DEC = 10 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 NOISE vs INPUT SIGNAL V IN (V) Noise (rms, ppm of FS) 22.0 21.5 21.0 20.5 20.0 19.5 19.0 18.5 18.0 EFFECTIVE NUMBER OF BITS vs INPUT SIGNAL (Internal and External VREF ) VIN (V) ENOB (rms) External Internal 1.00010 1.00006 1.00002 0.99998 0.99994 0.99990 0.99986 GAIN vs TEMPERATURE −50 −30 10 −10 30 50 70 90 Gain (Normalized) Temperature ( C)°

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com TYPICAL CHARACTERISTICS (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625Hz, Bipolar, Buffer ON, and VREF = (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. −10 INTEGRAL NONLINEARITY vs INPUT SIGNAL VIN (V) INL (ppm of FS) −40/C0095C +25/C0095C +85/C0095C −10 −20 −30 INTEGRAL NONLINEARITY vs INPUT SIGNAL VIN (V) VIN = −VREF 0V IN =+ VREF VREF =A VDD , Buffer OFF INL (ppm of FS) ADC INTEGRAL NONLINEARITY vs V REF VREF (V) ADC INL (ppm of FS) Buffer OFF AV DD =3 V AV DD =5 V INL ERROR vs PGA PGA Setting INL (ppm of FS) 14 21 6 81 2 8 6432 100 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 MAXIMUM ANALOG SUPPLY CURRENT Analog Supply Voltage (V) Analog Supply Current (mA) PGA = 128 ADC ON Brownout Detect ON −40/C0095C +25/C0095C +85/C0095C 900 800 700 600 500 400 300 200 100 ADC CURRENT vs PGA PGA Setting 01 8 24 3 2 16 128 64 IADC (A ) AV DD = 5V, Buffer = ON AV DD = 3V, Buffer = ON Buffer = OFF Buffer = OFF µ

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com TYPICAL CHARACTERISTICS (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625Hz, Bipolar, Buffer ON, and VREF = (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. 4500 4000 3500 3000 2500 2000 1500 1000 500 HISTOGRAM OF OUTPUT DATA ppm of FS Number of Occurrences 2.510 2.508 2.506 2.504 2.502 2.500 2.498 2.496 2.494 2.492 2.490 VREFOUT vs LOAD CURRENT VREFOUT Current Load (mA) VREFOUT (V) −10 −12 OFFSET DAC: OFFSET vs TEMPERATURE Offset (ppm of FSR) −40 +25 +85 Temperature (°C) 1.00006 1.00004 1.00002 0.99998 0.99996 0.99994 OFFSET DAC: GAIN vs TEMPERATURE Normalized Gain −40 +25 +85 Temperature (°C) DIGITAL CURRENT vs FREQUENCY Clock Frequency (MHz) Supply Current (mA) 1 10 100 1000 100 5V All Periph ON 5V All Periph OFF 5V All Periph ON IDLE 3V All Periph ON 3V All Periph OFF 3V All Periph ON IDLE Clock Frequency (MHz) Digital Current (µA) 01 0 2 0 4 0 30 100 0.1 DIGITAL STOP CURRENT vs FREQUENCY with EXT CLOCK

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com TYPICAL CHARACTERISTICS (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625Hz, Bipolar, Buffer ON, and VREF = (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. DIGITAL SUPPLY CURRENT vs SUPPLY VOLTAGE Supply Voltage (V) Digital Supply Current (mA) −40 C +85 C +25 C °° NORMALIZED GAIN vs PGA PGA Setting Normalized Gain (%) 14 21 6 8 128 6432 101 100 Buffer ON Buffer OFF CMOS DIGITAL OUTPUT Output Current (mA) Output Voltage (V) 02 0 10 40 30 70 6050 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 Low Output Low Output 200 150 100 HISTOGRAM OF TEMPERATURE SENSOR VALUES Temperature Sensor Value (mV) 111.0 111.5 112.0 112.5 113.0 113.5 114.0 114.5 115.0 115.5 116.0 116.5 117.0 Number of Occurrences −11 −13 −15 Internal VREF (V) AV DD (V) 1.25V 2.5V INTERNAL V REF vs AVDD

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com

DESCRIPTION

The MSC1210Yx is a completely integrated family of mixed-signal devices incorporating a high-resolution delta-sigma ADC, 8-channel multiplexer, burnout current sources, selectable buffered input, offset DAC (digital-to-analog converter), PGA (programmable gain amplifier), temperature sensor, voltage reference, 8-bit microcontroller, Flash Program Memory, Flash Data Memory, and Data SRAM, as shown in Figure 8. On-chip peripherals include an additional 32-bit accumulator, an SPI-compatible serial port, dual USARTs, multiple digital input/output ports, watchdog timer, low-voltage detect, on-chip power-on reset, 16-bit PWM, and system timers, brownout reset, and three timer/counters. The device accepts low-level differential or single-ended signals directly from a transducer. The ADC provides 24 bits of resolution and 24 bits of no-missing-code performance using a Sinc 3 filter with a programmable sample rate. The ADC also has a selectable filter that allows for high-resolution single-cycle conversion. The microcontroller core is 8051 instruction set compatible. The microcontroller core is an optimized 8051 core that executes up to three times faster than the standard 8051 core, given the same clock source. That makes it possible to run the device at a lower external clock frequency and achieve the same performance at lower power than the standard 8051 core. The MSC1210Yx allows the user to uniquely configure the Flash and SRAM memory maps to meet the needs of their application. The Flash is programmable down to 2.7V using both serial and parallel programming methods. The Flash endurance is 1 million Erase/Write cycles. In addition, 1280 bytes of RAM are incorporated on-chip. The part has separate analog and digital supplies, which can be independently powered from 2.7V to +5.25V. At +3V operation, the power dissipation for the part is typically less than 4mW. The MSC1210Yx is packaged in a TQFP-64 package. The MSC1210Yx is designed for high-resolution measurement applications in smart transmitters, industrial process control, weigh scales, chromatography, and portable instrumentation. ACC MUX AGND +AV DD AV DD BUFFER PGA VREF Modulator Up to 32K FLASH 1.2K SRAM SPI Digital Filter 8051 SFR LVD BOR PORT1 PORT2 WDT Timers/ Counters Clock Generator PORT0 PORT3 EA SPI/EXT USART2 ADDR ADDR DATA Alternate Functions USART1 EXT RW 8− Bit PGA OffsetAIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AINCOM AGND REF OUT REF IN+ REF IN − DV DD DGND XIN XOUT ALE PSEN RST POR Temperature Sensor REF NOTE (1) REF IN− must be tied to AGND when using internal VREF . (1) Figure 8. Block Diagram

speed of 82.5MHz compared to the standard 8051 core. timing of software loops will be faster with the MSC1210. run at 4 clocks per increment. to speed block Data Memory moves. memory/peripheral interface or general-purpose I/O.

12 Cycles

4 Cycles

Figure 10. Comparison of MSC1210 Timing to Table 1. Memory Cycle Stretching. Stretching of bits in CKCON register (address 8Eh). Figure 9. Instruction Timing Cycle

instruction cycles through a software implementation. device used across several application platforms. board, and third-party developers also provide support. see the Idle Mode and Stop Mode sections. Figure 11. MSC1210 Timing Chain and Clock Control

associated with each component. differential input pair to negate any offset voltages. sink current to detect open or short circuits on the pins. On-chip diodes provide temperature sensing capability. all 1s, the diodes are connected to the input of the ADC. All other channels are open. Figure 12. MSC1210 ADC Structure

resolve to 75nV, as shown in Table 2. Table 2. ENOB versus PGA (Bipolar Mode) using the ODAC does not reduce the range of the ADC. and Decimation Ratio is set in [ADCON3:ADCON2]. complete system, can be reduced with calibration. both an offset and gain calibration. ratio, buffer, Power Supply, voltage reference, or PGA. NOTE: (1) MUX change may add one cycle. Figure 15. Filter Step Responses

frequency response of each filter is shown in Figure 16. used, then VREF should be disabled in ADCON0. performance for high−precision applications. Figure 16. Filter Frequency Responses

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com IDLE MODE Idle mode is entered by setting the IDLE bit in the Power Control register (PCON, 087h). In Idle mode, the CPU, Timer0, Timer1, and USARTs are stopped, but all other peripherals and digital pins remain active. The device can be returned to active mode via an active internal or external interrupt. This mode is typically used for reducing power consumption between ADC samples. By configuring the device prior to entering Idle mode, further power reductions can be achieved (while in Idle mode). These reductions include powering down peripherals not in use in the PDCON register (0F1h). STOP MODE Stop mode is entered by setting the STOP bit in the Power Control register (PCON, 087h). In Stop mode, all internal clocks are halted. This mode has the lowest power consumption. The device can be returned to active mode only via an external or power-on reset. By configuring the device prior to entering Stop mode, further power reductions can be achieved (while in Stop mode). These power reductions include halting the external clock into the device, configuring all digital I/O pins as open drain with low output drive, disabling the ADC buffer, disabling the internal V REF , and setting PDCON to 0FFh to power down all peripherals. In Stop mode, if the brownout reset is enabled, there is approximately 25µA of draw from the power supply. To achieve zero current (≈ 100nA) in Stop mode, disable the brownout reset via HCR1. In Stop mode, all digital pins retain their values. POWER CONSUMPTION CONSIDERATIONS The following suggestions will reduce current consumption: 1. Use the lowest supply voltage that will work in the application for both AVDD and DVDD . 2. Use the lowest clock frequency that will work in the application. 3. Use Idle mode and the system clock divider whenever possible. Note that the system clock divider also affects the ADC clock. 4. Avoid using 8051-compatible I/O mode on the I/O ports. The internal pull-up resistors will draw current when the outputs are low. 5. Use the delay line for Flash Memory control by setting the FRCM bit in the FMCON register (SFR EEh) 6. Power down peripherals when they are not needed. Refer to SFR PDCON, LVDCON, and ADCON0. MEMORY MAP The MSC1210 contains on-chip SFR, Flash Memory, Scratchpad SRAM Memory, Boot ROM, and SRAM. THe SFR registers are primarily used for control and status. The standard 8051 features and additional peripheral features of the MSC1210 are controlled through the SFR. Reading from an undefined SFR and writing to undefined SFR registers is not recommended, and will have indeterminate effects. Flash Memory is used for both Program Memory and Data Memory. The user has the ability to select the partition size of Program and Data Memories. The partition size is set through hardware configuration bits, which are programmed through either the parallel or serial programming methods. Both Program and Data Flash Memories are erasable and writable (programmable) in User Application mode (UAM). However, program execution can only occur from Program Memory. As an added precaution, a lock feature can be activated through the hardware configuration bits, which disables erase and writes to 4kB of Program Flash Memory or the entire Program Flash Memory in UAM. The MSC1210 includes 1kB of SRAM on-chip. SRAM starts at address 0 and is accessed through the MOVX instruction. This SRAM can also be located to start at 8400h and can be accessed as both Program and Data Memory.

overlap since they are accessed in different ways. externally via Ports 0 and 2. Flash Memory Programming mode. or thefaddr_data_readBoot ROM routine. Figure 18. Memory Map

Table 3. MSC1210 Flash Partitioning Table 4. MSC1210 Flash Memory Partitioning access external program memory. Program Memory that is being used for data storage. (during data bus timing) for internal memory access. space directly above the SRAM. The MOVX instruction is used to write the flash memory. Flash memory must be erased before it can be written. Flash memory is erased in 128 byte pages.

accessed using bit addressable instructions. Figure 21. Scratchpad Register Addressing or RET will decrement as well. DV DD for internal access, or DGND for external access. Table 5. If enabled the Boot ROM will appear from address Table 5. MSC1210 Maximum Internal Program download from the TI web site (www.ti.com).

Table 6. MSC1210 Boot ROM Routines

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com ACCESSING EXTERNAL MEMORY If external memory is used, P0 and P2 can be configured as address and data lines. If external memory is not used, P0 and P2 can be configured as general-purpose I/O lines through the Hardware Configuration Register. To enable access to external memory, bits 0 and 1 of the HCR1 register must be set to 0. When these bits are enabled all memory addresses for both internal and external memory will appear on ports 0 and 2. During the data portion of the cycle for internal memory, Port 0 will be zero for security purposes. Accesses to external memory are of two types: accesses to external Program Memory and accesses to external Data Memory. Accesses to external Program Memory use signal PSEN (program store enable) as the read strobe. Accesses to external Data Memory use RD or WR (alternate functions of P3.7 and P3.6) to strobe the memory. External Program Memory and external Data Memory may be combined if desired by applying the RD and PSEN signals to the inputs of an AND gate and using the output of the gate as the read strobe to the external Program/Data Memory. Program fetches from external Program Memory always use a 16-bit address. Accesses to external Data Memory can use either a 16-bit address (MOVX @DPTR) or an 8-bit address (MOVX @R I). If Port 2 is selected for external memory use (HCR1, bit 0), it cannot be used as general-purpose I/O. This bit (or Bit 1 of HCR1) also forces bits P3.6 and P3.7 to be used for WR and RD instead of I/O. Port 2, P3.6, and P3.7 should all be written to ‘1.’ If an 8-bit address is being used (MOVX @RI), the contents of the MPAGE (92h) SFR remain at the Port 2 pins throughout the external memory cycle. This will facilitate paging. In any case, the low byte of the address is time-multiplexed with the data byte on Port 0. The ADDR/DATA signals use CMOS drivers in the Port 0, Port 2, WR , and RD output buffers. Thus, in this application the Port 0 pins are not open-drain outputs, and do not require external pull-ups for high-speed access. Signal ALE (Address Latch Enable) should be used to capture the address byte into an external latch. The address byte is valid at the negative transition of ALE. Then, in a write cycle, the data byte to be written appears on Port 0 just before WR is activated, and remains there until after WR is deactivated. In a read cycle, the incoming byte is accepted at Port 0 just before the read strobe is deactivated. The functions of Port 0 and Port 2 are selected in Hardware Configuration Register 1. This can only be changed during the Flash Program mode. There is no conflict in the use of these registers; they will either be used as general-purpose I/O or for external memory access. The default state is for Port 0 and Port 2 to be used as general-purpose I/O. If an external memory access is attempted when they are configured as general-purpose I/O, the values of Port 0 and Port 2 will not be affected. External Program Memory is accessed under two conditions: 1. Whenever signal EA is LOW during reset, then all future accesses are external; or 2. Whenever the Program Counter (PC) contains a number that is outside of the internal Program Memory address range, if the ports are enabled. If Port 0 and Port 2 are selected for external memory, all 8 bits of Port 0 and Port 2, as well as P3.6 and P3.7, are dedicated to an output function and may not be used for general-purpose I/O. During external program fetches, Port 2 outputs the high byte of the PC. Programming Flash Memory There are four sections of Flash Memory for programming: 1. 128 configuration bytes. 2. Reset sector (4kB) (not to be confused with the 2kB Boot ROM). 3. Program Memory. 4. Data Memory. Flash Programming Mode There are two programming modes: parallel and serial. The programming mode is selected by the state of the ALE and PSEN signals during power-on reset. Serial programming mode is selected with PSEN = 0 and ALE = 1. Parallel programming mode is selected with PSEN = 1 and ALE = 0 (see Figure 22). If they are both HIGH, the MSC1210 will operate in normal user mode. Both signals LOW is a reserved mode and is not defined. Programming mode is exited with a reset (BOR, WDT, software, or POR) and the normal mode selected.

Table 7. Interrupt Summary (1)These interrupts set the AI flag (EICON.4) and are enabled by EAI (EICON.5). (3)Cleared automatically by hardware when interrupt vector occurs. (4)Globally enabled by EA (IE.7).

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Hardware Configuration Register 0 (HCR0)—Accessed Using SFR Registers CADDR and CDATA. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CADDR 7Fh EPMA PML RSL EBR EWDR DFSEL2 DFSEL1 DFSEL0 NOTE: HCR0 is programmable only in Flash Programming mode, but can be read in User Application mode using the CADDR and CDATA SFRs or the faddr_data_read Boot ROM routine. EPMA Enable Programming Memory Access (Security Bit). bit 7 0: After reset in programming modes, Flash Memory can only be accessed in UAM until a mass erase is done. 1: Fully Accessible (default) PML Program Memory Lock (PML has Priority Over RSL). bit 6 0: Enable all Flash Programming modes in program mode, can be written in UAM. 1: Enable read-only for program mode; cannot be written in UAM (default). RSL Reset Sector Lock. The reset sector can be used to provide another method of Flash Memory programming. This bit 5 will allow Program Memory updates without changing the jumpers for in-circuit code updates or program development. The code in this boot sector would then provide the monitor and programming routines with the ability to jump into the main Flash code when programming is finished. 0: Enable Reset Sector Writing 1: Enable Read-Only Mode for Reset Sector (4kB) (default) EBR Enable Boot ROM. Boot ROM is 2kB of code located in ROM, not to be confused with the 4kB Boot Sector located bit 4 in Flash Memory. 0: Disable Internal Boot ROM 1: Enable Internal Boot ROM (default) EWDR Enable Watchdog Reset. bit 3 0: Disable Watchdog Reset 1: Enable Watchdog Reset (default) DFSEL Data Flash Memory Size (see Table 3 and Table 4). bits 2−0 000: Reserved 001: 32kB, 16kB, 8kB, or 4kB Data Flash Memory 010: 16kB, 8kB, or 4kB Data Flash Memory 011: 8kB or 4kB Data Flash Memory 100: 4kB Data Flash Memory 101: 2kB Data Flash Memory 110: 1kB Data Flash Memory 111: No Data Flash Memory (default)

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Hardware Configuration Register 1 (HCR1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CADDR 7Eh DBLSEL1 DBLSEL0 ABLSEL1 ABLSEL0 DAB DDB EGP0 EGP23 NOTE: HCR1 is programmable only in Flash Programming mode, but can be read in User Application mode using the CADDR and CDATA SFRs or the faddr_data_read Boot ROM routine. DBLSEL Digital Brownout Level Select bits 7−6 00: 4.5V 01: 4.2V 10: 2.7V 11: 2.5V (default) ABLSEL Analog Brownout Level Select bits 5−4 00: 4.5V 01: 4.2V 10: 2.7V 11: 2.5V (default) DAB Disable Analog Power-Supply Brownout Reset bit 3 0: Enable Analog Brownout Reset 1: Disable Analog Brownout Reset (default) (will not disable unless AV DD > 2.0V) DDB Disable Digital Power-Supply Brownout Reset bit 2 0: Enable Digital Brownout Reset 1: Disable Digital Brownout Reset (default) EGP0 Enable General-Purpose I/O for Port 0 bit 1 0: Port 0 is Used for External Memory, P3.6 and P3.7 Used for WR and RD. 1: Port 0 is Used as General-Purpose I/O (default) EGP23 Enable General-Purpose I/O for Ports 2 and 3 bit 0 0: Port 2 is Used for External Memory, P3.6 and P3.7. Used for WR and RD. 1: Port 2 and Port3 are Used as General-Purpose I/O (default) Configuration Memory Programming Certain key functions such as Brownout Reset and Watchdog Timer are controlled by the hardware configuration bits. These bits are nonvolatile and can only be changed through serial and parallel programming. Other peripheral control and status functions, such as ADC configuration, timer setup, and Flash control, are controlled through the SFRs.

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com SFR Definitions (Boldface definitions indicate that the register is unique to the MSC1210Yx) ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET VALUES 81h SP 07h 82h DPL0 00h 83h DPH0 00h 84h DPL1 00h 85h DPH1 00h 86h DPS 0 0 0 0 0 0 0 SEL 00h 87h PCON SMOD 0 1 1 GF1 GF0 STOP IDLE 30h 88h TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00h GATE C/T M1 M0 GATE C/T M1 M0 00h 8Ah TL0 00h 8Bh TL1 00h 8Ch TH0 00h 8Dh TH1 00h 8Eh CKCON 0 0 T2M T1M T0M MD2 MD1 MD0 01h 8Fh MWS 0 0 0 0 0 0 0 MXWS 00h 90h P1 P1.7 INT5/SCK P1.6 INT4 /MISO P1.5 INT3 /MOSI P1.4 INT2/SS P1.3 TXD1 P1.2 RXD1 P1.1 T2EX P1.0 FFh 91h EXIF IE5 IE4 IE3 IE2 1 0 0 0 08h 92h MPAGE 00h 93h CADDR 00h 94h CDATA 00h 95h MCON BPSEL 0 0 RAMMAP 00h 96h 97h 98h SCON0 SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00h 99h SBUF0 00h 9Ah SPICON SCK2 SCK1 SCK0 0 ORDER MSTR CPHA CPOL 00h 9Bh SPIDATA 00h 9Dh SPITCON CLK_EN DRV_DLY DRV_EN 00h A1h PWMCON PPOL PWMSEL SPDSEL TPCNTL2 TPCNTL1 TPCNTL0 00h A2h PWMLOW TONELOW PWM7 TDIV7 PWM6 TDIV6 PWM5 TDIV5 PWM4 TDIV4 PWM3 TDIV3 PWM2 TDIV2 PWM1 TDIV1 PWM0 TDIV0 00h A3h PWMHI TONEHI PWM15 TDIV15 PWM14 TDIV14 PWM13 TDIV13 PWM12 TDIV12 PWM11 TDIV11 PWM10 TDIV10 PWM9 TDIV9 PWM8 TDIV8 00h A4h A5h PAI 0 0 0 0 PAI3 PAI2 PAI1 PAI0 00h A6h AIE ESEC ESUM EADC EMSEC ESPIT ESPIR EALV EDLVB 00h A7h AISTAT SEC SUM ADC MSEC SPIT SPIR ALVD DLVD 00h A8h IE EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 00h A9h BPCON BP 0 0 0 0 0 PMSEL EBP 00h AAh BPL 00h ABh BPH 00h ACh P0DDRL P03H P03L P02H P02L P01H P01L P00H P00L 00h ADh P0DDRH P07H P07L P06H P06L P05H P05L P04H P04L 00h

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com SFR Definitions (continued) (Boldface definitions indicate that the register is unique to the MSC1210Yx) ADDRESS RESET VALUESBIT 0BIT 1BIT 2BIT 3BIT 4BIT 5BIT 6BIT 7REGISTER AEh P1DDRL P13H P13L P12H P12L P11H P11L P10H P10L 00h AFh P1DDRH P17H P17L P16H P16L P15H P15L P14H P14L 00h B0h P3 P3.7 RD P3.6 WR P3.5 P3.4 P3.3 INT1 P3.2 INT0 P3.1 TXD0 P3.0 RXD0 FFh B1h P2DDRL P23H P23L P22H P22L P21H P21L P20H P20L 00h B2h P2DDRH P27H P27L P26H P26L P25H P25L P24H P24L 00h B3h P3DDRL P33H P33L P32H P32L P31H P31L P30H P30L 00h B4h P3DDRH P37H P37L P36H P36L P35H P35L P34H P34L 00h B5h B6h B7h B8h IP 1 PS1 PT2 PS0 PT1 PX1 PT0 PX0 80h B9h BAh BBh BCh BDh BEh BFh C0h SCON1 SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 00h C1h SBUF1 00h C2h C3h C4h C5h C6h EWU EWUWDT EWUEX1 EWUEX0 00h C7h C8h T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 00h C9h CAh RCAP2L 00h CBh RCAP2H 00h CCh TL2 00h CDh TH2 00h CEh CFh D0h PSW CY AC F0 RS1 RS0 OV F1 P 00h D1h OCL LSB 00h D2h OCM 00h D3h OCH MSB 00h D4h GCL LSB 5Ah D5h GCM ECh D6h GCH MSB 5Fh D7h ADMUX INP3 INP2 INP1 INP0 INN3 INN2 INN1 INN0 01h D8h EICON SMOD1 1 EAI AI WDTI 0 0 0 40h D9h ADRESL LSB 00h DAh ADRESM 00h

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com SFR Definitions (continued) (Boldface definitions indicate that the register is unique to the MSC1210Yx) ADDRESS RESET VALUESBIT 0BIT 1BIT 2BIT 3BIT 4BIT 5BIT 6BIT 7REGISTER DBh ADRESH MSB 00h DCh ADCON0 — BOD EVREF VREFH EBUF PGA2 PGA1 PGA0 30h DDh ADCON1 — POL SM1 SM0 — CAL2 CAL1 CAL0 0000_0000b DEh ADCON2 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 1Bh DFh ADCON3 0 0 0 0 0 DR10 DR9 DR8 06h E0h ACC 00h E1h SSCON SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 00h E2h SUMR0 00h E3h SUMR1 00h E4h SUMR2 00h E5h SUMR3 00h E6h ODAC 00h E7h LVDCON ALVDIS ALVD2 ALVD1 ALVD0 DLVDIS DLVD2 DLVD1 DLVD0 00h E8h EIE 1 1 1 EWDI EX5 EX4 EX3 EX2 E0h E9h HWPC0 0 0 0 0 0 0 MEMORY SIZE 0000_00xxb EAh HWPC1 0 0 0 0 0 0 0 0 00h EBh HDWVER xxh ECh Reserved 00h EDh Reserved 00h EEh FMCON 0 PGERA 0 FRCM 0 BUSY 1 0 02h EFh FTCON FER3 FER2 FER1 FER0 FWR3 FWR2 FWR1 FWR0 A5h F1h PDCON 0 0 0 PDPWM PDADC PDWDT PDST PDSPI 1Fh F2h PASEL 0 0 PSEN2 PSEN1 PSEN0 0 ALE1 ALE0 00h F3h F4h F5h F6h ACLK 0 FREQ6 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03h F7h SRST 0 0 0 0 0 0 0 RSTREQ 00h F8h EIP 1 1 1 PWDI PX5 PX4 PX3 PX2 E0h F9h SECINT WRT SECINT6 SECINT5 SECINT4 SECINT3 SECINT2 SECINT1 SECINT0 7Fh FAh MSINT WRT MSINT6 MSINT5 MSINT4 MSINT3 MSINT2 MSINT1 MSINT0 7Fh FBh USEC 0 0 0 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03h FCh MSECL 9Fh FDh MSECH 0Fh FEh HMSEC 63h FFh WDTCON EWDT DWDT RWDT WDCNT4 WDCNT3 WDCNT2 WDCNT1 WDCNT0 00h

Table 8. Special Function Register Cross Reference

Table 8. Special Function Register Cross Reference (continued)

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Port 0 (P0) 7 6 5 4 3 2 1 0 Reset Value P0.7−0 Port 0. This port functions as a multiplexed address/data bus during external memory access, and as a general- bits 7−0 purpose I/O port when external memory access is not needed. During external memory cycles, this port will contain the LSB of the address when ALE is HIGH, and Data when ALE is LOW. When used as a general-purpose I/O, this port drive is selected by P0DDRL and P0DDRH (ACh, ADh). Whether Port 0 is used as general-purpose I/O or for external memory access is determined by the Flash Configuration Register (HCR1.1) Stack Pointer (SP) 7 6 5 4 3 2 1 0 Reset Value SP .7−0 Stack Pointer. The stack pointer identifies the location where the stack will begin. The stack pointer is incremented bits 7−0 before every PUSH or CALL operation and decremented after each POP or RET/RETI. This register defaults to 07h after reset. Data Pointer Low 0 (DPL0) 7 6 5 4 3 2 1 0 Reset Value DPL0.7−0 Data Pointer Low 0. This register is the low byte of the standard 8051 16-bit data pointer. DPL0 and DPH0 are bits 7−0 used to point to non-scratchpad data RAM. The current data pointer is selected by DPS (SFR 86h). Data Pointer High 0 (DPH0) 7 6 5 4 3 2 1 0 Reset Value DPH0.7−0 Data Pointer High 0. This register is the high byte of the standard 8051 16-bit data pointer. DPL0 and DPH0 are bits 7−0 used to point to non-scratchpad data RAM. The current data pointer is selected by DPS (SFR 86h). Data Pointer Low 1 (DPL1) 7 6 5 4 3 2 1 0 Reset Value DPL1.7−0 Data Pointer Low 1. This register is the low byte of the auxiliary 16-bit data pointer. When the SEL bit (DPS.0, bits 7−0 SFR 86h) is set, DPL1 and DPH1 are used in place of DPL0 and DPH0 during DPTR operations.

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Data Pointer High 1 (DPH1) 7 6 5 4 3 2 1 0 Reset Value DPH1.7−0 Data Pointer High. This register is the high byte of the auxiliary 16-bit data pointer. When the SEL bit (DPS.0, bits 7−0 SFR 86h) is set, DPL1 and DPH1 are used in place of DPL0 and DPH0 during DPTR operations. Data Pointer Select (DPS) 7 6 5 4 3 2 1 0 Reset Value SFR 86h 0 0 0 0 0 0 0 SEL 00h SEL Data Pointer Select. This bit selects the active data pointer. bit 0 0: Instructions that use the DPTR will use DPL0 and DPH0. 1: Instructions that use the DPTR will use DPL1 and DPH1. Power Control (PCON) 7 6 5 4 3 2 1 0 Reset Value SFR 87h SMOD 0 1 1 GF1 GF0 STOP IDLE 30h SMOD Serial Port 0 Baud Rate Doubler Enable. The serial baud rate doubling function for Serial Port 0. bit 7 0: Serial Port 0 baud rate will be a standard baud rate. 1: Serial Port 0 baud rate will be double that defined by baud rate generation equation when using Timer 1. GF1 General-Purpose User Flag 1. This is a general-purpose flag for software control. bit 3 GF0 General-Purpose User Flag 0. This is a general-purpose flag for software control. bit 2 STOP Stop Mode Select. Setting this bit will halt the oscillator and block external clocks. This bit will always read as a 0. bit 1 All DACs and digital pins keep their respective output values. Exit with RESET. IDLE Idle Mode Select. Setting this bit will freeze the CPU, Timer 0, 1, and 2, and the USARTs; other peripherals remain bit 0 active. All DACs and digital pins keep their respective output values. This bit will always be read as a 0. Exit with AI (A6h) and EWU (C6h) interrupts.The internal reference remains unchanged.

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Timer/Counter Control (TCON) 7 6 5 4 3 2 1 0 Reset Value SFR 88h TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00h TF1 Timer 1 Overflow Flag. This bit indicates when Timer 1 overflows its maximum count as defined by the current mode. bit 7 This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine. 0: No Timer 1 overflow has been detected. 1: Timer 1 has overflowed its maximum count. TR1 Timer 1 Run Control. This bit enables/disables the operation of Timer 1. Halting this timer will preserve the current count bit 6 in TH1, TL1. 0: Timer is halted. 1: Timer is enabled. TF0 Timer 0 Overflow Flag. This bit indicates when Timer 0 overflows its maximum count as defined by the current mode. bit 5 This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 0 interrupt service routine. 0: No Timer 0 overflow has been detected. 1: Timer 0 has overflowed its maximum count. TR0 Timer 0 Run Control. This bit enables/disables the operation of Timer 0. Halting this timer will preserve the current bit 4 count in TH0, TL0. 0: Timer is halted. 1: Timer is enabled. IE1 Interrupt 1 Edge Detect. This bit is set when an edge/level of the type defined by IT1 is detected. If IT1 = 1, this bit bit 3 will remain set until cleared in software or the start of the External Interrupt 1 service routine. If IT1 = 0, this bit will inversely reflect the state of the INT1 pin. IT1 Interrupt 1 Type Select. This bit selects whether the INT1 pin will detect edge or level triggered interrupts. bit 2 0: INT1 is level triggered. 1: INT1 is edge triggered. IE0 Interrupt 0 Edge Detect. This bit is set when an edge/level of the type defined by IT0 is detected. If IT0 = 1, this bit bit 3 will remain set until cleared in software or the start of the External Interrupt 0 service routine. If IT0 = 0, this bit will inversely reflect the state of the INT0 pin. IT0 Interrupt 0 Type Select. This bit selects whether the INT0 pin will detect edge or level triggered interrupts. bit 2 0: INT0 is level triggered. 1: INT0 is edge triggered.

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Timer Mode Control (TMOD) 7 6 5 4 3 2 1 0 TIMER 1 TIMER 0 Reset Value SFR 89h GATE C/T M1 M0 GATE C/T M1 M0 Reset Value 00h GATE Timer 1 Gate Control. This bit enables/disables the ability of Timer 1 to increment. bit 7 0: Timer 1 will clock when TR1 = 1, regardless of the state of pin INT1. 1: Timer 1 will clock only when TR1 = 1 and pin INT1 = 1. C/T Timer 1 Counter/Timer Select. bit 6 0: Timer is incremented by internal clocks. 1: Timer is incremented by pulses on T1 pin when TR1 (TCON.6, SFR 88h) is 1. M1, M0 Timer 1 Mode Select. These bits select the operating mode of Timer 1. bits 5−4 M1 M0 MODE 0 0 Mode 0: 8-bit counter with 5-bit prescale. 0 1 Mode 1: 16 bits. 1 0 Mode 2: 8-bit counter with auto reload. 1 1 Mode 3: Timer 1 is halted, but holds its count. GATE Timer 0 Gate Control. This bit enables/disables the ability of Timer 0 to increment. bit 3 0: Timer 0 will clock when TR0 = 1, regardless of the state of pin INT0 (software control). 1: Timer 0 will clock only when TR0 = 1 and pin INT0 = 1 (hardware control). C/T Timer 0 Counter/Timer Select. bit 2 0: Timer is incremented by internal clocks. 1: Timer is incremented by pulses on pin T0 when TR0 (TCON.4, SFR 88h) is 1. M1, M0 Timer 0 Mode Select. These bits select the operating mode of Timer 0. bits 1−0 M1 M0 MODE 0 0 Mode 0: 8-bit counter with 5-bit prescale. 0 1 Mode 1: 16 bits. 1 0 Mode 2: 8-bit counter with auto reload. 1 1 Mode 3: Two 8-bit counters. Timer 0 LSB (TL0) 7 6 5 4 3 2 1 0 Reset Value TL0.7−0 Timer 0 LSB. This register contains the least significant byte of Timer 0. bits 7−0 Timer 1 LSB (TL1) 7 6 5 4 3 2 1 0 Reset Value TL1.7−0 Timer 1 LSB. This register contains the least significant byte of Timer 1. bits 7−0

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Timer 0 MSB (TH0) 7 6 5 4 3 2 1 0 Reset Value TH0.7−0 Timer 0 MSB. This register contains the most significant byte of Timer 0. bits 7−0 Timer 1 MSB (TH1) 7 6 5 4 3 2 1 0 Reset Value TH1.7−0 Timer 1 MSB. This register contains the most significant byte of Timer 1. bits 7−0 Clock Control (CKCON) 7 6 5 4 3 2 1 0 Reset Value SFR 8Eh 0 0 T2M T1M T0M MD2 MD1 MD0 01h T2M Timer 2 Clock Select. This bit controls the division of the system clock that drives Timer 2. This bit has no effect when bit 5 the timer is in baud rate generator or clock output mode. Clearing this bit to 0 maintains 8051 compatibility. This bit has no effect on instruction cycle timing. 0: Timer 2 uses a divide-by-12 of the crystal frequency. 1: Timer 2 uses a divide-by-4 of the crystal frequency. T1M Timer 1 Clock Select. This bit controls the division of the system clock that drives Timer 1. Clearing this bit to 0 bit 4 maintains 8051 compatibility. This bit has no effect on instruction cycle timing. 0: Timer 1 uses a divide-by-12 of the crystal frequency. 1: Timer 1 uses a divide-by-4 of the crystal frequency. T0M Timer 0 Clock Select. This bit controls the division of the system clock that drives Timer 0. Clearing this bit to 0 bit 3 maintains 8051 compatibility. This bit has no effect on instruction cycle timing. 0: Timer 0 uses a divide-by-12 of the crystal frequency. 1: Timer 0 uses a divide-by-4 of the crystal frequency. MD2, MD1, MD0 Stretch MOVX Select 2−0. These bits select the time by which external MOVX cycles are to be stretched. This bits 2−0 allows slower memory or peripherals to be accessed without using ports or manual software intervention. The width of the RD or WR strobe will be stretched by the specified interval, which will be transparent to the software except for the increased time to execute the MOVX instruction. All internal MOVX instructions on devices containing MOVX SRAM are performed at the 2 instruction cycle rate. MD2 MD1 MD0 STRETCH VALUE MOVX DURATION RD or WR STROBE WIDTH (SYS CLKs) RD or WR STROBE WIDTH (/C0109s) at 12MHz 0 0 0 0 2 Instruction Cycles 2 0.167 0 0 1 1 3 Instruction Cycles (default)(1) 4 0.333 0 1 0 2 4 Instruction Cycles 8 0.667 0 1 1 3 5 Instruction Cycles 12 1.000 1 0 0 4 6 Instruction Cycles 16 1.333 1 0 1 5 7 Instruction Cycles 20 1.667 1 1 0 6 8 Instruction Cycles 24 2.000 1 1 1 7 9 Instruction Cycles 28 2.333 (1)For applications without external memory, no extra cycle is needed. To increase speed, set MD2, MD1, and MD0 to ‘000’.

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Memory Write Select (MWS) 7 6 5 4 3 2 1 0 Reset Value SFR 8Fh 0 0 0 0 0 0 0 MXWS 00h MXWS MOVX Write Select. This allows writing to the internal Flash program memory. bit 0 0: No writes are allowed to the internal Flash program memory. 1: Writing is allowed to the internal Flash program memory, unless PML (HCR0) or RSL (HCR0) are on. Port 1 (P1) 7 6 5 4 3 2 1 0 Reset Value SFR 90h P1.7 INT5/SCK P1.6 INT4/MISO P1.5 INT3/MOSI P1.4 INT2/SS P1.3 TXD1 P1.2 RXD1 P1.1 T2EX P1.0 T2 FFh P1.7−0 General-Purpose I/O Port 1. This register functions as a general-purpose I/O port. In addition, all the pins have an bits 7−0 alternative function listed below. Each of the functions is controlled by several other SFRs. The associated Port 1 latch bit must contain a logic ‘1’ before the pin can be used in its alternate function capacity. To use the alternate function, set the appropriate mode in P1DDRL (SFR AEh), P1DDRH (SFR AFh). INT5/SCK External Interrupt 5. A falling edge on this pin will cause an external interrupt 5 if enabled. bit 7 SPI Clock. The master clock for SPI data transfers. INT4/MISO External Interrupt 4. A rising edge on this pin will cause an external interrupt 4 if enabled. bit 6 Master In Slave Out. For SPI data transfers, this pin receives data for the master and transmits data from the slave. INT3/MOSI External Interrupt 3. A falling edge on this pin will cause an external interrupt 3 if enabled. bit 5 Master Out Slave In. For SPI data transfers, this pin transmits master data and receives slave data. INT2/SS External Interrupt 2. A rising edge on this pin will cause an external interrupt 2 if enabled. bit 4 Slave Select. During SPI operation, this pin provides the select signal for the slave device but does not control the output drive of MISO. TXD1 Serial Port 1 Transmit. This pin transmits the serial Port 1 data in serial port modes 1, 2, 3, and emits the synchro- bit 3 nizing clock in serial port mode 0. RXD1 Serial Port 1 Receive. This pin receives the serial Port 1 data in serial port modes 1, 2, 3, and is a bidirectional data bit 2 transfer pin in serial port mode 0. T2EX Timer 2 Capture/Reload Trigger. A 1 to 0 transition on this pin will cause the value in the T2 registers to be bit 1 transferred into the capture registers, if enabled by EXEN2 (T2CON.3, SFR C8h). When in auto-reload mode, a 1 to 0 transition on this pin will reload the Timer 2 registers with the value in RCAP2L and RCAP2H if enabled by EXEN2 (T2CON.3, SFR C8h). T2 Timer 2 External Input. A 1 to 0 transition on this pin will cause Timer 2 to increment. bit 0

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com External Interrupt Flag (EXIF) 7 6 5 4 3 2 1 0 Reset Value SFR 91h IE5 IE4 IE3 IE2 1 0 0 0 08h IE5 External Interrupt 5 Flag. This bit will be set when a falling edge is detected on INT5. This bit must be cleared bit 7 manually by software. Setting this bit in software will cause an interrupt if enabled. IE4 External Interrupt 4 Flag. This bit will be set when a rising edge is detected on INT4. This bit must be cleared bit 6 manually by software. Setting this bit in software will cause an interrupt if enabled. IE3 External Interrupt 3 Flag. This bit will be set when a falling edge is detected on INT3. This bit must be cleared bit 5 manually by software. Setting this bit in software will cause an interrupt if enabled. IE2 External Interrupt 2 Flag. This bit will be set when a rising edge is detected on INT2. This bit must be cleared bit 4 manually by software. Setting this bit in software will cause an interrupt if enabled. Memory Page (MPAGE) 7 6 5 4 3 2 1 0 Reset Value SFR 92h 00h MPAGE The 8051 uses Port 2 for the upper 8 bits of the external data memory access by MOVX A,@Ri and MOVX @Ri,A bits 7−0 instructions. The MSC1210 uses register MPAGE instead of Port 2. To access external data memory using the MOVX A,@Ri and MOVX @Ri,A instructions, the user should preload the upper byte of the address into MPAGE (versus preloading into P2 for the standard 8051). Configuration Address Register (CADDR) (write-only) 7 6 5 4 3 2 1 0 Reset Value SFR 93h 00h CADDR Configuration Address Register. This register supplies the address for reading bytes in the 128 bytes of Flash bits 7−0 Configuration memory. This is a write-only register. CAUTION: If this register is written to while executing from Flash Memory, the CDATA register will be incorrect. The faddr_data_read routine in the Boot ROM can be used for this purpose. Configuration Data Register (CDATA) (read-only) 7 6 5 4 3 2 1 0 Reset Value SFR 94h 00h CDATA Configuration Data Register. This register will contain the data in the 128 bytes of Flash Configuration memory that bits 7−0 are located at the last written address in the CADDR register. This is a read-only register.

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Memory Control (MCON) 7 6 5 4 3 2 1 0 Reset Value SFR 95h BPSEL 0 0 — — — — RAMMAP 00h BPSEL Breakpoint Address Selection bit 7 Write: Select one of two Breakpoint registers: 0 or 1. 0: Select breakpoint register 0. 1: Select breakpoint register 1. Read: Provides the Breakpoint register that created the last interrupt: 0 or 1. RAMMAP Memory Map 1kB extended SRAM. bit 0 0: Address is: 0000h—03FFh (default) (Data Memory) 1: Address is 8400h—87FFh (Data and Program Memory) Serial Port 0 Control (SCON0) 7 6 5 4 3 2 1 0 Reset Value SFR 98h SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00h SM0−2 Serial Port 0 Mode. These bits control the mode of serial Port 0. Modes 1, 2, and 3 have 1 start and 1 stop bit in bits 7−5 addition to the 8 or 9 data bits. MODE SM0 SM1 SM2 FUNCTION LENGTH PERIOD 0 0 0 0 Synchronous 8 bits 12 pCLK (1) 0 0 0 1 Synchronous 8 bits 4 pCLK (1) 1(2) 0 1 0 Asynchronous 10 bits Timer 1 or 2 Baud Rate Equation 1(2) 0 1 1 Valid Stop Required(3) 10 bits Timer 1 Baud Rate Equation 2 1 0 0 Asynchronous 11 bits 64 pCLK (1) (SMOD = 0) 32 pCLK (1) (SMOD = 1) 2 1 0 1 Asynchronous with Multiprocessor Communication(4) 11 bits 64 pCLK (1) (SMOD = 0) 32 pCLK (1) (SMOD = 1) 3(2) 1 1 0 Asynchronous 11 bits Timer 1 or 2 Baud Rate Equation 3(2) 1 1 1 Asynchronous with Multiprocessor Communication(4) 11 bits Timer 1 or 2 Baud Rate Equation (1)pCLK will be equal to tCLK , except that pCLK will stop for IDLE. (2)For modes 1 and 3, the selection of Timer 1 or 2 for baud rate is specified via the T2CON (C8h) register. (3)RI_0 will only be activated when a valid STOP is received. (4)RI_0 will not be activated if bit 9 = 0. REN_0 Receive Enable. This bit enables/disables the serial Port 0 received shift register. bit 4 0: Serial Port 0 reception disabled. 1: Serial Port 0 received enabled (modes 1, 2, and 3). Initiate synchronous reception (mode 0). TB8_0 9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial Port 0 modes 2 and 3. bit 3 RB8_0 9th Received Bit State. This bit identifies the state of the 9th reception bit of received data in serial Port 0 modes bit 2 2 and 3. In serial port mode 1, when SM2_0 = 0, RB8_0 is the state of the stop bit. RB8_0 is not used in mode 0. TI_0 Transmitter Interrupt Flag. This bit indicates that data in the serial Port 0 buffer has been completely shifted out. In serial bit 1 port mode 0, TI_0 is set at the end of the 8th data bit. In all other modes, this bit is set at the end of the last data bit. This bit must be manually cleared by software. RI_0 Receiver Interrupt Flag. This bit indicates that a byte of data has been received in the serial Port 0 buffer. In serial bit 0 port mode 0, RI_0 is set at the end of the 8th bit. In serial port mode 1, RI_0 is set after the last sample of the incoming stop bit subject to the state of SM2_0. In modes 2 and 3, RI_0 is set after the last sample of RB8_0. This bit must be manually cleared by software.

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Serial Data Buffer 0 (SBUF0) 7 6 5 4 3 2 1 0 Reset Value SFR 99h 00h SBUF0 Serial Data Buffer 0. Data for Serial Port 0 is read from or written to this location. The serial transmit and receive bits 7−0 buffers are separate registers, but both are addressed at this location. SPI Control (SPICON). Any change resets the SPI interface, counters, and pointers. PDCON controls which is enabled. 7 6 5 4 3 2 1 0 Reset Value SFR 9Ah SCK2 SCK1 SCK0 0 ORDER MSTR CPHA CPOL 00h SCK SCK Selection. Selection of tCLK divider for generation of SCK in Master mode. bits 7−5 SCK2 SCK1 SCK0 SCK PERIOD 0 0 0 tCLK /2 0 0 1 tCLK /4 0 1 0 tCLK /8 0 1 1 tCLK /16 1 0 0 tCLK /32 1 0 1 tCLK /64 1 1 0 tCLK /128 1 1 1 tCLK /256 ORDER Set Bit Order for Transmit and Receive. bit 3 0: Most Significant Bits First 1: Least Significant Bits First MSTR SPI Master Mode. bit 2 0: Slave Mode 1: Master Mode CPHA Serial Clock Phase Control. bit 1 0: Valid data starting from half SCK period before the first edge of SCK 1: Valid data starting from the first edge of SCK CPOL Serial Clock Polarity. bit 0 0: SCK idle at logic LOW 1: SCK idle at logic HIGH SPI Data Register (SPIDATA) 7 6 5 4 3 2 1 0 Reset Value SFR 9Bh 00h SPIDATA SPI Data Register. Data for SPI is read from or written to this location. The SPI transmit and receive buffers are bits 7−0 separate registers, but both are addressed at this location. Read to clear the receive interrupt and write to clear the transmit interrupt.

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com SPI Transmit Control Register (SPITCON) 7 6 5 4 3 2 1 0 Reset Value SFR 9Dh CLK_EN DRV_DLY DRV_EN 00h CLK_EN SCK Driver Enable. bit 5 0: Disable SCK Driver (Master Mode) 1: Enable SCK Driver (Master Mode) DRV_DLY Drive Delay. (Refer to DRV_EN bit) bit 4 0: Drive output immediately 1: Drive output after current byte transfer DRV_EN Drive Enable. bit 3 DRV_DLY DRV_EN MOSI or MISO OUTPUT CONTROL 0 0 Tristate immediately 0 1 Drive immediately 1 0 Tristate after the current byte transfer 1 1 Drive after the current byte transfer Port 2 (P2) 7 6 5 4 3 2 1 0 Reset Value SFR A0h FFh P2 Port 2. This port functions as an address bus during external memory access, and as a general-purpose I/O port. bits 7−0 During external memory cycles, this port will contain the MSB of the address. Whether Port 2 is used as general-purpose I/O or for external memory access is determined by the Flash Configuration Register (HCR1.0). PWM Control (PWMCON) 7 6 5 4 3 2 1 0 Reset Value SFR A1h — — PPOL PWMSEL SPDSEL TPCNTL2 TPCNTL1 TPCNTL0 00h PPOL Period Polarity. Specifies the starting level of the PWM pulse. bit 5 0: ON Period. PWM Duty register programs the ON period. 1: OFF Period. PWM Duty register programs the OFF period. PWMSEL PWM Register Select. Select which 16-bit register is accessed by PWMLOW/PWMHIGH. bit 4 0: Period (must be 0 for TONE mode) 1: Duty SPDSEL Speed Select. bit 3 0: 1MHz (the USEC Clock) 1: SYSCLK TPCNTL Tone Generator/Pulse Width Modulation Control. bits 2−0 TPCNTL.2 TPCNTL.1 TPCNTL.0 MODE 0 0 0 Disable (default) 0 0 1 PWM 0 1 1 TONE—Square 1 1 1 TONE—Staircase

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Tone Low (TONELOW)/PWM Low (PWMLOW) 7 6 5 4 3 2 1 0 Reset Value SFR A2h TDIV7 PWM7 TDIV6 PWM6 TDIV5 PWM5 TDIV4 PWM4 TDIV3 PWM3 TDIV2 PWM2 TDIV1 PWM1 TDIV0 PWM0 00h TDIV7−0 Tone Divisor. The low order bits that define the half-time period. For staircase mode the output is high impedance bits 7−0 for the last 1/4 of this period. PWMLOW Pulse Width Modulator Low Bits. These 8 bits are the least significant 8 bits of the PWM register. bits 7−0 Tone High (TONEHI)/PWM High (PWMHI) 7 6 5 4 3 2 1 0 Reset Value SFR A3h TDIV15 PWM15 TDIV14 PWM14 TDIV13 PWM13 TDIV12 PWM12 TDIV11 PWM11 TDIV10 PWM10 TDIV9 PWM9 TDIV8 PWM8 00h TDIV15−8 Tone Divisor. The high order bits that define the half time period. For staircase mode the output is high impedance bits 7−0 for the last 1/4 of this period. PWMHI Pulse Width Modulator High Bits. These 8 bits are the high order bits of the PWM register. bits 7−0 Pending Auxiliary Interrupt (PAI) 7 6 5 4 3 2 1 0 Reset Value SFR A5h — — — — PAI3 PAI2 PAI1 PAI0 00h PAI Pending Auxiliary Interrupt Register. The results of this register can be used as an index to vector to the bits 3−0 appropriate interrupt routine. All of these interrupts vector through address 0033h. PAI3 PAI2 PAI1 PAI0 AUXILIARY INTERRUPT STATUS 0 0 0 0 No Pending Auxiliary IRQ 0 0 0 1 Digital Low Voltage IRQ Pending 0 0 1 0 Analog Low Voltage IRQ Pending 0 0 1 1 SPI Receive IRQ Pending. 0 1 0 0 SPI Transmit IRQ Pending. 0 1 0 1 One Millisecond System Timer IRQ Pending. 0 1 1 0 Analog-to-Digital Conversion IRQ Pending. 0 1 1 1 Accumulator IRQ Pending. 1 0 0 0 One Second System Timer IRQ Pending.

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Auxiliary Interrupt Enable (AIE) 7 6 5 4 3 2 1 0 Reset Value SFR A6h ESEC ESUM EADC EMSEC ESPIT ESPIR EALV EDLVB 00h Interrupts are enabled by EICON.4 (SFR D8H ). The other interrupts are controlled by the IE and EIE registers. ESEC Enable Seconds Timer Interrupt (lowest priority auxiliary interrupt). bit 7 Write: Set mask bit for this interrupt 0 = masked, 1 = enabled. Read: Current value of Seconds Timer Interrupt before masking. ESUM Enable Summation Interrupt. bit 6 Write: Set mask bit for this interrupt 0 = masked, 1 = enabled. Read: Current value of Summation Interrupt before masking. EADC Enable ADC Interrupt. bit 5 Write: Set mask bit for this interrupt 0 = masked, 1 = enabled. Read: Current value of ADC Interrupt before masking. EMSEC Enable Millisecond System Timer Interrupt. bit 4 Write: Set mask bit for this interrupt 0 = masked, 1 = enabled. Read: Current value of Millisecond System Timer Interrupt before masking. ESPIT Enable SPI Transmit Interrupt. bit 3 Write: Set mask bit for this interrupt 0 = masked, 1 = enabled. Read: Current value of SPI Transmit Interrupt before masking. ESPIR Enable SPI Receive Interrupt. bit 2 Write: Set mask bit for this interrupt 0 = masked, 1 = enabled. Read: Current value of SPI Receive Interrupt before masking. EALV Enable Analog Low Voltage Interrupt. bit 1 Write: Set mask bit for this interrupt 0 = masked, 1 = enabled. Read: Current value of Analog Low Voltage Interrupt before masking. EDLVB Enable Digital Low Voltage or Breakpoint Interrupt (highest priority auxiliary interrupt). bit 0 Write: Set mask bit for this interrupt 0 = masked, 1 = enabled. Read: Current value of Digital Low Voltage or Breakpoint Interrupt before masking.

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Auxiliary Interrupt Status Register (AISTAT) 7 6 5 4 3 2 1 0 Reset Value SFR A7h SEC SUM ADC MSEC SPIT SPIR ALVD DLVD 00h SEC Second System Timer Interrupt Status Flag (lowest priority AI). bit 7 0: SEC interrupt inactive or masked. 1: SEC Interrupt active. (It is set inactive by reading the SECINT register.) SUM Summation Register Interrupt Status Flag. bit 6 0: SUM interrupt inactive or masked. 1: SUM interrupt active. (It is set inactive by reading the lowest byte of the Summation register.) ADC ADC Interrupt Status Flag. bit 5 0: ADC interrupt inactive or masked (If active, it is set inactive by reading the lowest byte of the Data Output Register). 1: ADC interrupt active. (If active, no new data will be written to the Data Output Register.) MSEC Millisecond System Timer Interrupt Status Flag. bit 4 0: MSEC interrupt inactive or masked. 1: MSEC interrupt active. (It is set inactive by reading the MSINT register.) SPIT SPI Transmit Interrupt Status Flag. bit 3 0: SPI transmit interrupt inactive or masked. 1: SPI transmit interrupt active. (It is set inactive by writing to the SPIDATA register.) SPIR SPI Receive Interrupt Status Flag. bit 2 0: SPI receive interrupt inactive or masked. 1: SPI receive interrupt active. (It is set inactive by reading from the SPIDATA register.) ALVD Analog Low Voltage Detect Interrupt Status Flag. bit 1 0: ALVD interrupt inactive or masked. 1: ALVD interrupt active. (Interrupt stays active until the AVDD voltage exceeds the threshold.) DLVD Digital Low Voltage Detect or Breakpoint Interrupt Status Flag (highest priority AI). bit 0 0: DLVD interrupt inactive or masked. 1: DLVD interrupt active. (Interrupt stays active until the DVDD voltage exceeds the threshold or the Breakpoint is cleared.)

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Interrupt Enable (IE) 7 6 5 4 3 2 1 0 Reset Value SFR A8h EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 00h EA Global Interrupt Enable. This bit controls the global masking of all interrupts except those in AIE (SFR A6h). bit 7 0: Disable interrupt sources. This bit overrides individual interrupt mask settings for this register. 1: Enable all individual interrupt masks. Individual interrupts in this register will occur if enabled. ES1 Enable Serial Port 1 Interrupt. This bit controls the masking of the serial Port 1 interrupt. bit 6 0: Disable all serial Port 1 interrupts. 1: Enable interrupt requests generated by the RI_1 (SCON1.0, SFR C0h) or TI_1 (SCON1.1, SFR C0h) flags. ET2 Enable Timer 2 Interrupt. This bit controls the masking of the Timer 2 interrupt. bit 5 0: Disable all Timer 2 interrupts. 1: Enable interrupt requests generated by the TF2 flag (T2CON.7, SFR C8h). ES0 Enable Serial port 0 interrupt. This bit controls the masking of the serial Port 0 interrupt. bit 4 0: Disable all serial Port 0 interrupts. 1: Enable interrupt requests generated by the RI_0 (SCON0.0, SFR 98h) or TI_0 (SCON0.1, SFR 98h) flags. ET1 Enable Timer 1 Interrupt. This bit controls the masking of the Timer 1 interrupt. bit 3 0: Disable Timer 1 interrupt. 1: Enable interrupt requests generated by the TF1 flag (TCON.7, SFR 88h). EX1 Enable External Interrupt 1. This bit controls the masking of external interrupt 1. bit 2 0: Disable external interrupt 1. 1: Enable interrupt requests generated by the INT1 pin. ET0 Enable Timer 0 Interrupt. This bit controls the masking of the Timer 0 interrupt. bit 1 0: Disable all Timer 0 interrupts. 1: Enable interrupt requests generated by the TF0 flag (TCON.5, SFR 88h). EX0 Enable External Interrupt 0. This bit controls the masking of external interrupt 0. bit 0 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the INT0 pin.

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Breakpoint Control (BPCON) 7 6 5 4 3 2 1 0 Reset Value SFR A9h BP 0 0 0 0 0 PMSEL EBP 00h Writing to register sets the breakpoint condition specified by MCON, BPL, and BPH. BP Breakpoint Interrupt. This bit indicates that a break condition has been recognized by a hardware breakpoint register(s). bit 7 Read: Status of Breakpoint Interrupt. Will indicate a breakpoint match for any of the breakpoint registers. Write: 0: No effect. 1: Clear Breakpoint 1 for breakpoint register selected by MCON (SFR 95h). PMSEL Program Memory Select. Write this bit to select memory for address breakpoints of register selected in bit 1 MCON (SFR 95h). 0: Break on address in data memory. 1: Break on address in program memory. EBP Enable Breakpoint. This bit enables this breakpoint register. Address of breakpoint register selected by bit 0 MCON (SFR 95h). 0: Breakpoint disabled. 1: Breakpoint enabled. Breakpoint Low (BPL) Address for BP Register Selected in MCON (95h) 7 6 5 4 3 2 1 0 Reset Value BPL.7−0 Breakpoint Low Address. The low 8 bits of the 16-bit breakpoint address. bits 7−0 Breakpoint High Address (BPH) Address for BP Register Selected in MCON (95h) 7 6 5 4 3 2 1 0 Reset Value BPH.7−0 Breakpoint High Address. The high 8 bits of the 16-bit breakpoint address. bits 7−0

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Port 0 Data Direction Low Register (P0DDRL) 7 6 5 4 3 2 1 0 Reset Value SFR ACh P03H P03L P02H P02L P01H P01L P00H P00L 00h P0.3 Port 0 Bit 3 Control. bits 7−6 P03H P03L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P0.2 Port 0 Bit 2 Control. bits 5−4 P02H P02L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P0.1 Port 0 Bit 1 Control. bits 3−2 P01H P01L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P0.0 Port 0 Bit 0 Control. bits 1−0 P00H P00L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input NOTE : Port 0 also controlled by EA and Memory Access Control HCR1.1.

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Port 0 Data Direction High Register (P0DDRH) 7 6 5 4 3 2 1 0 Reset Value SFR ADh P07H P07L P06H P06L P05H P05L P04H P04L 00h P0.7 Port 0 Bit 7 Control. bits 7−6 P07H P07L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P0.6 Port 0 Bit 6 Control. bits 5−4 P06H P06L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P0.5 Port 0 Bit 5 Control. bits 3−2 P05H P05L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P0.4 Port 0 Bit 4 Control. bits 1−0 P04H P04L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input NOTE : Port 0 also controlled by EA and Memory Access Control HCR1.1.

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Port 1 Data Direction Low Register (P1DDRL) 7 6 5 4 3 2 1 0 Reset Value SFR AEh P13H P13L P12H P12L P11H P11L P10H P10L 00h P1.3 Port 1 Bit 3 Control. bits 7−6 P13H P13L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P1.2 Port 1 Bit 2 Control. bits 5−4 P12H P12L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P1.1 Port 1 Bit 1 Control. bits 3−2 P11H P11L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P1.0 Port 1 Bit 0 Control. bits 1−0 P10H P10L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Port 1 Data Direction High Register (P1DDRH) 7 6 5 4 3 2 1 0 Reset Value SFR AFh P17H P17L P16H P16L P15H P15L P14H P14L 00h P1.7 Port 1 Bit 7 Control. bits 7−6 P17H P17L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P1.6 Port 1 Bit 6 Control. bits 5−4 P16H P16L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P1.5 Port 1 Bit 5 Control. bits 3−2 P15H P15L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P1.4 Port 1 Bit 4 Control. bits 1−0 P14H P14L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Port 3 (P3) 7 6 5 4 3 2 1 0 Reset Value SFR B0h P3.7 RD P3.6 WR P3.5 P3.4 P3.3 INT1 P3.2 INT0 P3.1 TXD0 P3.0 RXD0 FFh P3.7−0 General-Purpose I/O Port 3. This register functions as a general-purpose I/O port. In addition, all the pins have an bits 7−0 alternative function listed below. Each of the functions is controlled by several other SFRs. The associated Port 3 latch bit must contain a logic ‘1’ before the pin can be used in its alternate function capacity. RD External Data Memory Read Strobe. This pin provides an active low read strobe to an external memory device. bit 7 If Port 0 or Port 2 is selected for external memory in the HCR1 register, this function will be enabled even if a ‘1’ is not written to this latch bit. When external memory is selected, the settings of P3DRRH are ignored. WR External Data Memory Write Strobe. This pin provides an active low write strobe to an external memory device. bit 6 If Port 0 or Port 2 is selected for external memory in the HCR1 register, this function will be enabled even if a ‘1’ is not written to this latch bit. When external memory is selected, the settings of P3DRRH are ignored. T1 Timer/Counter 1 External Input. A 1 to 0 transition on this pin will increment Timer 1. bit 5 T0 Timer/Counter 0 External Input. A 1 to 0 transition on this pin will increment Timer 0. bit 4 INT1 External Interrupt 1. A falling edge/low level on this pin will cause an external interrupt 1 if enabled. bit 3 INT0 External Interrupt 0. A falling edge/low level on this pin will cause an external interrupt 0 if enabled. bit 2 TXD0 Serial Port 0 Transmit. This pin transmits the serial Port 0 data in serial port modes 1, 2, 3, and emits the bit 1 synchronizing clock in serial port mode 0. RXD0 Serial Port 0 Receive. This pin receives the serial Port 0 data in serial port modes 1, 2, 3, and is a bidirectional data bit 0 transfer pin in serial port mode 0.

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Port 2 Data Direction Low Register (P2DDRL) 7 6 5 4 3 2 1 0 Reset Value SFR B1h P23H P23L P22H P22L P21H P21L P20H P20L 00h P2.3 Port 2 Bit 3 Control. bits 7−6 P23H P23L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P2.2 Port 2 Bit 2 Control. bits 5−4 P22H P22L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P2.1 Port 2 Bit 1 Control. bits 3−2 P21H P21L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P2.0 Port 2 Bit 0 Control. bits 1−0 P20H P20L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input NOTE : Port 2 also controlled by EA and Memory Access Control HCR1.1.

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Port 2 Data Direction High Register (P2DDRH) 7 6 5 4 3 2 1 0 Reset Value SFR B2h P27H P27L P26H P26L P25H P25L P24H P24L 00h P2.7 Port 2 Bit 7 Control. bits 7−6 P27H P27L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P2.6 Port 2 Bit 6 Control. bits 5−4 P26H P26L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P2.5 Port 2 Bit 5 Control. bits 3−2 P25H P25L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P2.4 Port 2 Bit 4 Control. bits 1−0 P24H P24L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input NOTE : Port 2 also controlled by EA and Memory Access Control HCR1.1.

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Port 3 Data Direction Low Register (P3DDRL) 7 6 5 4 3 2 1 0 Reset Value SFR B3h P33H P33L P32H P32L P31H P31L P30H P30L 00h P3.3 Port 3 Bit 3 Control. bits 7−6 P33H P33L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P3.2 Port 3 Bit 2 Control. bits 5−4 P32H P32L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P3.1 Port 3 Bit 1 Control. bits 3−2 P31H P31L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P3.0 Port 3 Bit 0 Control. bits 1−0 P30H P30L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Port 3 Data Direction High Register (P3DDRH) 7 6 5 4 3 2 1 0 Reset Value SFR B4h P37H P37L P36H P36L P35H P35L P34H P34L 00h P3.7 Port 3 Bit 7 Control. bits 7−6 P37H P37L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input NOTE : Port 3.7 also controlled by EA and Memory Access Control HCR1.1. P3.6 Port 3 Bit 6 Control. bits 5−4 P36H P36L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input NOTE : Port 3.6 also controlled by EA and Memory Access Control HCR1.1. P3.5 Port 3 Bit 5 Control. bits 3−2 P35H P35L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P3.4 Port 3 Bit 4 Control. bits 1−0 P34H P34L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Interrupt Priority (IP) 7 6 5 4 3 2 1 0 Reset Value SFR B8h 1 PS1 PT2 PS0 PT1 PX1 PT0 PX0 80h PS1 Serial Port 1 Interrupt. This bit controls the priority of the serial Port 1 interrupt. bit 6 0 = Serial Port 1 priority is determined by the natural priority order. 1 = Serial Port 1 is a high priority interrupt. PT2 Timer 2 Interrupt. This bit controls the priority of the Timer 2 interrupt. bit 5 0 = Timer 2 priority is determined by the natural priority order. 1 = Timer 2 priority is a high priority interrupt. PS0 Serial Port 0 Interrupt. This bit controls the priority of the serial Port 0 interrupt. bit 4 0 = Serial Port 0 priority is determined by the natural priority order. 1 = Serial Port 0 is a high priority interrupt. PT1 Timer 1 Interrupt. This bit controls the priority of the Timer 1 interrupt. bit 3 0 = Timer 1 priority is determined by the natural priority order. 1 = Timer 1 priority is a high priority interrupt. PX1 External Interrupt 1. This bit controls the priority of external interrupt 1. bit 2 0 = External interrupt 1 priority is determined by the natural priority order. 1 = External interrupt 1 is a high priority interrupt. PT0 Timer 0 Interrupt. This bit controls the priority of the Timer 0 interrupt. bit 1 0 = Timer 0 priority is determined by the natural priority order. 1 = Timer 0 priority is a high priority interrupt. PX0 External Interrupt 0. This bit controls the priority of external interrupt 0. bit 0 0 = External interrupt 0 priority is determined by the natural priority order. 1 = External interrupt 0 is a high priority interrupt.

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Serial Port 1 Control (SCON1) 7 6 5 4 3 2 1 0 Reset Value SFR C0h SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 00h SM0−2 Serial Port 1 Mode. These bits control the mode of serial Port 1. Modes 1, 2, and 3 have 1 start and 1 stop bit bits 7−5 in addition to the 8 or 9 data bits. MODE SM0 SM1 SM2 FUNCTION LENGTH PERIOD 0 0 0 0 Synchronous 8 bits 12 pCLK (1) 0 0 0 1 Synchronous 8 bits 4 pCLK (1) 1 0 1 0 Asynchronous 10 bits Timer 1 Baud Rate Equation 1 0 1 1 Valid Stop Required(2) 10 bits Timer 1 or Baud Rate Equation 2 1 0 0 Asynchronous 11 bits 64 pCLK (1) (SMOD = 0) 32 pCLK (1) (SMOD = 1) 2 1 0 1 Asynchronous with Multiprocessor Communication(3) 11 bits 64 pCLK (1) (SMOD = 0) 32 pCLK (1) (SMOD = 1) 3 1 1 0 Asynchronous 11 bits Timer 1 Baud Rate Equation 3 1 1 1 Asynchronous with Multiprocessor Communication(3) 11 bits Timer 1 Baud Rate Equation (1)pCLK will be equal to tCLK , except that pCLK will stop for IDLE. (2)RI_0 will only be activated when a valid STOP is received. (3)RI_0 will not be activated if bit 9 = 0. REN_1 Receive Enable. This bit enables/disables the serial Port 1 received shift register. bit 4 0 = Serial Port 1 reception disabled. 1 = Serial Port 1 received enabled (modes 1, 2, and 3). Initiate synchronous reception (mode 0). TB8_1 9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial Port 1 modes 2 and 3. bit 3 RB8_1 9th Received Bit State. This bit identifies the state of the 9th reception bit of received data in serial Port 1 modes bit 2 2 and 3. In serial port mode 1, when SM2_1 = 0, RB8_1 is the state of the stop bit. RB8_1 is not used in mode 0. TI_1 Transmitter Interrupt Flag. This bit indicates that data in the serial Port 1 buffer has been completely shifted out. bit 1 In serial port mode 0, TI_1 is set at the end of the 8th data bit. In all other modes, this bit is set at the end of the last data bit. This bit must be cleared by software to transmit the next byte. RI_1 Receiver Interrupt Flag. This bit indicates that a byte of data has been received in the serial Port 1 buffer. In serial bit 0 port mode 0, RI_1 is set at the end of the 8th bit. In serial port mode 1, RI_1 is set after the last sample of the incoming stop bit subject to the state of SM2_1. In modes 2 and 3, RI_1 is set after the last sample of RB8_1. This bit must be cleared by software to receive the next byte.

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Serial Data Buffer 1 (SBUF1) 7 6 5 4 3 2 1 0 Reset Value SFR C1h 00h SBUF1.7−0 Serial Data Buffer 1. Data for serial Port 1 is read from or written to this location. The serial transmit and receive bits 7−0 buffers are separate registers, but both are addressed at this location. Enable Wake Up (EWU) Waking Up from IDLE Mode 7 6 5 4 3 2 1 0 Reset Value SFR C6h — — — — — EWUWDT EWUEX1 EWUEX0 00h Auxiliary interrupts will wake up from IDLE. They are enabled with EAI (EICON.5, SFR D8h). EWUWDT Enable Wake Up Watchdog Timer. Wake using watchdog timer interrupt. bit 2 0 = Don’t wake up on watchdog timer interrupt. 1 = Wake up on watchdog timer interrupt. EWUEX1 Enable Wake Up External 1. Wake using external interrupt source 1. bit 1 0 = Don’t wake up on external interrupt source 1. 1 = Wake up on external interrupt source 1. EWUEX0 Enable Wake Up External 0. Wake using external interrupt source 0. bit 0 0 = Don’t wake up on external interrupt source 0. 1 = Wake up on external interrupt source 0.

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Timer 2 Control (T2CON) 7 6 5 4 3 2 1 0 Reset Value SFR C8h TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 00h TF2 Timer 2 Overflow Flag. This flag will be set when Timer 2 overflows from FFFFh. It must be cleared by software. bit 7 TF2 will only be set if RCLK and TCLK are both cleared to 0. Writing a 1 to TF2 forces a Timer 2 interrupt if enabled. EXF2 Timer 2 External Flag. A negative transition on the T2EX pin (P1.1) will cause this flag to be set based on the EXEN2 bit 6 (T2CON.3) bit. If set by a negative transition, this flag must be cleared to 0 by software. Setting this bit in software will force a timer interrupt if enabled. RCLK Receive Clock Flag. This bit determines the serial Port 0 timebase when receiving data in serial modes 1 or 3. bit 5 0 = Timer 1 overflow is used to determine receiver baud rate for USART0. 1 = Timer 2 overflow is used to determine receiver baud rate for USART0. Setting this bit will force Timer 2 into baud rate generation mode. The timer will operate from a divide by 2 of the external clock. TCLK Transmit Clock Flag. This bit determines the serial Port 0 timebase when transmitting data in serial modes 1 or 3. bit 4 0 = Timer 1 overflow is used to determine transmitter baud rate for USART0. 1 = Timer 2 overflow is used to determine transmitter baud rate for USART0. Setting this bit will force Timer 2 into baud rate generation mode. The timer will operate from a divide by 2 of the external clock. EXEN2 Timer 2 External Enable. This bit enables the capture/reload function on the T2EX pin if Timer 2 is not generating bit 3 baud rates for the serial port. 0 = Timer 2 will ignore all external events at T2EX. 1 = Timer 2 will capture or reload a value if a negative transition is detected on the T2EX pin. TR2 Timer 2 Run Control. This bit enables/disables the operation of Timer 2. Halting this timer will preserve the current bit 2 count in TH2, TL2. 0 = Timer 2 is halted. 1 = Timer 2 is enabled. C/T2 Counter/Timer Select. This bit determines whether Timer 2 will function as a timer or counter. Independent of this bit 1 bit, Timer 2 runs at 2 clocks per tick when used in baud rate generator mode. 0 = Timer 2 functions as a timer. The speed of Timer 2 is determined by the T2M bit (CKCON.5). 1 = Timer 2 will count negative transitions on the T2 pin (P1.0). CP/RL2 Capture/Reload Select. This bit determines whether the capture or reload function is used for Timer 2. If either RCLK bit 0 or TCLK is set, this bit will not function and the timer will function in an auto-reload mode following each overflow. 0 = Auto-reloads will occur when Timer 2 overflows or a falling edge is detected on T2EX if EXEN2 = 1. 1 = Timer 2 captures will occur when a falling edge is detected on T2EX if EXEN2 = 1. Timer 2 Capture LSB (RCAP2L) 7 6 5 4 3 2 1 0 Reset Value SFR CAh 00h RCAP2L T imer 2 Capture LSB. This register is used to capture the TL2 value when Timer 2 is configured in capture mode. bits 7−0 RCAP2L is also used as the LSB of a 16-bit reload value when Timer 2 is configured in auto-reload mode.

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Timer 2 Capture MSB (RCAP2H) 7 6 5 4 3 2 1 0 Reset Value SFR CBh 00h RCAP2H T imer 2 Capture MSB. This register is used to capture the TH2 value when Timer 2 is configured in capture mode. bits 7−0 RCAP2H is also used as the MSB of a 16-bit reload value when Timer 2 is configured in auto-reload mode. Timer 2 LSB (TL2) 7 6 5 4 3 2 1 0 Reset Value SFR CCh 00h TL2 Timer 2 LSB. This register contains the least significant byte of Timer 2. bits 7−0 Timer 2 MSB (TH2) 7 6 5 4 3 2 1 0 Reset Value SFR CDh 00h TH2 Timer 2 MSB. This register contains the most significant byte of Timer 2. bits 7−0 Program Status Word (PSW) 7 6 5 4 3 2 1 0 Reset Value SFR D0h CY AC F0 RS1 RS0 OV F1 P 00h CY Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (during addition) or a borrow (during bit 7 subtraction). Otherwise, it is cleared to 0 by all arithmetic operations. AC Auxiliary Carry Flag. This bit is set to 1 if the last arithmetic operation resulted in a carry into (during addition), or bit 6 a borrow (during subtraction) from the high-order nibble. Otherwise, it is cleared to 0 by all arithmetic operations. F0 User Flag 0. This is a bit-addressable, general-purpose flag for software control. bit 5 RS1, RS0 Register Bank Select 1−0. These bits select which register bank is addressed during register accesses. bits 4−3 RS1 RS0 REGISTER BANK ADDRESS 0 0 0 00h − 07h 0 1 1 08h − 0Fh 1 0 2 10h − 17h 1 1 3 18h − 1Fh OV Overflow Flag. This bit is set to 1 if the last arithmetic operation resulted in a carry (addition), borrow (subtraction), bit 2 or overflow (multiply or divide). Otherwise it is cleared to 0 by all arithmetic operations. F1 User Flag 1. This is a bit-addressable, general-purpose flag for software control. bit 1 P Parity Flag. This bit is set to 1 if the modulo-2 sum of the 8 bits of the accumulator is 1 (odd parity); and cleared to bit 0 0 on even parity.

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com ADC Offset Calibration Register Low Byte (OCL) 7 6 5 4 3 2 1 0 Reset Value SFR D1h LSB 00h OCL ADC Offset Calibration Register Low Byte. This is the low byte of the 24-bit word that contains the ADC offset bits 7−0 calibration. A value that is written to this location will set the ADC offset calibration value. ADC Offset Calibration Register Middle Byte (OCM) 7 6 5 4 3 2 1 0 Reset Value SFR D2h 00h OCM ADC Offset Calibration Register Middle Byte. This is the middle byte of the 24-bit word that contains the ADC offset bits 7−0 calibration. A value that is written to this location will set the ADC offset calibration value. ADC Offset Calibration Register High Byte (OCH) 7 6 5 4 3 2 1 0 Reset Value SFR D3h MSB 00h OCH ADC Offset Calibration Register High Byte. This is the high byte of the 24-bit word that contains the ADC offset bits 7−0 calibration. A value that is written to this location will set the ADC offset calibration value. ADC Gain Calibration Register Low Byte (GCL) 7 6 5 4 3 2 1 0 Reset Value SFR D4h LSB 5Ah GCL ADC Gain Calibration Register Low Byte. This is the low byte of the 24-bit word that contains the ADC gain bits 7−0 calibration. A value that is written to this location will set the ADC gain calibration value. ADC Gain Calibration Register Middle Byte (GCM) 7 6 5 4 3 2 1 0 Reset Value SFR D5h ECh GCM ADC Gain Calibration Register Middle Byte. This is the middle byte of the 24-bit word that contains the ADC gain bits 7−0 calibration. A value that is written to this location will set the ADC gain calibration value. ADC Gain Calibration Register High Byte (GCH) 7 6 5 4 3 2 1 0 Reset Value SFR D6h MSB 5Fh GCH ADC Gain Calibration Register High Byte. This is the high byte of the 24-bit word that contains the ADC gain bits 7−0 calibration. A value that is written to this location will set the ADC gain calibration value.

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com ADC Multiplexer Register (ADMUX) 7 6 5 4 3 2 1 0 Reset Value SFR D7h INP3 INP2 INP1 INP0 INN3 INN2 INN1 INN0 01h INP3−0 Input Multiplexer Positive Channel. This selects the positive signal input. bits 7−4 INP3 INP2 INP1 INP0 POSITIVE INPUT 0 0 0 0 AIN0 (default) 0 0 0 1 AIN1 0 0 1 0 AIN2 0 0 1 1 AIN3 0 1 0 0 AIN4 0 1 0 1 AIN5 0 1 1 0 AIN6 0 1 1 1 AIN7 1 0 0 0 AINCOM 1 1 1 1 Temperature Sensor (requires ADMUX = FFh) INN3−0 Input Multiplexer Negative Channel. This selects the negative signal input. bits 3−0 INN3 INN2 INN1 INN0 NEGATIVE INPUT 0 0 0 0 AIN0 0 0 0 1 AIN1 (default) 0 0 1 0 AIN2 0 0 1 1 AIN3 0 1 0 0 AIN4 0 1 0 1 AIN5 0 1 1 0 AIN6 0 1 1 1 AIN7 1 0 0 0 AINCOM 1 1 1 1 Temperature Sensor (requires ADMUX = FFh)

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Enable Interrupt Control (EICON) 7 6 5 4 3 2 1 0 Reset Value SFR D8h SMOD1 1 EAI AI WDTI 0 0 0 40h SMOD1 Serial Port 1 Mode. When this bit is set the serial baud rate for Port 1 will be doubled. bit 7 0 = Standard baud rate for Port 1 (default). 1 = Double baud rate for Port 1. EAI Enable Auxiliary Interrupt. The Auxiliary Interrupt accesses nine different interrupts which are masked and bit 5 identified by SFR registers PAI (SFR A5h), AIE (SFR A6h), and AISTAT (SFR A7h). 0 = Auxiliary Interrupt disabled (default). 1 = Auxiliary Interrupt enabled. AI Auxiliary Interrupt Flag. AI must be cleared by software before exiting the interrupt service routine, after the source bit 4 of the interrupt is cleared. Otherwise, the interrupt occurs again. Setting AI in software generates an Auxiliary Interrupt, if enabled. 0 = No Auxiliary Interrupt detected (default). 1 = Auxiliary Interrupt detected. WDTI Watchdog T imer Interrupt Flag. WDTI must be cleared by software before exiting the interrupt service routine. bit 3 Otherwise, the interrupt will occur again. Setting WDTI in software generates a watchdog time interrupt, if enabled. The Watchdog timer can generate an interrupt or reset. The interrupt is available only if the reset action is disabled in HCR0. 0 = No Watchdog Timer Interrupt detected (default). 1 = Watchdog Timer Interrupt detected. ADC Results Register Low Byte (ADRESL) 7 6 5 4 3 2 1 0 Reset Value SFR D9h LSB 00h ADRESL The ADC Results Low Byte. This is the low byte of the 24-bit word that contains the ADC converter results. bits 7−0 Reading from this register clears the ADC interrupt. However, AI in EICON (SFR D8h) must also be cleared. ADC Results Register Middle Byte (ADRESM) 7 6 5 4 3 2 1 0 Reset Value SFR DAh 00h ADRESM The ADC Results Middle Byte. This is the middle byte of the 24-bit word that contains the ADC converter results. bits 7−0 ADC Results Register High Byte (ADRESH) 7 6 5 4 3 2 1 0 Reset Value SFR DBh MSB 00h ADRESH The ADC Results High Byte. This is the high byte of the 24-bit word that contains the ADC converter results. bits 7−0

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com ADC Control Register 0 (ADCON0) 7 6 5 4 3 2 1 0 Reset Value SFR DCh BOD EVREF VREFH EBUF PGA2 PGA1 PGA0 30h BOD Burnout Detect. When enabled this connects a positive current source to the positive channel and a negative bit 6 current source to the negative channel. If the channel is open circuit then the ADC results will be full-scale. 0 = Burnout Current Sources Off (default). 1 = Burnout Current Sources On. EVREF Enable Internal Voltage Reference. If the internal voltage reference is not used, it should be turned off to save power bit 5 and reduce noise. 0 = Internal Voltage Reference Off. 1 = Internal Voltage Reference On (default). NOTE: REFIN− must be connected to AGND, and REFOUT to REFIN+. VREFH Voltage Reference High Select. The internal voltage reference can be selected to be 2.5V or 1.25V. bit 4 0 = REFOUT is 1.25V. 1 = REFOUT is 2.5V (default). EBUF Enable Buffer. Enable the input buffer to provide higher input impedance but limits the input voltage range and bit 3 dissipates more power. 0 = Buffer disabled (default). 1 = Buffer enabled. PGA2−0 Programmable Gain Amplifier. Sets the gain for the PGA from 1 to 128. bits 2−0 PGA2 PGA1 PGA0 GAIN 0 0 0 1 (default) 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com ADC Control Register 1 (ADCON1) 7 6 5 4 3 2 1 0 Reset Value SFR DDh — POL SM1 SM0 — CAL2 CAL1 CAL0 0000 0000b POL Polarity. Polarity of the ADC result and Summation register. bit 6 0 = Bipolar. 1 = Unipolar. The LSB size is 1/2 the size of bipolar (twice the resolution). POL ANALOG INPUT DIGITAL OUTPUT +FSR 7FFFFFh

0 ZERO 000000h0

−FSR 800000h +FSR FFFFFFh

1 ZERO 000000h1

−FSR 000000h SM1−0 Settling Mode. Selects the type of filter or auto select which defines the digital filter settling characteristics. bits 5−4 SM1 SM0 SETTLING MODE 0 0 Auto 0 1 Fast Settling Filter 1 0 Sinc2 Filter 1 1 Sinc3 Filter CAL2−0 Calibration Mode Control Bits. bits 2−0 Writing to these bits starts ADC calibration. CAL2 CAL1 CAL0 CALIBRATION MODE 0 0 0 No Calibration (default) 0 0 1 Self-Calibration, Offset and Gain 0 1 0 Self-Calibration, Offset only 0 1 1 Self-Calibration, Gain only 1 0 0 System Calibration, Offset only (requires external connection) 1 0 1 System Calibration, Gain only (requires external connection) 1 1 0 Reserved 1 1 1 Reserved NOTE : Read Value—000b. ADC Control Register 2 (ADCON2) 7 6 5 4 3 2 1 0 Reset Value SFR DEh DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 1Bh DR7−0 Decimation Ratio LSB. bits 7−0 ADC Control Register 3 (ADCON3) 7 6 5 4 3 2 1 0 Reset Value SFR DFh — — — — — DR10 DR9 DR8 06h DR10−8 Decimation Ratio Most Significant 3 Bits. The output data rate = fCLK /[(ACLK + 1) /C0083 64 /C0083 Decimation Ratio]. bits 2−0

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Accumulator (A or ACC) 7 6 5 4 3 2 1 0 Reset Value ACC.7−0 Accumulator. This register serves as the accumulator for arithmetic and logic operations. bits 7−0 Summation/Shifter Control (SSCON) 7 6 5 4 3 2 1 0 Reset Value SFR E1h SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 00h The Summation register is powered down when the ADC is powered down. If all zeroes are written to this register the 32-bit SUMR3−0 registers will be cleared. The Summation registers will do sign extend if Bipolar is selected in ADCON1. SSCON1−0 Summation/Shift Count. bits 7−6 SOURCE SSCON1 SSCON0 MODE CPU 0 0 Values written to the SUM registers are accumulated when the SUMR0 value is written (sum/shift ignored) ADC 0 1 Summation register Enabled. Source is ADC, summation count is working. CPU 1 0 Shift Enabled. Summation register is shifted by SHF Count bits. It takes four system clocks to execute. ADC 1 1 Accumulate and Shift Enable. Values are accumulated for SUM Count times and then shifted by SHF Count. SCNT2−0 Summation Count. When the summation is complete an interrupt will be generated unless masked. Reading the bits 5−3 SUMR0 register clears the interrupt. SCNT2 SCNT1 SCNT0 SUMMATION COUNT 0 0 0 2 0 0 1 4 0 1 0 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 256 SHF2−0 Shift Count. bits 2−0 SHF2 SHF1 SHF0 SHIFT DIVIDE 0 0 0 1 2 0 0 1 2 4 0 1 0 3 8 0 1 1 4 16 1 0 0 5 32 1 0 1 6 64 1 1 0 7 128 1 1 1 8 256

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Summation Register 0 (SUMR0) 7 6 5 4 3 2 1 0 Reset Value SFR E2h LSB 00h SUMR0 Summation Register 0. This is the least significant byte of the 32-bit summation register or bits 0 to 7. bits 7−0 Write: Will cause values in SUMR3−0 to be added to the summation register. Read: Will clear the Summation Count Interrupt. AI in EICON (SFR D8h) must also be cleared. Summation Register 1 (SUMR1) 7 6 5 4 3 2 1 0 Reset Value SFR E3h 00h SUMR1 Summation Register 1. These are bits 8−15 of the 32-bit summation register. bits 7−0 Summation Register 2 (SUMR2) 7 6 5 4 3 2 1 0 Reset Value SFR E4h 00h SUMR2 Summation Register 2. These are bits 16−23 of the 32-bit summation register. bits 7−0 Summation Register 3 (SUMR3) 7 6 5 4 3 2 1 0 Reset Value SFR E5h MSB 00h SUMR3 Summation Register 3. This is the most significant byte of the 32-bit summation register or bits 24−31. bits 7−0 Offset DAC Register (ODAC) 7 6 5 4 3 2 1 0 Reset Value SFR E6h 00h ODAC Offset DAC Register. This register will shift the input by up to half of the ADC full-scale input range. The offset DAC bits 7−0 value is summed with the ADC input prior to conversion. Writing 00h or 80h to ODAC turns off the offset DAC. bit 7 Offset DAC Sign bit. 0 = Positive 1 = Negative bit 6−0 Offset/C0043/C0042V REF 2 /C0064PGA /C0064/C0466ODAC /C04266:0 /C0427 127 /C0467/C0064(/C00421) bit7 NOTE: ODAC cannot be used to offset the input so that the buffer can be used for AGND signals. Offset DAC should be cleared before offset calibration, since the offset DAC output is applied directly to the ADC input.

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Low Voltage Detect Control (LVDCON) 7 6 5 4 3 2 1 0 Reset Value SFR E7h ALVDIS ALVD2 ALVD1 ALVD0 DLVDIS DLVD2 DLVD1 DLVD0 00h NOTE: By default, both analog and digital low-voltage detections are enabled, which causes approximately 25µA of current consumption from the power supply. To minimize this power consumption, both low-voltage detections should be disabled before entering Stop mode. ALVDIS Analog Low Voltage Detect Disable. bit 7 0 = Enable Detection of Low Analog Supply Voltage 1 = Disable Detection of Low Analog Supply Voltage ALVD2−0 Analog Voltage Detection Level. bits 6−4 ALVD2 ALVD1 ALVD0 VOLTAGE LEVEL 0 0 0 AVDD 2.7V (default) 0 0 1 AVDD 3.0V 0 1 0 AVDD 3.3V 0 1 1 AVDD 4.0V 1 0 0 AVDD 4.2V 1 0 1 AVDD 4.5V 1 1 0 AVDD 4.7V 1 1 1 External Voltage AIN7 compared to 1.2V DLVDIS Digital Low Voltage Detect Disable. bit 3 0 = Enable Detection of Low Digital Supply Voltage 1 = Disable Detection of Low Digital Supply Voltage DLVD2−0 Digital Voltage Detection Level. bits 2−0 DLVD2 DLVD1 DLVD0 VOLTAGE LEVEL 0 0 0 DV DD 2.7V (default) 0 0 1 DV DD 3.0V 0 1 0 DV DD 3.3V 0 1 1 DV DD 4.0V 1 0 0 DV DD 4.2V 1 0 1 DV DD 4.5V 1 1 0 DV DD 4.7V 1 1 1 External Voltage AIN6 compared to 1.2V

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Extended Interrupt Enable (EIE) 7 6 5 4 3 2 1 0 Reset Value SFR E8h 1 1 1 EWDI EX5 EX4 EX3 EX2 E0h EWDI Enable Watchdog Interrupt. This bit enables/disables the watchdog interrupt. The Watchdog timer is enabled by bit 4 (SFR FFh) and PDCON (SFR F1h) registers. 0 = Disable the Watchdog Interrupt 1 = Enable Interrupt Request Generated by the Watchdog Timer EX5 External Interrupt 5 Enable. This bit enables/disables external interrupt 5. bit 3 0 = Disable External Interrupt 5 1 = Enable External Interrupt 5 EX4 External Interrupt 4 Enable. This bit enables/disables external interrupt 4. bit 2 0 = Disable External Interrupt 4 1 = Enable External Interrupt 4 EX3 External Interrupt 3 Enable. This bit enables/disables external interrupt 3. bit 1 0 = Disable External Interrupt 3 1 = Enable External Interrupt 3 EX2 External Interrupt 2 Enable. This bit enables/disables external interrupt 2. bit 0 0 = Disable External Interrupt 2 1 = Enable External Interrupt 2 Hardware Product Code Register 0 (HWPC0) (read-only) 7 6 5 4 3 2 1 0 Reset Value SFR E9h 0 0 0 0 0 0 MEMORY SIZE 0000_00xxb HWPC1.7−0 Hardware Product Code LSB. Read-only. bits 7−0 MEMORY SIZE MODEL FLASH MEMORY 0 0 MSC1210Y2 4kB 0 1 MSC1210Y3 8kB 1 0 MSC1210Y4 16kB 1 1 MSC1210Y5 32kB Hardware Product Code Register 1 (HWPC1) (read-only) 7 6 5 4 3 2 1 0 Reset Value SFR EAh 0 0 0 0 0 0 0 0 00h HWPC1.7−0 Hardware Product Code MSB. Read-only. bits 7−0

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Hardware Version Register (HDWVER) 7 6 5 4 3 2 1 0 Reset Value SFR EBh Flash Memory Control (FMCON) 7 6 5 4 3 2 1 0 Reset Value SFR EEh 0 PGERA 0 FRCM 0 BUSY 1 0 02h PGERA Page Erase. bit 6 0 = MOVX to Flash will perform a byte write operation 1 = MOVX to Flash will perform a page erase operation FRCM Frequency Control Mode. bit 4 0 = Bypass (default) 1 = Use Delay Line. Saves power when reading Flash (recommended) BUSY Write/Erase BUSY Signal. bit 2 0 = Idle or Available 1 = Busy Flash Memory Timing Control Register (FTCON) 7 6 5 4 3 2 1 0 Reset Value SFR EFh FER3 FER2 FER1 FER0 FWR3 FWR2 FWR1 FWR0 A5h Refer to Flash Timing Characteristics. FER3−0 Set Erase. Flash Erase Time = (1 + FER) • (MSEC + 1) • tCLK . bits 7−4 A minimum of 10ms is needed for industrial temperature range. A minimum of 4ms is needed for commercial temperature range. FWR3−0 Set Write. Flash Write Time = (1 + FWR) • (USEC + 1) • 5 • tCLK . bits 3−0 Write time should be 30−40µs. B Register (B) 7 6 5 4 3 2 1 0 Reset Value B.7−0 B Register. This register serves as a second accumulator for certain arithmetic operations. bits 7−0

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Power-Down Control Register (PDCON) 7 6 5 4 3 2 1 0 Reset Value SFR F1h 0 0 0 PDPWM PDADC PDWDT PDST PDSPI 1Fh Turning peripheral modules off puts the MSC1210 in the lowest power mode. PDPWM Pulse Width Module Control. bit 4 0 = PWM On 1 = PWM Power Down PDADC ADC Control. bit 3 0 = ADC On 1 = ADC, VREF , and summation registers are powered down. PDWDT Watchdog Timer Control. bit 2 0 = W atchdog Timer On 1 = Watchdog Timer Power Down PDST System Timer Control. bit 1 0 = System Timer On 1 = System Timer Power Down PDSPI SPI System Control. bit 0 0 = SPI System On 1 = SPI System Power Down PSEN /ALE Select (PASEL) 7 6 5 4 3 2 1 0 Reset Value SFR F2h 0 0 PSEN2 PSEN1 PSEN0 0 ALE1 ALE0 00h PSEN2−0 PSEN Mode Select. bits 5−3 PSEN2 PSEN1 PSEN0 0 0 x PSEN 0 1 x CLK 1 0 x ADC MODCLK 1 1 0 LOW 1 1 1 HIGH ALE1−0 ALE Mode Select. bits 1−0 ALE1 ALE0 0 x ALE 1 0 LOW 1 1 HIGH NOTE: For power-saving purposes, it is recommended that the PSEN and ALE pins be set to low or high mode when external memory is not used.

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Analog Clock (ACLK) 7 6 5 4 3 2 1 0 Reset Value SFR F6h 0 FREQ6 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03h FREQ6−0 Clock Frequency − 1. This value + 1 divides the system clock to create the ADC clock. bit 6−0 fACLK /C0043fCLK FREQ /C00411 /C0043fCLK ACLK /C00411 fMOD /C0043 fCLK (ACLK /C00411)/C006464 Output Data Rate/C0043fMOD Decimation System Reset Register (SRST) 7 6 5 4 3 2 1 0 Reset Value SFR F7h 0 0 0 0 0 0 0 RSTREQ 00h RSTREQ Reset Request. Setting this bit to 1 and then clearing to 0 will generate a system reset. bit 0 Extended Interrupt Priority (EIP) 7 6 5 4 3 2 1 0 Reset Value SFR F8h 1 1 1 PWDI PX5 PX4 PX3 PX2 E0h PWDI Watchdog Interrupt Priority. This bit controls the priority of the watchdog interrupt. bit 4 0 = The watchdog interrupt is low priority. 1 = The watchdog interrupt is high priority. PX5 External Interrupt 5 Priority. This bit controls the priority of external interrupt 5. bit 3 0 = External interrupt 5 is low priority. 1 = External interrupt 5 is high priority. PX4 External Interrupt 4 Priority. This bit controls the priority of external interrupt 4. bit 2 0 = External interrupt 4 is low priority. 1 = External interrupt 4 is high priority. PX3 External Interrupt 3 Priority. This bit controls the priority of external interrupt 3. bit 1 0 = External interrupt 3 is low priority. 1 = External interrupt 3 is high priority. PX2 External Interrupt 2 Priority. This bit controls the priority of external interrupt 2. bit 0 0 = External interrupt 2 is low priority. 1 = External interrupt 2 is high priority.

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com Seconds Timer Interrupt (SECINT) 7 6 5 4 3 2 1 0 Reset Value SFR F9h WRT SECINT6 SECINT5 SECINT4 SECINT3 SECINT2 SECINT1 SECINT0 7Fh This system clock is divided by the value of the 16-bit register MSECH:MSECL. Then, the 1ms timer tick is divided by the register HMSEC that provides the 100ms signal used by this seconds timer. Therefore, the seconds timer can generate an interrupt that occurs from 100ms to 12.8 seconds. Reading this register clears the Seconds Interrupt. This Interrupt can be monitored in the AIE register. WRT Write Control. Determines whether to write the value immediately or wait until the current count is finished. bit 7 Read = 0. 0 = Delay Write Operation. The SEC value is loaded when the current count expires. 1 = Write Immediately. The counter is loaded once the CPU completes the write operation. SECINT6−0 Seconds Count. Normal operation uses 100ms as the clock interval, and would equal: (SEC + 1)/10 seconds. bits 6−0 Seconds Interrupt = (1 + SEC) • (HMSEC + 1) • (MSEC + 1) • t CLK Milliseconds Interrupt (MSINT) 7 6 5 4 3 2 1 0 Reset Value SFR FAh WRT MSINT6 MSINT5 MSINT4 MSINT3 MSINT2 MSINT1 MSINT0 7Fh The clock used for this timer is the 1ms clock, which results from dividing the system clock by the values in registers MSECH:MSECL. Reading this register clears the milliseconds interrupt. AI in EICON (SFR D8h) must also be cleared. WRT Write Control. Determines whether to write the value immediately or wait until the current count is finished. bit 7 Read = 0. 0 = Delay Write Operation. The MSINT value is loaded when the current count expires. 1 = Write Immediately. The MSINT counter is loaded once the CPU completes the write operation. MSINT6−0 Seconds Count. Normal operation would use 1ms as the clock interval. bits 6−0 MS Interrupt Interval = (1 + MSINT) • (MSEC + 1) • t CLK One Microsecond Register (USEC) 7 6 5 4 3 2 1 0 Reset Value SFR FBh 0 0 0 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03h FREQ4−0 Clock Frequency − 1. This value + 1 divides the system clock to create a 1µs clock. bits 4−0 USEC = CLK/(FREQ + 1). This clock is used to set Flash write time. See FTCON (SFR EFh). One Millisecond Low Register (MSECL) 7 6 5 4 3 2 1 0 Reset Value SFR FCh MSECL7 MSECL6 MSECL5 MSECL4 MSECL3 MSECL2 MSECL1 MSECL0 9Fh MSECL7−0 One Millisecond Low. This value in combination with the next register is used to create a 1ms clock. bits 7−0 1ms = (MSECH • 256 + MSECL + 1) • tCLK . This clock is used to set Flash erase time. See FTCON (SFR EFh).

/C0077/C0083/C0067/C0049/C0050/C0049/C0048 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com One Millisecond High Register (MSECH) 7 6 5 4 3 2 1 0 Reset Value SFR FDh MSECH7 MSECH6 MSECH5 MSECH4 MSECH3 MSECH2 MSECH1 MSECH0 0Fh MSECH7−0 One Millisecond High. This value in combination with the previous register is used to create a 1ms clock. bits 7−0 1ms = (MSECH • 256 + MSECL + 1) • tCLK One Hundred Millisecond Register (HMSEC) 7 6 5 4 3 2 1 0 Reset Value SFR FEh HMSEC7 HMSEC6 HMSEC5 HMSEC4 HMSEC3 HMSEC2 HMSEC1 HMSEC0 63h HMSEC7−0 One Hundred Millisecond. This clock divides the 1ms clock to create a 100ms clock. bits 7−0 100ms = (MSECH • 256 + MSECL + 1) • (HMSEC + 1) • tCLK Watchdog Timer Register (WDTCON) 7 6 5 4 3 2 1 0 Reset Value SFR FFh EWDT DWDT RWDT WDCNT4 WDCNT3 WDCNT2 WDCNT1 WDCNT0 00h EWDT Enable Watchdog (R/W). bit 7 Write 1/Write 0 sequence sets the Watchdog Enable Counting bit. DWDT Disable Watchdog (R/W). bit 6 Write 1/Write 0 sequence clears the Watchdog Enable Counting bit. RWDT Reset Watchdog (R/W). bit 5 Write 1/Write 0 sequence restarts the Watchdog Counter. WDCNT4−0 Watchdog Count (R/W). bits 4−0 Watchdog expires in (WDCNT + 1) • HMSEC to (WDCNT + 2) • HMSEC, if the sequence is not asserted. There is an uncertainty of 1 count.

SBAS203J − MARCH 2002 − REVISED JANUARY 2008 www.ti.com

Revision History

DATE REV PAGE SECTION DESCRIPTION 1/08 J 70 Serial Port Mode 1 Deleted note (2) from SM0−2 table. 10/07 I 26 Voltage Reference Added paragraph to end of section. NOTE : Page numbers for previous revisions may differ from page numbers in the current version.

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) MSC1210Y2PAGR Active Production TQFP (PAG) | 64 1500 | LARGE T&R Yes NIPDAU Level-4-260C-72 HR - MSC1210Y2 MSC1210Y2PAGR.B Active Production TQFP (PAG) | 64 1500 | LARGE T&R Yes NIPDAU Level-4-260C-72 HRSee MSC1210Y2PAGR MSC1210Y2 MSC1210Y2PAGT Active Production TQFP (PAG) | 64 250 | SMALL T&R Yes NIPDAU Level-4-260C-72 HR - MSC1210Y2 MSC1210Y2PAGT.B Active Production TQFP (PAG) | 64 250 | SMALL T&R Yes NIPDAU Level-4-260C-72 HRSee MSC1210Y2PAGT MSC1210Y2 MSC1210Y3PAGR Active Production TQFP (PAG) | 64 1500 | LARGE T&R Yes NIPDAU Level-4-260C-72 HR - MSC1210Y3 MSC1210Y3PAGR.B Active Production TQFP (PAG) | 64 1500 | LARGE T&R Yes NIPDAU Level-4-260C-72 HRSee MSC1210Y3PAGR MSC1210Y3 MSC1210Y3PAGT Active Production TQFP (PAG) | 64 250 | SMALL T&R Yes NIPDAU Level-4-260C-72 HR - MSC1210Y3 MSC1210Y3PAGT.B Active Production TQFP (PAG) | 64 250 | SMALL T&R Yes NIPDAU Level-4-260C-72 HRSee MSC1210Y3PAGT MSC1210Y3 MSC1210Y4PAGR Active Production TQFP (PAG) | 64 1500 | LARGE T&R Yes NIPDAU Level-4-260C-72 HR - MSC1210Y4 MSC1210Y4PAGR.B Active Production TQFP (PAG) | 64 1500 | LARGE T&R Yes NIPDAU Level-4-260C-72 HRSee MSC1210Y4PAGR MSC1210Y4 MSC1210Y4PAGT Active Production TQFP (PAG) | 64 250 | SMALL T&R Yes NIPDAU Level-4-260C-72 HR - MSC1210Y4 MSC1210Y4PAGT.B Active Production TQFP (PAG) | 64 250 | SMALL T&R Yes NIPDAU Level-4-260C-72 HRSee MSC1210Y4PAGT MSC1210Y4 MSC1210Y5PAGR Active Production TQFP (PAG) | 64 1500 | LARGE T&R Yes NIPDAU Level-4-260C-72 HR - MSC1210Y5 MSC1210Y5PAGR.B Active Production TQFP (PAG) | 64 1500 | LARGE T&R Yes NIPDAU Level-4-260C-72 HRSee MSC1210Y5PAGR MSC1210Y5 MSC1210Y5PAGT Active Production TQFP (PAG) | 64 250 | SMALL T&R Yes NIPDAU Level-4-260C-72 HR - MSC1210Y5 MSC1210Y5PAGT.B Active Production TQFP (PAG) | 64 250 | SMALL T&R Yes NIPDAU Level-4-260C-72 HRSee MSC1210Y5PAGT MSC1210Y5 MSC1210Y5PAGTG4.B Active Production TQFP (PAG) | 64 250 | SMALL T&R Yes NIPDAU Level-4-260C-72 HR See MSC1210Y5PAGTG4 MSC1210Y5 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1

www.ti.com 23-May-2025 (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 27-Dec-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 27-Dec-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSC1210Y2PAGR TQFP PAG 64 1500 350.0 350.0 43.0 MSC1210Y2PAGT TQFP PAG 64 250 213.0 191.0 55.0 MSC1210Y3PAGR TQFP PAG 64 1500 350.0 350.0 43.0 MSC1210Y3PAGT TQFP PAG 64 250 213.0 191.0 55.0 MSC1210Y4PAGR TQFP PAG 64 1500 350.0 350.0 43.0 MSC1210Y4PAGT TQFP PAG 64 250 213.0 191.0 55.0 MSC1210Y5PAGR TQFP PAG 64 1500 350.0 350.0 43.0 MSC1210Y5PAGT TQFP PAG 64 250 213.0 191.0 55.0 Pack Materials-Page 2

MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,13 NOM 0,25 0,45 0,75 Seating Plane 0,05 MIN 4040282/C 11/96 Gage Plane 0,17 0,27 7,50 TYP SQ 9,80 1,05 0,95 11,80 12,20 1,20 MAX 10,20 SQ 0,08 0,50 M0,08 0°–7° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026

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