Microcontroller

MSC1202Y3RHHT

Burr-Brown (TI)

Precision, Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with 8051 Microcontroller and Flash Memory

Manufacturer: Burr-Brown (TI)

Document: 78 Pages / 684Kb

Request Quote Download Datasheet Read online HTML view

More from Burr-Brown (TI) Browse M parts

Online Datasheet

Read MSC1202Y3RHHT online.

MSC1202 BURR-BROWN | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 78

Technical content

FEATURES

/C0068MSC1201: − 24 Bits No Missing Codes − 22 Bits Effective Resolution At 10Hz − Low Noise: 75nV /C0068MSC1202: − 16 Bits No Missing Codes − 16 Bits Effective Resolution At 200Hz − Noise: 600nV /C0068PGA From 1 to 128 /C0068Precision On-Chip Voltage Reference /C00686 Differential/Single-Ended Channels /C0068On-Chip Offset/Gain Calibration /C0068Offset Drift: 0.02ppm/°C /C0068Gain Drift: 0.5ppm/°C /C0068On-Chip Temperature Sensor /C0068Selectable Buffer Input /C0068Burnout Detect /C00688-Bit Current DAC DIGITAL FEATURES Microcontroller Core /C00688051-Compatible /C0068High-Speed Core: − 4 Clocks per Instruction Cycle /C0068DC to 33MHz /C0068On-Chip Oscillator /C0068PLL with 32kHz Capability /C0068Single Instruction 121ns /C0068Dual Data Pointer Memory /C00684kB or 8kB of Flash Memory /C0068Flash Memory Partitioning /C0068Endurance 1M Erase/Write Cycles, 100-Year Data Retention /C0068256 Bytes Data SRAM /C0068In-System Serially Programmable /C0068Flash Memory Security /C00681kB Boot ROM Peripheral Features /C006816 Digital I/O Pins /C0068Additional 32-Bit Accumulator /C0068Two 16-Bit Timer/Counters /C0068System Timers /C0068Programmable Watchdog Timer /C0068Full-Duplex USART /C0068Basic SPI /C0068Basic I2C  /C0068Power Management Control /C0068Internal Clock Divider /C0068Idle Mode Current < 200/C0109A /C0068Stop Mode Current < 100nA /C0068Digital Brownout Reset /C0068Analog Low-Voltage Detect /C006820 Interrupt Sources GENERAL FEATURES /C0068Each Device Has Unique Serial Number /C0068Package: QFN-36 /C0068Low Power: 3mW at 3.0V, 1MHz /C0068Industrial Temperature Range: −40°C to +125°C /C0068Power Supply: 2.7V to 5.25V

APPLICATIONS

/C0068Industrial Process Control /C0068Instrumentation /C0068Liquid/Gas Chromatography /C0068Blood Analysis /C0068Smart Transmitters /C0068Portable Instruments /C0068Weigh Scales /C0068Pressure Transducers /C0068Intelligent Sensors /C0068Portable Applications /C0068DAS Systems MSC1201 MSC1202 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Precision, Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with 8051 Microcontroller and Flash Memory www.ti.com Copyright  2004−2005, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola. I2C is a trademark of Philips Corporation. All other trademarks are the property of their respective owners. /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com PACKAGE/ORDERING INFORMATION (1) PRODUCT FLASH MEMORY (BYTES) ADC RESOUTION (BITS) PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING MSC1201Y2 4k 24 QFN-36 RHH −40°C to +125°C MSC1201Y2MSC1201Y2 4k 24 QFN-36 RHH −40°C to +125°C MSC1201Y2 MSC1201Y3 8k 24k QFN-36 RHH −40°C to +125°C MSC1201Y3MSC1201Y3 8k 24k QFN-36 RHH −40°C to +125°C MSC1201Y3 MSC1202Y2 4k 16 QFN-36 RHH −40°C to +125°C MSC1202Y2MSC1202Y2 4k 16 QFN-36 RHH −40°C to +125°C MSC1202Y2 MSC1202Y3 8k 16 QFN-36 RHH −40°C to +125°C MSC1202Y3MSC1202Y3 8k 16 QFN-36 RHH −40°C to +125°C MSC1202Y3 (1)For the most current package and ordering information, see the Package Option Addendum located at the end of this datasheet, or refer to our web site at www.ti.com. MSC1201Yx/MSC1202Yx FAMILY FEATURES FEATURES (1) MSC120xY2 (2) MSC120xY3 (2) Flash Program Memory (Bytes) Up to 4k Up to 8k Flash Data Memory (Bytes) Up to 2k Up to 4k Internal Scratchpad RAM (Bytes) 256 256 (1)All peripheral features are the same on all devices; the flash memory size is the only difference. (2)The last digit of the part number (N ) represents the onboard flash size = (2N)kBytes. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS (1) MSC1201Yx, MSC1202Yx UNITS Analog Inputs Input current Momentary 100 mA Input current Continuous 10 mA Input voltage AGND − 0.3 to AVDD + 0.3 V Power Supply DV DD to DGND −0.3 to +6 V AVDD to AGND −0.3 to +6 V AGND to DGND −0.3 to +0.3 V VREF to AGND −0.3 to AVDD + 0.3 V Digital input voltage to DGND −0.3 to DVDD + 0.3 V Digital output voltage to DGND −0.3 to DVDD + 0.3 V Maximum junction temperature +150 °C Operating temperature range −40 to +125 °C Storage temperature range −65 to +150 °C Lead temperature (soldering, 10s) +235 °C Package power dissipation (TJ Max − TAMBIENT )//C0113JA W Output current, all pins 200 mA Output pin short-circuit 10 s Junction to ambient (/C0113JA) High K (2s 2p) 21.9 °C/W Thermal Resistance Junction to ambient (/C0113JA) Low K (1s) 103.7 °C/WThermal Resistance Junction to case (/C0113JC) 21.9 °C/W Digital Outputs Output current Continuous 100 mA I/O source/sink current 100 mA Power pin maximum 300 mA (1)Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability.

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com ELECTRICAL CHARACTERISTICS: AV DD = 5V All specifications from TMIN to T MAX , DV DD = +2.7V to +5.25V , fMOD = 15.625kHz, PGA = 1, Buffer ON, f DATA = 10Hz, Bipolar, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V , unless otherwise noted. MSC1201Yx, MSC1202Yx PARAMETER CONDITION MIN TYP MAX UNITS Analog Input (AIN0-AIN5, AINCOM) Analog Input Range Buffer OFF AGND − 0.1 AVDD + 0.1 V Analog Input Range Buffer ON AGND + 50mV AVDD − 1.5 V Full-Scale Input Voltage Range (In+) − (In−) ±VREF /PGA V Differential Input Impedance Buffer OFF 7/PGA(1) M Ω Input Current Buffer ON 0.5 nA Fast Settling Filter−3dB 0.469 • fDATA Bandwidth Sinc2 Filter −3dB 0.318 • fDATABandwidth Sinc3 Filter −3dB 0.262 • fDATA Programmable Gain Amplifier User-Selectable Gain Range 1 128 Input Capacitance Buffer ON 7 pF Input Leakage Current Multiplexer Channel OFF, T = +25°C 0.5 pA Burnout Current Sources Buffer ON ±2 µA ADC Offset DAC Offset DAC Range ±VREF /(2 • PGA) V Offset DAC Resolution 8 Bits Offset DAC Full-Scale Gain Error ±1.0 % of Range Offset DAC Full-Scale Gain Error Drift 0.6 ppm/°C System Performance Resolution MSC1201 24 Bits Resolution MSC1202 16 Bits ENOB MSC1201 22 Bits ENOB MSC1202 16 Bits Output Noise See Typical Characteristics No Missing Codes MSC1201, Sinc3 Filter, Decimation > 360 24 Bits No Missing Codes MSC1202, Sinc3 Filter 16 Bits Integral Nonlinearity End Point Fit, Differential Input ±0.0004 ±0.0015 % of FSR Offset Error After Calibration 1.5 ppm of FS Offset Drift(2) Before Calibration 0.02 ppm of FS/°C Gain Error(3) After Calibration 0.005 % Gain Error Drift(2) Before Calibration 0.5 ppm/°C System Gain Calibration Range 80 120 % of FS System Offset Calibration Range −50 50 % of FS At DC 120 dB Common-Mode Rejection fCM = 60Hz, fDATA = 10Hz 130 dB Common-Mode Rejection fCM = 50Hz, fDATA = 50Hz 120 dB fCM = 60Hz, fDATA = 60Hz 120 dB Normal-Mode Rejection fCM = 50Hz, fDATA = 50Hz 100 dB Normal-Mode Rejection fCM = 60Hz, fDATA = 60Hz 100 dB Power-Supply Rejection At DC, dB = −20log(∆VOUT /∆VDD )(4) 100 dB (1)The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64). (2)Calibration can minimize these errors. (3)The gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF. (4)∆VOUT is change in digital result.

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com ELECTRICAL CHARACTERISTICS: AV DD = 5V (continued) All specifications from TMIN to T MAX , DV DD = +2.7V to +5.25V , fMOD = 15.625kHz, PGA = 1, Buffer ON, f DATA = 10Hz, Bipolar, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V , unless otherwise noted. MSC1201Yx, MSC1202Yx PARAMETER UNITSMAXTYPMINCONDITION Voltage Reference Input Reference Input Range REF IN+, REF IN− AGND AVDD (3) V ADC VREF VREF ≡ (REFIN+) − (REFIN−) 0.1 2.5 AVDD V VREF Common-Mode Rejection At DC 115 dB Input Current VREF = 2.5V, PGA = 1 1 µA On-Chip Voltage Reference Output Voltage VREFH = 1 at +25°C 2.5 V Output Voltage VREFH = 0 1.25 V Short-Circuit Current Source 8 mA Short-Circuit Current Sink 50 mA Short-Circuit Duration Sink or Source Indefinite Startup Time from Power ON C REFOUT = 0.1µF 8 ms Temperature Sensor Temperature Sensor Voltage T = +25°C 115 mV Temperature Sensor Coefficient 345 µV/°C IDAC Output Characteristics IDAC Resolution 8 Bits Full-Scale Output Current 1 mA Maximum Short-Circuit Current Duration Indefinite Compliance Voltage AVDD − 1.5 V Analog Power-Supply Requirements Analog Power-Supply Voltage AVDD 4.75 5.0 5.25 V Analog Current BOR OFF, External Clock Mode, Analog OFF, ALVD OFF, PDADC = PDIDAC = 1 < 1 nA PGA = 1, Buffer OFF 170 µA Analog ADC Current PGA = 128, Buffer OFF 430 µA Analog Power-Supply ADC Current (IADC ) PGA = 1, Buffer ON 230 µAPower-Supply Current ADC PGA = 128, Buffer ON 770 µACurrent VREF Supply Current (IVREF ) ADC ON 360 µA IDAC Supply Current (IIDAC ) IDAC = 00h 230 µA (1)The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64). (2)Calibration can minimize these errors. (3)The gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF. (4)∆VOUT is change in digital result.

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com ELECTRICAL CHARACTERISTICS: AV DD = 3V All specifications from TMIN to T MAX , DV DD = +2.7V to +5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, f DATA = 10Hz, Bipolar, and VREF ≡ (REF IN+) − (REF IN−) = +1.25V, unless otherwise noted. MSC1201Yx, MSC1202Yx PARAMETER CONDITIONS MIN TYP MAX UNITS Analog Input (AIN0-AIN5, AINCOM) Analog Input Range Buffer OFF AGND − 0.1 AVDD + 0.1 V Analog Input Range Buffer ON AGND + 50mV AVDD − 1.5 V Full-Scale Input Voltage Range (In+) − (In−) ±VREF /PGA V Differential Input Impedance Buffer OFF 7/PGA(1) M Ω Input Current Buffer ON 0.5 nA Fast Settling Filter−3dB 0.469 • fDATA Bandwidth Sinc2 Filter −3dB 0.318 • fDATABandwidth Sinc3 Filter −3dB 0.262 • fDATA Programmable Gain Amplifier User-Selectable Gain Range 1 128 Input Capacitance Buffer ON 7 pF Input Leakage Current Multiplexer Channel Off, T = +25°C 0.5 pA Burnout Current Sources Buffer ON ±2 µA ADC Offset DAC Offset DAC Range ±VREF /(2 • PGA) V Offset DAC Resolution 8 Bits Offset DAC Full-Scale Gain Error ±1.5 % of Range Offset DAC Full-Scale Gain Error Drift 0.6 ppm/°C System Performance Resolution MSC1201 24 Bits Resolution MSC1202 16 Bits ENOB MSC1201 22 Bits ENOB MSC1202 16 Bits Output Noise See Typical Characteristics No Missing Codes MSC1201, Sinc3 Filter, Decimation > 360 24 Bits No Missing Codes MSC1202, Sinc3 Filter 16 Bits Integral Nonlinearity End Point Fit, Differential Input ±0.0004 ±0.0015 % of FSR Offset Error After Calibration 1.3 ppm of FS Offset Drift(2) Before Calibration 0.02 ppm of FS/°C Gain Error(3) After Calibration 0.005 % Gain Error Drift(2) Before Calibration 0.5 ppm/°C System Gain Calibration Range 80 120 % of FS System Offset Calibration Range −50 50 % of FS At DC 130 dB Common-Mode Rejection fCM = 60Hz, fDATA = 10Hz 130 dB Common-Mode Rejection fCM = 50Hz, fDATA = 50Hz 120 dB fCM = 60Hz, fDATA = 60Hz 120 dB Normal-Mode Rejection fSIG = 50Hz, fDATA = 50Hz 100 dB Normal-Mode Rejection fSIG = 60Hz, fDATA = 60Hz 100 dB Power-Supply Rejection At DC, dB = −20log(∆VOUT /∆VDD )(4) 88 dB (1)The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64). (2)Calibration can minimize these errors. (3)The gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF. (4)∆VOUT is change in digital result.

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com ELECTRICAL CHARACTERISTICS: AV DD = 3V (continued) All specifications from TMIN to T MAX , DV DD = +2.7V to +5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, f DATA = 10Hz, Bipolar, and VREF ≡ (REF IN+) − (REF IN−) = +1.25V, unless otherwise noted. MSC1201Yx, MSC1202Yx PARAMETER UNITSMAXTYPMINCONDITIONS Voltage Reference Input Reference Input Range REF IN+, REF IN− AGND AVDD (3) V ADC V REF VREF ≡ (REFIN+) − (REFIN−) 0.1 1.25 AVDD V VREF Common-Mode Rejection At DC 110 dB Input Current VREF = 1.25V, PGA = 1 0.5 µA On-Chip Voltage Reference Output Voltage VREFH = 0 at +25°C 1.25 V Short-Circuit Current Source 8 mA Short-Circuit Current Sink 50 µA Short-Circuit Duration Sink or Source Indefinite Startup Time from Power ON C REFOUT 8 ms Temperature Sensor Temperature Sensor Voltage T = +25°C 115 mV Temperature Sensor Coefficient 345 µV/°C IDAC Output Characteristics IDAC Resolution 8 Bits Full-Scale Output Current 1 mA Maximum Short-Circuit Current Duration Indefinite Compliance Voltage AVDD − 1.5 V Analog Power-Supply Requirements Analog Power-Supply Voltage AVDD 2.7 3.6 V Analog Current BOR OFF, External Clock Mode, Analog OFF, ALVD OFF, PDADC = PDIDAC = 1 < 1 nA PGA = 1, Buffer OFF 150 µA Analog ADC Current PGA = 128, Buffer OFF 380 µA Analog Power-Supply ADC Current (IADC ) PGA = 1, Buffer ON 200 µAPower-Supply Current ADC PGA = 128, Buffer ON 610 µACurrent VREF Supply Current (IVREF ) ADC ON 330 µA IDAC Supply Current (IIDAC ) IDAC = 00h 220 µA (1)The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64). (2)Calibration can minimize these errors. (3)The gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF. (4)∆VOUT is change in digital result.

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com DIGITAL CHARACTERISTICS: DV DD = 2.7V to 5.25V All specifications from TMIN to TMAX , unless otherwise specified. MSC1201Yx, MSC1202Yx PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Power-Supply Requirements DV DD 2.7 3.0 3.6 V Normal Mode, fOSC = 1MHz 0.6 mA Digital Power-Supply Current Normal Mode, fOSC = 8MHz, All Peripherals ON 5 mA Digital Power-Supply Current Internal Oscillator LF Mode (12.8MHz nominal) 7.1 mA Stop Mode, External Clock OFF 100 nA DV DD 4.75 5.0 5.25 V Normal Mode, fOSC = 1MHz 1.2 mA Normal Mode, fOSC = 8MHz, All Peripherals ON 9 mA Digital Power-Supply Current Internal Oscillator LF Mode (12.8MHz nominal) 15 mADigital Power-Supply Current Internal Oscillator HF Mode (25.6MHz nominal) 29 mA Stop Mode, External Clock OFF 100 nA Digital Input/Output (CMOS) Logic Level VIH (except XIN pin) 0.6 • DV DD DV DD V Logic Level VIL (except XIN pin) DGND 0.2 • DV DD V Ports 1 and 3, Input Leakage Current, Input ModeVIH = DVDD or VIH = 0V 0 µA I/O Pin Hysteresis 700 mV VOL , Ports 1 and 3, All Output Modes IOL = 1mA DGND 0.4 V VOL , Ports 1 and 3, All Output Modes IOL = 30mA, 3V (20mA) 1.5 V VOH , Ports 1 and 3, Strong Drive Output IOH = 1mA DV DD − 0.4 DV DD − 0.1 DV DD V VOH , Ports 1 and 3, Strong Drive Output IOH = 30mA, 3V (20mA) DV DD − 1.5 V Ports 1 and 3, Pull-Up Resistors 11 kΩ FLASH MEMORY CHARACTERISTICS: DV DD = 2.7V to 5.25V tUSEC = 1µs and tMSEC = 1ms MSC1201Yx, MSC1202Yx PARAMETER CONDITIONS MIN TYP MAX UNITS Flash Memory Endurance 100,000 1,000,000 cycles Flash Memory Data Retention 100 Years Mass and Page Erase Time Set with FER Value in FTCON, from TMIN to TMAX 10 ms Flash Memory Write Time Set with FWR Value in FTCON 30 40 µs

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com PIN CONFIGURATION P3.7 P3.6/SCK/SCL/CLKS P3.5/T1 P3.4/T0 P3.3/INT1 P3.2/INT0 P3.1/TxD0 P3.0/RxD0 P1.7/INT5 DV DD DGND P1.6/INT4 P1.5/INT3 P1.4/INT2/SS P1.3/DIN P1.2/DOUT P1.1 P1.0/PROG IDAC REFOUT/REFIN+ REFIN − AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 XIN XOUT DGND RST NC AV DD AGND AGND AINCOM 36 35 34 33 32 31 30 29 28 10 11 12 13 14 15 16 17 18 MSC1201 MSC1202

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com PIN ASSIGNMENTS PIN # NAME DESCRIPTION 1 XIN The crystal oscillator pin XIN supports parallel resonant AT cut fundamental frequency crystals and ceramic resonators. XIN can also be an input if there is an external clock source instead of a crystal. XIN must not be left floating. 2 XOUT The crystal oscillator pin XOUT supports parallel resonant AT cut fundamental frequency crystals and ceramic resonators. XOUT serves as the output of the crystal amplifier. 3, 26 DGND Digital Ground 4 RST A HIGH on the reset input for two tOSC periods will reset the device.

5 NC No connection

6 AVDD Analog Power Supply

7, 8 AGND Analog Ground 9 AINCOM Analog Input (can be analog common for single-ended inputs or analog input for differential inputs)

10 IDAC IDAC Output

11 REFOUT/REF IN+ Internal Voltage Reference Output/Voltage Reference Positive Input

12 REF IN− Voltage Reference Negative Input (tie to AGND for internal voltage reference)

13 AIN5 Analog Input Channel 5

14 AIN4 Analog Input Channel 4

15 AIN3 Analog Input Channel 3

16 AIN2 Analog Input Channel 2

17 AIN1 Analog Input Channel 1

18 AIN0 Analog Input Channel 0

19−25, 28 P1.0−P1.7 Port 1 is a bidirectional I/O port (refer to P1DDRL, SFR AEh, and P1DDRH, SFR AFh, for port pin configuration control). The alternate functions for Port 1 are listed below. Port Alternate Name(s) Alternate Use P1.0 PROG Serial programming mode P1.1 N/A P1.2 DOUT Serial data out P1.3 DIN Serial data in P1.4 INT2/SS External interrupt 2 / Slave Select P1.5 INT3 External interrupt 3 P1.6 INT4 External interrupt 4 P1.7 INT5 External interrupt 5

27 DV DD Digital Power Supply

29−36 P3.0−P3.7 Port 3 is a bidirectional I/O port (refer to P3DDRL, SFR B3h, and P3DDRH, SFR B4h, for port pin configuration control). The alternate functions for Port 3 are listed below. Port Alternate Name(s) Alternate Use P3.0 RxD0 Serial port 0 input P3.1 TxD0 Serial port 0 output P3.2 INT0 External interrupt 0 P3.3 INT1 External interrupt 1 P3.4 T0 Timer 0 external input P3.5 T1 Timer 1 external input P3.6 SCK/SCL/CLKS SCK / SCL / various clocks (refer to PASEL, SFR F2h) P1.7 N/A

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com TYPICAL CHARACTERISTICS: MSC1201 ONLY AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. EFFECTIVE NUMBER OF BITS vs DATA RATE ENOB (rms) Data Rate (SPS) 1 10 100 1000 Sinc3 Filter, Buffer OFF PGA1 PGA8 PGA32 PGA64 PGA128 EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO Decimation Ratio = fMOD fDATA 0 500 1000 1500 2000 PGA4 ENOB (rms) PGA1 PGA2 PGA16 PGA8 PGA32 PGA64 PGA128 Sinc3 Filter, Buffer OFF EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 0 500 1000 1500 2000 ENOB (rms) PGA4 PGA8 PGA1 PGA2 PGA16 PGA32 PGA64 PGA128 Decimation Ratio = fMOD fDATA Sinc3 Filter, Buffer ON EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 0 500 1000 1500 2000 ENOB (rms) PGA4 PGA8PGA1 PGA2 PGA16 PGA32 PGA64 PGA128 Decimation Ratio = fMOD fDATA AV DD = 3V, Sinc3 Filter, VREF = 1.25V, Buffer OFF EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 0 500 1000 1500 2000 ENOB (rms) PGA4 PGA8 PGA1 PGA2 PGA16 PGA32 PGA64 PGA128 AV DD = 3V, Sinc3 Filter, VREF = 1.25V, Buffer ON Decimation Ratio = fMOD fDATA EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 0 500 1000 1500 2000 ENOB (rms) PGA4 PGA8 PGA1 PGA2 PGA32 PGA128PGA16 PGA64 Decimation Ratio = fMOD fDATA Sinc2 Filter

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com TYPICAL CHARACTERISTICS: MSC1201 ONLY (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. FAST SETTLING FILTER EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 0 500 1000 2000 1500 ENOB (Bits) Gain = 1 Gain = 128 Decimation Ratio = fMOD fDATA Fast Settling Filter EFFECTIVE NUMBER OF BITS vs fMOD (set with ACLK) ENOB (rms) Data Rate (SPS) 1 10 100 1k 10k 100k fMOD = 15.6kHz fMOD = 62.5kHz fMOD = 203kHz fMOD = 110kHz fMOD = 31.25kHz EFFECTIVE NUMBER OF BITS vs fMOD (set with ACLK) WITH FIXED DECIMATION ENOB (rms) Data Rate (SPS) 10 100 1k 10k 100k DEC = 2020 DEC = 255 DEC = 500 DEC = 50 DEC = 20 DEC = 10 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 NOISE vs INPUT SIGNAL V IN (V) Noise (rms, ppm of FS) 4500 4000 3500 3000 2500 2000 1500 1000 500 HISTOGRAM OF ADC OUTPUT DATA ppm of FS Number of Occurrences − 1.5 − 1 −0.5 0 0.5 1 1.5 2

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com TYPICAL CHARACTERISTICS: MSC1202 ONLY AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. EFFECTIVE NUMBER OF BITS vs DATA RATE ENOB (rms) Data Rate (SPS) 1 10 100 1000 Sinc3 Filter, Buffer OFF PGA1 PGA128 EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO Decimation Ratio = fMOD fDATA 0 500 1000 1500 2000 ENOB (rms) PGA1 PGA128 Sinc3 Filter, Buffer OFF EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 0 500 1000 1500 2000 ENOB (rms) PGA1 PGA128 Decimation Ratio = fMOD fDATA Sinc3 Filter, Buffer ON PGA1 PGA128 EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 0 500 1000 1500 2000 ENOB (rms) Decimation Ratio = fMOD fDATA AV DD = 3V, Sinc3 Filter, VREF = 1.25V, Buffer OFF EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 0 500 1000 1500 2000 ENOB (rms) PGA1 PGA128 AV DD = 3V, Sinc3 Filter, VREF = 1.25V, Buffer ON Decimation Ratio = fMOD fDATA EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 0 500 1000 1500 2000 ENOB (rms) PGA1 Decimation Ratio = fMOD fDATA Sinc2 Filter PGA128

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com TYPICAL CHARACTERISTICS: MSC1201 AND MSC1202 AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. −10 −15 ADC INTEGRAL NONLINEARITY vs INPUT VOLTAGE ADC Input Voltage (V) ADC INL (ppm) AV DD =5 V VREF =2 . 5 V +125/C0095C+85/C0095C +25/C0095C −55/C0095C −40/C0095C −10 −15 ADC INTEGRAL NONLINEARITY vs INPUT SIGNAL VIN (V) VIN = −VREF 0V IN =+ VREF INL (ppm of FS) VREF =A VDD =5 V Buffer OFF ADC INTEGRAL NONLINEARITY vs V REF VREF (V) INL (ppm of FS) VIN =V REF Buffer OFF AV DD =3 V AV DD =5 V ADC INTEGRAL NONLINEARITY ERROR vs PGA PGA Setting INL (ppm of FS) 14 21 6 81 2 8 6432 AV DD =5 V VREF =2 . 5 V 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 ANALOG SUPPLY CURRENT vs ANALOG SUPPLY VOLTAGE Analog Supply Voltage (V) Analog Supply Current (mA) −55/C0095C −40/C0095C +25/C0095C +85/C0095C +125/C0095CPGA = 128 DV DD =A VDD VREF = 1.25V 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 ADC POWER−SUPPLY CURRENT vs PGA PGA Setting 18 24 3 2 16 128 64 IADC (µA) AV DD = 5V, Buffer = ON AV DD = 5V, Buffer = OFF AV DD = 3V, Buffer = ON AV DD = 3V, Buffer = OFF

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com TYPICAL CHARACTERISTICS: MSC1201 AND MSC1202 (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. − 2 − 4 − 6 − 8 − 10 − 12 − 14 − 16 ADC OFFSET DAC: OFFSET vs TEMPERATURE Offset (ppm of FSR) Temperature (/C0095C) −60 −40 − 20 0 +20 +40 +60 +80 +100 +120 +140 1.00008 1.00006 1.00004 1.00002 0.99998 0.99996 0.99994 0.99992 ADC OFFSET DAC: GAIN vs TEMPERATURE Normalized Gain Temperature (/C0095C) − 60 −40 −20 +140 +20 +40 +60 +80 +100 +1200 DIGITAL SUPPLY CURRENT vs EXTERNAL CLOCK FREQUENCY Clock Frequency (MHz) Digital Supply Current (mA) 1 10 100 100 0.1 DV DD =5 V Normal Mode DV DD =3 V Normal Mode DV DD =3 V Idle Mode DV DD =5 V Idle Mode DIGITAL SUPPLY CURRENT vs CLOCK DIVIDER Clock Frequency (MHz) Digital Supply Current (mA) 11 0 1 0 0 100 0.1 1024 Divider Values DIGITAL SUPPLY CURRENT vs DIGITAL SUPPLY VOLTAGE Digital Supply Voltage (V) Digital Supply Current (mA) −55/C0095C −40/C0095C +25/C0095C +85/C0095C +125/C0095C PGA = 128 DV DD =A VDD VREF =1 . 2 5 V A D CN O R M A L I Z E DG A I Nv sP G A PGA Setting Normalized Gain (%) 14 21 6 81 2 8 6432 101 100 Buffer ON

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com TYPICAL CHARACTERISTICS: MSC1201 AND MSC1202 (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. DIGITAL OUTPUT PIN VOLTAGE Output Current (mA) Output Voltage (V) 02 0 10 40 30 70 6050 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 Low Output Low Output VOLTAGE REFERENCE CURRENT vs PGA SETTING PGA Gain 11 2 8 24 8 1 6 3 2 6 4 Input Current (µA) VREF =2 . 5 V fMOD =6 2 . 5 k H z VREF =1 . 2 5 V fMOD =6 2 . 5 k H z VREF =2 . 5 V fMOD =1 5 . 6 k H z VREF =1 . 2 5 V fMOD = 15.6kHz 16.0 15.5 15.0 14.5 14.0 13.5 13.0 12.5 12.0 INTERNAL OSCILLATOR LOW−FREQUENCY MODE vs TEMPERATURE Temperature (/C0095C) −60 0 20 80 60 120 140−20−40 40 100 IO Frequency (MHz) 5.25V 2.7V 3.3V 4.75V INTERNAL OSCILLATOR HIGH−FREQUENCY MODE vs TEMPERATURE Temperature (/C0095C) −60 0 20 80 60 120 140−20−40 40 100 IO Frequency (MHz) 5.25V 4.75V 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 IDAC OUTPUT CURRENT vs IDAC OUTPUT VOLTAGE IDAC Output Votage (V) IDAC Output Current (mA) AV DD =5 V IDAC = FFh AV DD =3 V 960 940 920 900 880 860 840 IDAC OUTPUT CURRENT vs TEMPERATURE Temperature (/C0095C) −60 0 20 80 60 120 140−20−40 40 100 IDAC Output Current (µA)

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com

DESCRIPTION

The MSC1201Yx/MSC1202Yx are completely integrated families of mixed-signal devices incorporating a high-resolution, delta-sigma ADC, 8-bit IDAC, 8-channel multiplexer, burnout detect current sources, selectable buffered input, offset DAC, programmable gain amplifier (PGA), temperature sensor, voltage reference, 8-bit microcontroller, Flash Program Memory, Flash Data Memory, and Data SRAM, as shown in Figure 3. On-chip peripherals include an additional 32-bit accumulator, basic SPI, basic I 2C, USART, multiple digital input/output ports, watchdog timer, low-voltage detect, on-chip power-on reset, brownout reset, timer/counters, system clock divider, PLL, on-chip oscillator, and external interrupts. The devices accept low-level differential or single-ended signals directly from a transducer. The ADC provides 24 bits (MSC1201) or 16 bits (MSC1202) of resolution and 24 bits (MSC1201) or 16 bits (MSC1202) of no-missing-code performance using a Sinc 3 filter with a programmable sample rate. The ADC also has a selectable filter that allows for high-resolution single-cycle conversion. The microcontroller core is 8051 instruction set compatible. The microcontroller core is an optimized 8051 core that executes up to three times faster than the standard 8051 core, given the same clock source. This makes it possible to run the device at a lower external clock frequency and achieve the same performance at lower power than the standard 8051 core. The MSC1201Yx/MSC1202Yx allow the user to uniquely configure the Flash Memory map to meet the needs of their application. The Flash is programmable down to +2.7V using serial programming. Flash endurance is typically 1M Erase/Write cycles. The parts have separate analog and digital supplies, which can be independently powered from +2.7V to +5.25V. At +3V operation, the power dissipation for the part is typically less than 3mW. The MSC1201Yx/MSC1202Yx are both packaged in a QFN-36 package. The MSC1201Yx/MSC1202Yx are designed for high-resolution measurement applications in smart transmitters, industrial process control, weigh scales, chromatography, and portable instrumentation. ACC MUX AV DD BUF PGA VREF Modulator 4K or 8K FLASH

128 Bytes

EXT (4) PROG USART EXT (2) SCK/SCL/CLKS On−Chip Oscillator 8−Bit Offset DAC 8−Bit IDAC Burnout Detect AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AINCOM IDAC AGND REFOUT/REFIN+ DV DD DGND XIN XOUT Temperature Sensor Burnout Detect RST AGND AV DD REF IN−(1) NOTE: (1) REF IN− must be tied to AGND when using internal VREF . Figure 3. Block Diagram

The effects on bits, flags, and registers are the

12 Cycles

4 Cycles

Figure 5. Comparison of MSC1201/02 Timing to Figure 4. Instruction Timing Cycle

Figure 6. MSC1201/02 Timing Chain and Clock Control

the corresponding special function register (SFR) associated with each component. (Unipolar mode) for the 16−bit result in registers DAh and D9h. Figure 7. MSC1201/02 ADC Structure

require a 26-bit ADC to resolve 75nV, as shown in Table 1. Table 1. ENOB versus PGA (Bipolar Mode) using the ODAC does not reduce the range of the ADC. complete system, can be reduced with calibration. both an offset and gain calibration. computes a gain value to nullify gain errors in the system. decimation ratio, buffer, or a change of the PGA. followed by the Sinc3 filter to improve noise performance. frequency response of each filter is shown in Figure 11. (1)With synchronized channel changes. Figure 10. Filter Step Responses

Figure 11. Filter Frequency Responses

Figure 18. SPI Timing Diagram is cleared on reading or writing to the SPIDATA register. SPI in master and slave modes.

Assert SS to enable slave communication (if
Read the received data from SPIDATA.
Configure the ports pins.
Wait for the Count Interrupt (eight SCKs).
Read the data from SPIDATA.

and the previous data will be lost.

clears the CNT interrupt and clock stretch. of the MSC1201/02 are controlled through the SFR. writable (programmable) in User Application mode. commonly used to read lookup tables. families offer two memory configurations. Table 3. Flash Memory Partitioning Table 4. Flash Memory Partitioning Addresses

Figure 20. Memory Map Flash Program Memory that is being used for data storage. for the addresses shown in Table 4. Programming mode, the lower 64 bytes can be written.

to 07h on reset and the user can then move it as needed. each POP or RET decrements it. Table 5. If enabled, the Boot ROM will appear from Table 5. MSC1201/02 Maximum Internal Program Table 6. MSC1201/02 Boot ROM Routines MSC1210 , available at www.ti.com. (1)CADDR must be set using the faddr_data_read routine. (2)MWS register (SFR 8Fh) defines Data Memory or Program Memory write. (3)SFR registers CKCON and TCON must be initialized: CKCON = 0x10 and TCON = 0x00.

P1.0/PROG pin low during reset, as shown in Figure 23. User Application mode also allows for Flash programming. from Boot ROM while programming. Flash Programming mode on power−up. Figure 23. Serial Flash Programming Mode Table 7. Interrupt Summary (1)These interrupts set the AI flag (EICON.4) and are enabled by EAI (EICON.5). (2)If edge-triggered, cleared automatically by hardware when the service routine is vectored to. If level-triggered, the flag follows the state of the pin. (3)Cleared automatically by hardware when interrupt vector occurs. (4)Globally enabled by EA (IE.7).

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com Hardware Configuration Register 0 (HCR0)—Accessed Using SFR Registers CADDR and CDATA. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CADDR 3Fh EPMA PML RSL EBR EWDR 1 DFSEL1 DFSEL0 EPMA Enable Programming Memory Access (Security Bit). bit 7 0: After reset in programming modes, Flash Memory can only be accessed in UAM until a mass erase is done. 1: Fully Accessible (default) PML Program Memory Lock (PML has Priority Over RSL). bit 6 0: Enable read and write for Program Memory in UAM. 1: Enable Read-Only mode for Program Memory in UAM (default). RSL Reset Sector Lock. The reset sector can be used to provide another method of Flash Memory programming. This bit 5 will allow Program Memory updates without changing the jumpers for in-circuit code updates or program development. The code in this boot sector would then provide the monitor and programming routines with the ability to jump into the main Flash code when programming is finished. 0: Enable Reset Sector Writing 1: Enable Read-Only mode for reset sector (4kB) (default). Same effect as PML for the MSC1201Y2/MSC1202Y2. EBR Enable Boot ROM. Boot ROM is 1kB of code located in ROM, not to be confused with the 4kB Boot Sector located bit 4 in Flash Memory. 0: Disable Internal Boot ROM 1: Enable Internal Boot ROM (default) EWDR Enable Watchdog Reset. bit 3 0: Disable Watchdog Reset 1: Enable Watchdog Reset (default) DFSEL1−0 Data Flash Memory Size (See Table 3). bits 1−0 00: 4kB Data Flash Memory (MSC1201Y3/MSC1202Y3 Only) 01: 2kB Data Flash Memory 10: 1kB Data Flash Memory 11: No Data Flash Memory (default)

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com Hardware Configuration Register 1 (HCR1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CADDR 3Eh 1 1 1 1 1 DDB 1 1 DDB Disable Digital Brownout Detection. bit 2 0: Enable Digital Brownout Detection (2.7V) 1: Disable Digital Brownout Detection (default) Hardware Configuration Register 2 (HCR2) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CADDR 3Dh 0 0 0 0 0 CLKSEL2 CLKSEL1 CLKSEL0 CLKSEL2−1 Clock Select. bits 2−0 000: Reserved 001: Reserved 010: Reserved 011: External Clock Mode 100: PLL High-Frequency (HF) Mode 101: PLL Low-Frequency (LF) Mode 110: Internal Oscillator High-Frequency (HF) Mode 111: Internal Oscillator Low-Frequency (LF) Mode

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com SFR DEFINITIONS ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET VALUE 80h 81h SP 07h 82h DPL0 00h 83h DPH0 00h 84h DPL1 00h 85h DPH1 00h 86h DPS 0 0 0 0 0 0 0 SEL 00h 87h PCON SMOD 0 1 1 GF1 GF0 STOP IDLE 30h 88h TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00h 89h 00h89h TMOD GATE C/T M1 M0 GATE C/T M1 M0 00h 8Ah TL0 00h 8Bh TL1 00h 8Ch TH0 00h 8Dh TH1 00h 8Eh CKCON 0 0 0 T1M T0M MD2 MD1 MD0 01h 8Fh MWS 0 0 0 0 0 0 0 MXWS 00h 90h P1 P1.7 INT5 P1.6 INT4 P1.5 INT3 P1.4 INT2/SS P1.3 DIN P1.2 DOUT P1.1 P1.0 PROG FFh 91h EXIF IE5 IE4 IE3 IE2 1 0 0 0 08h 92h MPAGE 93h CADDR 00h 94h CDATA 00h 95h 96h 97h 98h SCON0 SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00h 99h SBUF0 00h 9Ah SPICON I2CCON SBIT3 SBIT3 SBIT2 SBIT2 SBIT1 SBIT1 SBIT0 SBIT0 ORDER STOP CPHA START ESS DCS CPOL CNTSEL 00h 9Bh SPIDATA I2CDATA 00h 9Ch 9Dh 9Eh 9Fh A0h A1h A2h A3h A4h AIPOL SECIP SUMIP ADCIP MSECIP I2CIP CNTIP ALVDIP 0 00h A5h PAI 0 0 0 0 PAI3 PAI2 PAI1 PAI0 00h A6h AIE ESEC ESUM EADC EMSEC EI2C ECNT EALV 0 00h A7h AISTAT SEC SUM ADC MSEC I2C CNT ALVD 0 00h A8h IE EA 0 0 ES0 ET1 EX1 ET0 EX0 00h A9h

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com SFR DEFINITIONS (continued) ADDRESS RESET VALUEBIT 0BIT 1BIT 2BIT 3BIT 4BIT 5BIT 6BIT 7REGISTER AAh ABh ACh ADh AEh P1DDRL P13H P13L P12H P12L P11H P11L P10H P10L 00h AFh P1DDRH P17H P17L P16H P16L P15H P15L P14H P14L 00h B0h P3 P3.7 P3.6 SCK/SCL/CLKS P3.5 P3.4 P3.3 INT1 P3.2 INT0 P3.1 TXD0 P3.0 RXD0 FFh B1h B2h B3h P3DDRL P33H P33L P32H P32L P31H P31L P30H P30L 00h B4h P3DDRH P37H P37L P36H P36L P35H P35L P34H P34L 00h B5h IDAC 00h B6h B7h B8h IP 1 0 0 PS0 PT1 PX1 PT0 PX0 80h B9h BAh BBh BCh BDh BEh BFh C0h C1h C2h C3h C4h C5h C6h EWU EWUWDT EWUEX1 EWUEX0 00h C7h SYSCLK 0 0 DIVMOD1 DIVMOD0 0 DIV2 DIV1 DIV0 00h C8h C9h CAh CBh CCh CDh CEh CFh D0h PSW CY AC F0 RS1 RS0 OV F1 P 00h D1h OCL LSB 00h D2h OCM 00h D3h OCH MSB 00h D4h GCL LSB 5Ah D5h GCM ECh D6h GCH MSB 5Fh

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com SFR DEFINITIONS (continued) ADDRESS RESET VALUEBIT 0BIT 1BIT 2BIT 3BIT 4BIT 5BIT 6BIT 7REGISTER D7h ADMUX INP3 INP2 INP1 INP0 INN3 INN2 INN1 INN0 01h D8h EICON 0 1 EAI AI WDTI 0 0 0 40h D9h ADRESL (1) LSB (1) 00h DAh ADRESM (1) MSB (1) 00h DBh ADRESH (1) MSB (1) 00h DCh ADCON0 BOD EVREF VREFH EBUF PGA2 PGA1 PGA0 30h DDh ADCON1 OF_UF POL SM1 SM0 — CAL2 CAL1 CAL0 00h DEh ADCON2 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 1Bh DFh ADCON3 0 0 0 0 0 DR10 DR9 DR8 06h E1h SSCON SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 00h E2h SUMR0 LSB 00h E3h SUMR1 00h E4h SUMR2 00h E5h SUMR3 MSB 00h E6h ODAC 00h E7h LVDCON ALVDIS 0 0 0 1 1 1 1 8Fh E8h EIE 1 1 1 EWDI EX5 EX4 EX3 EX2 E0h E9h HWPC0 0 0 0 0 0 0 DEVICE MEMORY 0000_00xxb EAh HWPC1 0 0 1 0 0 0 0 0 20h EBh HWVER ECh Reserved EDh Reserved EEh FMCON 0 PGERA 0 FRCM 0 BUSY 1 0 02h EFh FTCON FER3 FER2 FER1 FER0 FWR3 FWR2 FWR1 FWR0 A5h F0h B 00h F1h PDCON PDICLK PDIDAC PDI2C 0 PDADC PDWDT PDST PDSPI 6Fh F2h PASEL PSEN4 PSEN3 PSEN2 PSEN1 PSEN0 0 0 0 00h F3h Reserved F4h PLLL PLL7 PLL6 PLL5 PLL4 PLL3 PLL2 PLL1 PLL0 xxh(2) F5h PLLH CKSTAT2 CKSTAT1 CKSTAT0 PLLLOCK 0 0 PLL9 PLL8 xxh(2) F6h ACLK 0 FREQ6 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03h F7h SRST 0 0 0 0 0 0 0 RSTREQ 00h F8h EIP 1 1 1 PWDI PX5 PX4 PX3 PX2 E0h F9h SECINT WRT SECINT6 SECINT5 SECINT4 SECINT3 SECINT2 SECINT1 SECINT0 7Fh FAh MSINT WRT MSINT6 MSINT5 MSINT4 MSINT3 MSINT2 MSINT1 MSINT0 7Fh FBh USEC 0 0 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03h FCh MSECL MSECL7 MSECL6 MSECL5 MSECL4 MSECL3 MSECL2 MSECL1 MSECL0 9Fh FDh MSECH MSECH7 MSECH6 MSECH5 MSECH4 MSECH3 MSECH2 MSECH1 MSECH0 0Fh FEh HMSEC HMSEC7 HMSEC6 HMSEC5 HMSEC4 HMSEC3 HMSEC2 HMSEC1 HMSEC0 63h FFh WDTCON EWDT DWDT RWDT WDCNT4 WDCNT3 WDCNT2 WDCNT1 WDCNT0 00h (1)For the MSC1201, the ADC result is contained in ADRESH, ADRESM, and ADRESL. For the MSC1202, the ADC result is contained in ADRESM and ADRESL (that is, shifted right one byte) and the MSB is sign-extended (Bipolar mode) or zero-padded (Unipolar mode) in ADRESH. T herefore, when migrating between the MSC1201 and MSC1202, the ADC result calculation must be adjusted accordingly. For both the MSC1201 and MSC1202, the ADC interrupt is cleared by reading ADRESL. (2)Dependent on HCR2 value.

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com Stack Pointer (SP) 7 6 5 4 3 2 1 0 Reset Value SP .7−0 Stack Pointer. The stack pointer identifies the location where the stack will begin. The stack pointer is incremented before bits 7−0 every PUSH or CALL operation and decremented after each POP or RET/RETI. This register defaults to 07h after reset. Data Pointer Low 0 (DPL0) 7 6 5 4 3 2 1 0 Reset Value DPL0.7−0 Data Pointer Low 0. This register is the low byte of the standard 8051 16-bit data pointer. DPL0 and DPH0 are used bits 7−0 to point to non-scratchpad data RAM. The current data pointer is selected by DPS (SFR 86h). Data Pointer High 0 (DPH0) 7 6 5 4 3 2 1 0 Reset Value DPH0.7−0 Data Pointer High 0. This register is the high byte of the standard 8051 16-bit data pointer. DPL0 and DPH0 are used bits 7−0 to point to non-scratchpad data RAM. The current data pointer is selected by DPS (SFR 86h). Data Pointer Low 1 (DPL1) 7 6 5 4 3 2 1 0 Reset Value DPL1.7−0 Data Pointer Low 1. This register is the low byte of the auxiliary 16-bit data pointer. When the SEL bit (DPS.0) bits 7−0 (SFR 86h) is set, DPL1 and DPH1 are used in place of DPL0 and DPH0 during DPTR operations. Data Pointer High 1 (DPH1) 7 6 5 4 3 2 1 0 Reset Value DPH1.7−0 Data Pointer High. This register is the high byte of the auxiliary 16-bit data pointer. When the SEL bit (DPS.0) bits 7−0 (SFR 86h) is set, DPL1 and DPH1 are used in place of DPL0 and DPH0 during DPTR operations. Data Pointer Select (DPS) 7 6 5 4 3 2 1 0 Reset Value SFR 86h 0 0 0 0 0 0 0 SEL 00h SEL Data Pointer Select. This bit selects the active data pointer. bit 0 0: Instructions that use the DPTR will use DPL0 and DPH0. 1: Instructions that use the DPTR will use DPL1 and DPH1.

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com Power Control (PCON) 7 6 5 4 3 2 1 0 Reset Value SFR 87h SMOD 0 1 1 GF1 GF0 STOP IDLE 30h SMOD Serial Port 0 Baud Rate Doubler Enable. The serial baud rate doubling function for Serial Port 0. bit 7 0: Serial Port 0 baud rate will be a standard baud rate. 1: Serial Port 0 baud rate will be double that defined by baud rate generation equation. GF1 General-Purpose User Flag 1. This is a general-purpose flag for software control. bit 3 GF0 General-Purpose User Flag 0. This is a general-purpose flag for software control. bit 2 STOP Stop Mode Select. Setting this bit will halt the internal oscillator and block external clocks. This bit will always read as 0. bit 1 Exit with RESET. In this mode, internal peripherals are frozen and I/O pins are held in their current state. The ADC is frozen, but IDAC and VREF remain active. IDLE Idle Mode Select. Setting this bit will freeze the CPU, Timer 0 and 1, and the USART; other peripherals remain active. bit 0 This bit will always be read as a 0. Exit with AIE (A6h) and EWU (C6h) interrupts (refer to Figure 6 for clocks affected during IDLE). Timer/Counter Control (TCON) 7 6 5 4 3 2 1 0 Reset Value SFR 88h TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00h TF1 Timer 1 Overflow Flag. This bit indicates when Timer 1 overflows its maximum count as defined by the current mode. bit 7 This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine. 0: No Timer 1 overflow has been detected. 1: Timer 1 has overflowed its maximum count. TR1 Timer 1 Run Control. This bit enables/disables the operation of Timer 1. Halting this timer will preserve the current bit bit 6 6 c ount in TH1, TL1. 0: Timer is halted. 1: Timer is enabled. TF0 Timer 0 Overflow Flag. This bit indicates when Timer 0 overflows its maximum count as defined by the current mode. bit 5 This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 0 interrupt service routine. 0: No Timer 0 overflow has been detected. 1: Timer 0 has overflowed its maximum count. TR0 Timer 0 Run Control. This bit enables/disables the operation of Timer 0. Halting this timer will preserve the current bit 4 count in TH0, TL0. 0: Timer is halted. 1: Timer is enabled. IE1 Interrupt 1 Edge Detect. This bit is set when an edge/level of the type defined by IT1 is detected. If IT1 = 1, this bit bit 3 will remain set until cleared in software or the start of the External Interrupt 1 service routine. If IT1 = 0, this bit will inversely reflect the state of the INT1 pin. IT1 Interrupt 1 Type Select. This bit selects whether the INT1 pin will detect edge- or level-triggered interrupts. bit 2 0: INT1 is level triggered. 1: INT1 is edge triggered. IE0 Interrupt 0 Edge Detect. This bit is set when an edge/level of the type defined by IT0 is detected. If IT0 = 1, this bit bit 1 will remain set until cleared in software or the start of the External Interrupt 0 service routine. If IT0 = 0, this bit will inversely reflect the state of the INT0 pin. IT0 Interrupt 0 Type Select. This bit selects whether the INT0 pin will detect edge- or level-triggered interrupts. bit 0 0: INT0 is level triggered. 1: INT0 is edge triggered.

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com Timer Mode Control (TMOD) 7 6 5 4 3 2 1 0 Reset Value SFR 89h TIMER 1 TIMER 0 00hSFR 89h GATE C/T M1 M0 GATE C/T M1 M0 00h GATE Timer 1 Gate Control. This bit enables/disables the ability of Timer 1 to increment. bit 7 0: Timer 1 will clock when TR1 = 1, regardless of the state of pin INT1. 1: Timer 1 will clock only when TR1 = 1 and pin INT1 = 1. C/T Timer 1 Counter/Timer Select. bit 6 0: Timer is incremented by internal clocks. 1: Timer is incremented by pulses on T1 pin when TR1 (TCON.6, SFR 88h) is 1. M1, M0 Timer 1 Mode Select. These bits select the operating mode of Timer 1. bits 5−4 M1 M0 MODE 0 0 Mode 0: 8-bit counter with 5-bit prescale. 0 1 Mode 1: 16 bits. 1 0 Mode 2: 8-bit counter with auto reload. 1 1 Mode 3: Timer 1 is halted, but holds its count. GATE Timer 0 Gate Control. This bit enables/disables the ability of Timer 0 to increment. bit 3 0: Timer 0 will clock when TR0 = 1, regardless of the state of pin INT0 (software control). 1: Timer 0 will clock only when TR0 = 1 and pin INT0 = 1 (hardware control). C/T Timer 0 Counter/Timer Select. bit 2 0: Timer is incremented by internal clocks. 1: Timer is incremented by pulses on pin T0 when TR0 (TCON.4, SFR 88h) is 1. M1, M0 Timer 0 Mode Select. These bits select the operating mode of Timer 0. bits 1−0 M1 M0 MODE 0 0 Mode 0: 8-bit counter with 5-bit prescale. 0 1 Mode 1: 16 bits. 1 0 Mode 2: 8-bit counter with auto reload. 1 1 Mode 3: Two 8-bit counters. Timer 0 LSB (TL0) 7 6 5 4 3 2 1 0 Reset Value TL0.7−0 Timer 0 LSB. This register contains the least significant byte of Timer 0. bits 7−0 Timer 1 LSB (TL1) 7 6 5 4 3 2 1 0 Reset Value TL1.7−0 Timer 1 LSB. This register contains the least significant byte of Timer 1. bits 7−0

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com Timer 0 MSB (TH0) 7 6 5 4 3 2 1 0 Reset Value TH0.7−0 Timer 0 MSB. This register contains the most significant byte of Timer 0. bits 7−0 Timer 1 MSB (TH1) 7 6 5 4 3 2 1 0 Reset Value TH1.7−0 Timer 1 MSB. This register contains the most significant byte of Timer 1. bits 7−0 Clock Control (CKCON) 7 6 5 4 3 2 1 0 Reset Value SFR 8Eh 0 0 0 T1M T0M MD2 MD1 MD0 01h T1M Timer 1 Clock Select. This bit controls the division of the system clock that drives Timer 1. Clearing this bit to 0 bit 4 maintains 8051 compatibility. This bit has no effect on instruction cycle timing. 0: Timer 1 uses a divide-by-12 of the crystal frequency. 1: Timer 1 uses a divide-by-4 of the crystal frequency. T0M Timer 0 Clock Select. This bit controls the division of the system clock that drives Timer 0. Clearing this bit to 0 bit 3 maintains 8051 compatibility. This bit has no effect on instruction cycle timing. 0: Timer 0 uses a divide-by-12 of the crystal frequency. 1: Timer 0 uses a divide-by-4 of the crystal frequency. MD2, MD1, MD0 Stretch MOVX Select. These bits select the time by which external MOVX cycles are to be stretched. Since bits 2−0 the MSC1201/02 does not allow external memory access, these bits should be set to 000 B to allow for the fastest Flash Data Memory access. Memory Write Select (MWS) 7 6 5 4 3 2 1 0 Reset Value SFR 8Fh 0 0 0 0 0 0 0 MXWS 00h MXWS MOVX Write Select. This allows writing to the internal Flash Program Memory. bit 0 0: No writes are allowed to the internal Flash Program Memory. 1: Writing is allowed to the internal Flash Program Memory, unless PML or RSL (HCR0, CADDR 3Fh) are on.

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com Port 1 (P1) 7 6 5 4 3 2 1 0 Reset Value SFR 90h P1.7 INT5 P1.6 INT4 P1.5 INT3 P1.4 INT2/SS P1.3 DIN P1.2 DOUT P1.1 P1.0 PROG FFh P1.7−0 General-Purpose I/O Port 1. This register functions as a general-purpose I/O port. In addition, all the pins have an bits 7−0 alternative function listed below. Each of the functions is controlled by several other SFRs. The associated Port 1 latch bit must contain a logic ‘1’ before the pin can be used in its alternate function capacity. To use the alternate function, set the appropriate mode in P1DDRL (SFR AEh), P1DDRH (SFR AFh). INT5 External Interrupt 5. A falling edge on this pin will cause an external interrupt 5 if enabled. bit 7 INT4 External Interrupt 4. A rising edge on this pin will cause an external interrupt 4 if enabled. bit 6 INT3 External Interrupt 3. A falling edge on this pin will cause an external interrupt 3 if enabled. bit 5 INT2/SS External Interrupt 2. A rising edge on this pin will cause an external interrupt 2 if enabled. This pin can be used as bit 4 slave select (SS ) in SPI slave mode. DIN Serial Data In. This pin receives serial data in SPI and I2C modes (in I2C mode, this pin should be configured as an bit 3 input) or standard 8051. DOUT Serial Data Out. This pin transmits serial data in SPI and I2C modes (in I2C mode, this pin should be configured as bit 2 an open drain) or standard 8051. PROG Program Mode. When this pin is pulled low at power-up, the device enters Serial Programming mode (refer to bit 0 Figure 2). External Interrupt Flag (EXIF) 7 6 5 4 3 2 1 0 Reset Value SFR 91h IE5 IE4 IE3 IE2 1 0 0 0 08h IE5 External Interrupt 5 Flag. This bit will be set when a falling edge is detected on INT5. This bit must be cleared bit 7 manually by software. Setting this bit in software will cause an interrupt if enabled. IE4 External Interrupt 4 Flag. This bit will be set when a rising edge is detected on INT4. This bit must be cleared bit 6 manually by software. Setting this bit in software will cause an interrupt if enabled. IE3 External Interrupt 3 Flag. This bit will be set when a falling edge is detected on INT3. This bit must be cleared bit 5 manually by software. Setting this bit in software will cause an interrupt if enabled. IE2 External Interrupt 2 Flag. This bit will be set when a rising edge is detected on INT2. This bit must be cleared bit 4 manually by software. Setting this bit in software will cause an interrupt if enabled.

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com Configuration Address Register (CADDR) (write-only) 7 6 5 4 3 2 1 0 Reset Value SFR 93h 00h CADDR Configuration Address Register. This register supplies the address for reading bytes in the 64 bytes of Flash bits 7−0 Configuration Memory. Always use the Boot ROM CADDR access routine (faddr_data_read). This register is also used for SFR read and write routines. CAUTION: If this register is written to while executing from Flash Memory, the CDATA register will be incorrect. Configuration Data Register (CDATA) (read-only) 7 6 5 4 3 2 1 0 Reset Value SFR 94h 00h CDATA Configuration Data Register. This register will contain the data in the 64 bytes of Flash Configuration Memory that bits 7−0 is located at the last written address in the CADDR register. This is a read-only register. Serial Port 0 Control (SCON0) 7 6 5 4 3 2 1 0 Reset Value SFR 98h SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00h SM0−2 Serial Port 0 Mode. These bits control the mode of serial Port 0. Modes 1, 2, and 3 have 1 start and 1 stop bit in bits 7−5 addition to the 8 or 9 data bits. MODE SM0 SM1 SM2 FUNCTION LENGTH PERIOD 0 0 0 0 Synchronous 8 bits 12 pCLK (1) 0 0 0 1 Synchronous 8 bits 4 pCLK (1) 1 0 1 0 Asynchronous 10 bits Timer 1 Baud Rate Equation 1 0 1 1 Asynchronous−Valid Stop Required(2) 10 bits Timer 1 Baud Rate Equation 2 1 0 0 Asynchronous 11 bits 64 pCLK (1) (SMOD = 0) 32 pCLK (1) (SMOD = 1) 2 1 0 1 Asynchronous with Multiprocessor Communication 11 bits 64 pCLK (1) (SMOD = 0) 32 pCLK (1) (SMOD = 1) 3 1 1 0 Asynchronous 11 bits Timer 1 Baud Rate Equation 3 1 1 1 Asynchronous with Multiprocessor Communication(3) 11 bits Timer 1 Baud Rate Equation (1)pCLK will be equal to tCLK , except that pCLK will stop for IDLE. (2)RI_0 will only be activated when a valid STOP is received. (3)RI_0 will not be activated if bit 9 = 0. REN_0 Receive Enable. This bit enables/disables the serial Port 0 received shift register. bit 4 0: Serial Port 0 reception disabled. 1: Serial Port 0 received enabled (modes 1, 2, and 3). Initiate synchronous reception (mode 0). TB8_0 9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial Port 0 modes 2 and 3. bit 3 RB8_0 9th Received Bit State. This bit identifies the state of the 9th reception bit of received data in serial Port 0 modes bit 2 2 and 3. In serial port mode 1, when SM2_0 = 0, RB8_0 is the state of the stop bit. RB8_0 is not used in mode 0. TI_0 Transmitter Interrupt Flag. This bit indicates that data in the serial Port 0 buffer has been completely shifted out. In serial bit 1 port mode 0, TI_0 is set at the end of the 8th data bit. In all other modes, this bit is set at the end of the last data bit. This bit must be manually cleared by software. RI_0 Receiver Interrupt Flag. This bit indicates that a byte of data has been received in the serial Port 0 buffer. In serial bit 0 port mode 0, RI_0 is set at the end of the 8th bit. In serial port mode 1, RI_0 is set after the last sample of the incoming stop bit subject to the state of SM2_0. In modes 2 and 3, RI_0 is set after the last sample of RB8_0. This bit must be manually cleared by software.

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com Serial Data Buffer 0 (SBUF0) 7 6 5 4 3 2 1 0 Reset Value SFR 99h 00h SBUF0 Serial Data Buffer 0. Data for Serial Port 0 is read from or written to this location. The serial transmit and receive bits 7−0 buffers are separate registers, but both are addressed at this location. SPI Control (SPICON) 7 6 5 4 3 2 1 0 Reset Value SFR 9Ah SBIT3 SBIT2 SBIT1 SBIT0 ORDER CPHA ESS CPOL 00h SBIT3−0 Serial Bit Count. Number of bits transferred (read-only). bits 7−4 SBIT3:0 COUNT 0x00 0 0x01 1 0x03 2 0x02 3 0x06 4 0x07 5 0x05 6 0x04 7 0x0C 8 ORDER Set Bit Order for Transmit and Receive. bit 3 0: Most Significant Bits First 1: Least Significant Bits First CPHA Serial Clock Phase Control. bit 2 0: Valid data starting from half SCK period before the first edge of SCK 1: Valid data starting from the first edge of SCK ESS Enable Slave Select. bit 1 0: SS (P1.4) is configured as a general-purpose I/O (default). 1: SS (P1.4) is configured as SS for SPI mode. DOUT (P1.2) drives when SS is low, and DOUT (P1.2) is high-impedance when SS is high. CPOL Serial Clock Polarity. bit 0 0: SCK idle at logic LOW 1: SCK idle at logic HIGH

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com I2C Control (I2CCON) 7 6 5 4 3 2 1 0 Reset Value SFR 9Ah SBIT3 SBIT2 SBIT1 SBIT0 STOP START DCS CNTSEL 00h SBIT3−0 Serial Bit Count. Number of bits transferred (read-only). bits 7−4 SBIT3:0 COUNT 0x00 0 0x01 1 0x03 2 0x02 3 0x06 4 0x07 5 0x05 6 0x04 7 0x0C 8 STOP Stop-Bit Status. bit 3 0: No Stop 1: Stop Condition Received and I2CCNT set (cleared on write to I2CDATA) START Start-Bit Status. bit 2 0: No Stop 1: Start or Repeated Start Condition Received and I2CCNT set (cleared on write to I2CDATA) DCS Disable Serial Clock Stretch. bit 1 0: Enable SCL Stretch (cleared by firmware or START condition) 1: Disable SCL Stretch CNTSEL Counter Select. bit 0 0: Counter IRQ Set for Bit Counter = 8 (default) 1: Counter IRQ Set for Bit Counter = 1 (default) SPI Data Register (SPIDATA) / I2C Data Register (I2CDATA) 7 6 5 4 3 2 1 0 Reset Value SFR 9Bh 00h SPIDATA SPI Data Register. Data for SPI is read from or written to this location. The SPI transmit and receive buffers are bits 7−0 separate registers, but both are addressed at this location. Read to clear the receive interrupt and write to clear the transmit interrupt. I2CDATA I2C Data Register. Data for I2C is read from or written to this location. The I2C transmit and receive buffers are bits 7−0 separate registers, but both are addressed at this location.

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com Auxiliary Interrupt Poll (AIPOL) 7 6 5 4 3 2 1 0 Reset Value SFR A4h SECIP SUMIP ADCIP MSECIP I2CIP CNTIP ALVDIP 0 00h Interrupts are enabled by EICON.4 (SFR D8h). The other interrupts are controlled by the IE and EIE registers. SECIP Second System Timer Interrupt Poll (before IRQ masking). bit 7 0 = Second System Timer Interrupt Poll Inactive 1 = Second System Timer Interrupt Poll Active SUMIP Accumulator Interrupt Poll (before IRQ masking). bit 6 0 = Accumulator Interrupt Poll Inactive 1 = Accumulator Interrupt Poll Active ADCIP ADC Interrupt Poll (before IRQ masking). bit 5 0 = ADC Interrupt Poll Inactive 1 = ADC Interrupt Poll Active MSECIP Millisecond System Timer Interrupt Poll (before IRQ masking). bit 4 0 = Millisecond System Timer Interrupt Poll Inactive 1 = Millisecond System Timer Interrupt Poll Active I2CIP I 2C Interrupt Poll (before IRQ masking). bit 3 0 = I 2C Interrupt Poll Inactive 1 = I2C Interrupt Poll Active CNTIP Serial Bit Count Interrupt Poll (before IRQ masking). bit 2 0 = Serial Bit Count Interrupt Poll Inactive 1 = Serial Bit Count Interrupt Poll Active ALVDIP Analog Low Voltage Detect Interrupt Poll (before IRQ masking). bit 1 0 = Analog Low Voltage Detect Interrupt Poll Inactive 0 = Analog Low Voltage Detect Interrupt Poll Active Pending Auxiliary Interrupt (PAI) 7 6 5 4 3 2 1 0 Reset Value SFR A5h 0 0 0 0 PAI3 PAI2 PAI1 PAI0 00h PAI Pending Auxiliary Interrupt Register. The results of this register can be used as an index to vector to the bits 3−0 appropriate interrupt routine. All of these interrupts vector through address 0033h. PAI3 PAI2 PAI1 PAI0 AUXILIARY INTERRUPT STATUS 0 0 0 0 No Pending Auxiliary IRQ. 0 0 0 1 Reserved. 0 0 1 0 Analog Low Voltage Detect IRQ and Possible Lower Priority Pending. 0 0 1 1 I2C IRQ and Possible Lower Priority Pending. 0 1 0 0 Serial Bit Count Interrupt and Possible Lower Priority Pending. 0 1 0 1 Millisecond System Timer IRQ and Possible Lower Priority Pending. 0 1 1 0 ADC IRQ and Possible Lower Priority Pending. 0 1 1 1 Accumulator IRQ and Possible Lower Priority Pending. 1 0 0 0 Second System Timer IRQ and Possible Lower Priority Pending.

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com Auxiliary Interrupt Enable (AIE) 7 6 5 4 3 2 1 0 Reset Value SFR A6h ESEC ESUM EADC EMSEC EI2C ECNT EALV 0 00h Interrupts are enabled by EICON.4 (SFR D8h). The other interrupts are controlled by the IE and EIE registers. ESEC Enable Second System T imer Interrupt (lowest priority auxiliary interrupt). bit 7 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: Second Timer Interrupt mask. ESUM Enable Summation Interrupt. bit 6 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: Summation Interrupt mask. EADC Enable ADC Interrupt. bit 5 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: ADC Interrupt mask. EMSEC Enable Millisecond System Timer Interrupt. bit 4 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: Millisecond System Timer Interrupt mask. ESPIT Enable I 2C Start/Stop Bit. bit 3 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: I2C Start/Stop Bit mask. ECNT Enable Serial Bit Count Interrupt. bit 2 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: Serial Bit Count Interrupt mask. EALV Enable Analog Low Voltage Interrupt. bit 1 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: Analog Low Voltage Detect Interrupt mask.

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com Auxiliary Interrupt Status Register (AISTAT) 7 6 5 4 3 2 1 0 Reset Value SFR A6h SEC SUM ADC MSEC I2C CNT ALVD 0 00h SEC Second System Timer Interrupt Status Flag (lowest priority AI). bit 7 0: SEC interrupt cleared or masked. 1: SEC Interrupt active (it is cleared by reading SECINT, SFR F9h). SUM Summation Register Interrupt Status Flag. bit 6 0: SUM interrupt cleared or masked. 1: SUM interrupt active (it is cleared by reading the lowest byte of SUMR0, SFR E2h). ADC ADC Interrupt Status Flag. bit 5 0: ADC interrupt cleared or masked. 1: ADC interrupt active (it is cleared by reading the lowest byte of ADRESL, SFR D9h; if active, no new data will be written to the ADC Results registers). MSEC Millisecond System Timer Interrupt Status Flag. bit 4 0: MSEC interrupt cleared or masked. 1: MSEC interrupt active (it is cleared by reading MSINT, SFR FAh). I2C I 2C Start/Stop Interrupt Status Flag. bit 3 0: I 2C Start/stop interrupt cleared or masked. 1: I2C Start/stop interrupt active (it is cleared by writing to I2CDATA, SFR 9Bh). CNT CNT Interrupt Status Flag. bit 2 0: CNT Interrupt cleared or masked. 1: CNT Interrupt active (it is cleared by reading from or writing to SPIDATA/I2CDATA, SFR 9Bh). ALVD Analog Low Voltage Detect Interrupt Status Flag. bit 1 0: ALVD Interrupt cleared or masked. 1: ALVD Interrupt active (cleared in HW if AVDD exceeds ALVD threshold). NOTE: If an interrupt is masked, the status can be read in AIPOL (SFR A4h).

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com Interrupt Enable (IE) 7 6 5 4 3 2 1 0 Reset Value SFR A8h EA 0 0 ES0 ET1 EX1 ET0 EX0 00h EA Global Interrupt Enable. This bit controls the global masking of all interrupts except those in AIE (SFR A6h). bit 7 0: Disable interrupt sources. This bit overrides individual interrupt mask settings for this register. 1: Enable all individual interrupt masks. Individual interrupts in this register will occur if enabled. ES0 Enable Serial port 0 Interrupt. This bit controls the masking of the serial Port 0 interrupt. bit 4 0: Disable all serial Port 0 interrupts. 1: Enable interrupt requests generated by the RI_0 (SCON0.0, SFR 98h) or TI_0 (SCON0.1, SFR 98h) flags. ET1 Enable T imer 1 Interrupt. This bit controls the masking of the Timer 1 interrupt. bit 3 0: Disable Timer 1 interrupt. 1: Enable interrupt requests generated by the TF1 flag (TCON.7, SFR 88h). EX1 Enable External Interrupt 1. This bit controls the masking of external interrupt 1. bit 2 0: Disable external interrupt 1. 1: Enable interrupt requests generated by the INT1 pin. ET0 Enable T imer 0 Interrupt. This bit controls the masking of the Timer 0 interrupt. bit 1 0: Disable all Timer 0 interrupts. 1: Enable interrupt requests generated by the TF0 flag (TCON.5, SFR 88h). EX0 Enable External Interrupt 0. This bit controls the masking of external interrupt 0. bit 0 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the INT0 pin.

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com Port 1 Data Direction Low Register (P1DDRL) 7 6 5 4 3 2 1 0 Reset Value SFR AEh P13H P13L P12H P12L P11H P11L P10H P10L 00h P1.3 Port 1 bit 3 control. bits 7−6 P13H P13L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P1.2 Port 1 bit 2 control. bits 5−4 P12H P12L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P1.1 Port 1 bit 1 control. bits 3−2 P11H P11L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P1.0 Port 1 bit 0 control. bits 1−0 P10H P10L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com Port 1 Data Direction High Register (P1DDRH) 7 6 5 4 3 2 1 0 Reset Value SFR AFh P17H P17L P16H P16L P15H P15L P14H P14L 00h P1.7 Port 1 bit 7 control. bits 7−6 P17H P17L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P1.6 Port 1 bit 6 control. bits 5−4 P16H P16L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P1.5 Port 1 bit 5 control. bits 3−2 P15H P15L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P1.4 Port 1 bit 4 control. bits 1−0 P14H P14L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com Port 3 (P3) 7 6 5 4 3 2 1 0 Reset Value SFR B0h P3.7 P3.6 SCK/SCL/CLKS P3.5 P3.4 P3.3 INT1 P3.2 INT0 P3.1 TXD0 P3.0 RXD0 FFh P3.7−0 General-Purpose I/O Port 3. This register functions as a general-purpose I/O port. In addition, all the pins have an bits 7−0 alternative function listed below. Each of the functions is controlled by several other SFRs. The associated Port 3 latch bit must contain a logic ‘1’ before the pin can be used in its alternate function capacity. SCK/SCL/CLKS Clock Source Select. Refer to PASEL (SFR F2h). bit 6 T1 Timer/Counter 1 External Input. A 1 to 0 transition on this pin will increment Timer 1. bit 5 T0 Timer/Counter 0 External Input. A 1 to 0 transition on this pin will increment Timer 0. bit 4 INT1 External Interrupt 1. A falling edge/low level on this pin will cause an external interrupt 1 if enabled. bit 3 INT0 External Interrupt 0. A falling edge/low level on this pin will cause an external interrupt 0 if enabled. bit 2 TXD0 Serial Port 0 Transmit. This pin transmits the serial Port 0 data in serial port modes 1, 2, 3, and emits the bit 1 synchronizing clock in serial port mode 0. RXD0 Serial Port 0 Receive. This pin receives the serial Port 0 data in serial port modes 1, 2, 3, and is a bidirectional data bit 0 transfer pin in serial port mode 0.

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com Port 3 Data Direction Low Register (P3DDRL) 7 6 5 4 3 2 1 0 Reset Value SFR B3h P33H P33L P32H P32L P31H P31L P30H P30L 00h P3.3 Port 3 bit 3 control. bits 7−6 P33H P33L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P3.2 Port 3 bit 2 control. bits 5−4 P32H P32L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P3.1 Port 3 bit 1 control. bits 3−2 P31H P31L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P3.0 Port 3 bit 0 control. bits 1−0 P30H P30L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com Port 3 Data Direction High Register (P3DDRH) 7 6 5 4 3 2 1 0 Reset Value SFR B4h P37H P37L P36H P36L P35H P35L P34H P34L 00h P3.7 Port 3 bit 7 control. bits 7−6 P37H P37L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input NOTE : Port 3.7 also controlled by EA and Memory Access Control HCR1.1. P3.6 Port 3 bit 6 control. bits 5−4 P36H P36L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input NOTE : Port 3.6 also controlled by EA and Memory Access Control HCR1.1. P3.5 Port 3 bit 5 control. bits 3−2 P35H P35L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P3.4 Port 3 bit 4 control. bits 1−0 P34H P34L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com IDAC Register 7 6 5 4 3 2 1 0 Reset Value SFR B5h 00h IDAC IDAC Register. bits 7−0 IDAC OUT = IDAC • 3.8µA (∼1mA full-scale). Setting (PDCON.PDIDAC) will shut down IDAC and float the IDAC pin. Interrupt Priority (IP) 7 6 5 4 3 2 1 0 Reset Value SFR B8h 1 0 0 PS0 PT1 PX1 PT0 PX0 80h PS0 Serial Port 0 Interrupt. This bit controls the priority of the serial Port 0 interrupt. bit 4 0 = Serial Port 0 priority is determined by the natural priority order. 1 = Serial Port 0 is a high priority interrupt. PT1 Timer 1 Interrupt. This bit controls the priority of the Timer 1 interrupt. bit 3 0 = Timer 1 priority is determined by the natural priority order. 1 = Timer 1 priority is a high priority interrupt. PX1 External Interrupt 1. This bit controls the priority of external interrupt 1. bit 2 0 = External interrupt 1 priority is determined by the natural priority order. 1 = External interrupt 1 is a high priority interrupt. PT0 Timer 0 Interrupt. This bit controls the priority of the Timer 0 interrupt. bit 1 0 = Timer 0 priority is determined by the natural priority order. 1 = Timer 0 priority is a high priority interrupt. PX0 External Interrupt 0. This bit controls the priority of external interrupt 0. bit 0 0 = External interrupt 0 priority is determined by the natural priority order. 1 = External interrupt 0 is a high priority interrupt. Enable Wake Up (EWU) Waking Up from IDLE Mode 7 6 5 4 3 2 1 0 Reset Value SFR C6h — — — — — EWUWDT EWUEX1 EWUEX0 00h Auxiliary interrupts will wake up from IDLE. They are enabled with EAI (EICON.5). EWUWDT Enable Wake Up Watchdog Timer. Wake using watchdog timer interrupt. bit 2 0 = Do not wake up on watchdog timer interrupt. 1 = Wake up on watchdog timer interrupt. EWUEX1 Enable Wake Up External 1. Wake using external interrupt source 1. bit 1 0 = Do not wake up on external interrupt source 1. 1 = Wake up on external interrupt source 1. EWUEX0 Enable Wake Up External 0. Wake using external interrupt source 0. bit 0 0 = Do not wake up on external interrupt source 0. 1 = Wake up on external interrupt source 0.

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com System Clock Divider Register (SYSCLK) 7 6 5 4 3 2 1 0 Reset Value SFR C7h 0 0 DIVMOD1 DIVMOD0 0 DIV2 DIV1 DIV0 00h DIVMOD1−0 Clock Divide Mode bits 5−4 Write: DIVMOD DIVIDE MODE 00 Normal mode (default, no divide). 01 Immediate mode: start divide immediately; return to Normal mode on IDLE wakeup condition or Normal mode write. 10 Delay mode: same as Immediate mode, except that the mode changes with the millisecond interrupt (MSINT). If MSINT is enabled, the divide will start on the next MSINT and return to normal mode on the following MSINT. If MSINT is not enabled, the divide will start on the next MSINT condition (even if masked) but will not leave the divide mode until the MSINT counter overflows, which follows a wakeup condition. Can exit on Normal mode write. 11 Manual mode: start divide immediately; exit mode only on write to DIVMOD. Read: DIVMOD DIVISION MODE STATUS

00 No divide

01 Divider is in Immediate mode

10 Divider is in Delay mode

11 Medium mode

DIV2−0 Divide Mode bit 2−0 DIV DIVISOR

000 Divide by 2 (default) fCLK = fSYS /2

001 Divide by 4 fCLK = fSYS /4

010 Divide by 8 fCLK = fSYS /8

011 Divide by 16 fCLK = fSYS /16

100 Divide by 32 fCLK = fSYS /32

101 Divide by 1024 fCLK = fSYS /1024

110 Divide by 2048 fCLK = fSYS /2048

111 Divide by 4096 fCLK = fSYS /4096

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com Program Status Word (PSW) 7 6 5 4 3 2 1 0 Reset Value SFR D0h CY AC F0 RS1 RS0 OV F1 P 00h CY Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (during addition) or a borrow (during bit 7 subtraction). Otherwise it is cleared to 0 by all arithmetic operations. AC Auxiliary Carry Flag. This bit is set to 1 if the last arithmetic operation resulted in a carry into (during addition), or bit 6 a borrow (during subtraction) from the high order nibble. Otherwise it is cleared to 0 by all arithmetic operations. F0 User Flag 0. This is a bit-addressable, general-purpose flag for software control. bit 5 RS1, RS0 Register Bank Select 1−0. These bits select which register bank is addressed during register accesses. bits 4−3 RS1 RS0 REGISTER BANK ADDRESS 0 0 0 00h − 07h 0 1 1 08h − 0Fh 1 0 2 10h − 17h 1 1 3 18h − 1Fh OV Overflow Flag. This bit is set to 1 if the last arithmetic operation resulted in a carry (addition), borrow (subtraction), bit 2 or overflow (multiply or divide). Otherwise it is cleared to 0 by all arithmetic operations. F1 User Flag 1. This is a bit-addressable, general-purpose flag for software control. bit 1 P Parity Flag. This bit is set to 1 if the modulo-2 sum of the 8 bits of the accumulator is 1 (odd parity); and cleared to bit 0 0 on even parity.

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com ADC Offset Calibration Register Low Byte (OCL) 7 6 5 4 3 2 1 0 Reset Value SFR D1h LSB 00h Both the MSC1201 and MSC1202 support 24-bit calibration values. OCL ADC Offset Calibration Register Low Byte. This is the low byte of the 24-bit word that contains the ADC offset bits 7−0 calibration. A value that is written to this location will set the ADC offset calibration value. ADC Offset Calibration Register Middle Byte (OCM) 7 6 5 4 3 2 1 0 Reset Value SFR D2h 00h Both the MSC1201 and MSC1202 support 24-bit calibration values. OCM ADC Offset Calibration Register Middle Byte. This is the middle byte of the 24-bit word that contains the ADC offset bits 7−0 calibration. A value that is written to this location will set the ADC offset calibration value. ADC Offset Calibration Register High Byte (OCH) 7 6 5 4 3 2 1 0 Reset Value SFR D3h MSB 00h Both the MSC1201 and MSC1202 support 24-bit calibration values. OCH ADC Offset Calibration Register High Byte. This is the high byte of the 24-bit word that contains the ADC offset bits 7−0 calibration. A value that is written to this location will set the ADC offset calibration value. ADC Gain Calibration Register Low Byte (GCL) 7 6 5 4 3 2 1 0 Reset Value SFR D4h LSB 5Ah Both the MSC1201 and MSC1202 support 24-bit calibration values. GCL ADC Gain Calibration Register Low Byte. This is the low byte of the 24-bit word that contains the ADC gain bits 7−0 calibration. A value that is written to this location will set the ADC gain calibration value. ADC Gain Calibration Register Middle Byte (GCM) 7 6 5 4 3 2 1 0 Reset Value SFR D5h ECh Both the MSC1201 and MSC1202 support 24-bit calibration values. GCM ADC Gain Calibration Register Middle Byte. This is the middle byte of the 24-bit word that contains the ADC gain bits 7−0 calibration. A value that is written to this location will set the ADC gain calibration value. ADC Gain Calibration Register High Byte (GCH) 7 6 5 4 3 2 1 0 Reset Value SFR D6h MSB 5Fh Both the MSC1201 and MSC1202 support 24-bit calibration values. GCH ADC Gain Calibration Register High Byte. This is the high byte of the 24-bit word that contains the ADC gain bits 7−0 calibration. A value that is written to this location will set the ADC gain calibration value.

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com ADC Input Multiplexer Register (ADMUX) 7 6 5 4 3 2 1 0 Reset Value SFR D7h INP3 INP2 INP1 INP0 INN3 INN2 INN1 INN0 01h INP3−0 Input Multiplexer Positive Input. This selects the positive signal input. bits 7−4 INP3 INP2 INP1 INP0 POSITIVE INPUT 0 0 0 0 AIN0 (default) 0 0 0 1 AIN1 0 0 1 0 AIN2 0 0 1 1 AIN3 0 1 0 0 AIN4 0 1 0 1 AIN5 0 1 1 0 REFIN− 0 1 1 1 REFIN− 1 0 0 0 AINCOM 1 1 1 1 Temperature Sensor (requires ADMUX = FFh) INN3−0 Input Multiplexer Negative Input. This selects the negative signal input. bits 3−0 INN3 INN2 INN1 INN0 NEGATIVE INPUT 0 0 0 0 AIN0 0 0 0 1 AIN1 (default) 0 0 1 0 AIN2 0 0 1 1 AIN3 0 1 0 0 AIN4 0 1 0 1 AIN5 0 1 1 0 REFIN− 0 1 1 1 REFIN− 1 0 0 0 AINCOM 1 1 1 1 Temperature Sensor (requires ADMUX = FFh)

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com Enable Interrupt Control (EICON) 7 6 5 4 3 2 1 0 Reset Value SFR D8h 0 1 EAI AI WDTI 0 0 0 40h EAI Enable Auxiliary Interrupt. The Auxiliary Interrupt accesses nine different interrupts which are masked and bit 5 identified by SFR registers PAI (SFR A5h), AIE (SFR A6h), and AISTAT (SFR A7h). 0 = Auxiliary Interrupt disabled (default). 1 = Auxiliary Interrupt enabled. AI Auxiliary Interrupt Flag. AI must be cleared by software before exiting the interrupt service routine, after the source bit 4 of the interrupt is cleared. Otherwise, the interrupt occurs again. Setting AI in software generates an Auxiliary Interrupt, if enabled. 0 = No Auxiliary Interrupt detected (default). 1 = Auxiliary Interrupt detected. WDTI Watchdog T imer Interrupt Flag. WDTI must be cleared by software before exiting the interrupt service routine. bit 3 Otherwise, the interrupt occurs again. Setting WDTI in software generates a watchdog time interrupt, if enabled. The Watchdog timer can generate an interrupt or reset. The interrupt is available only if the reset action is disabled in HCR0. 0 = No Watchdog Timer Interrupt Detected (default). 1 = Watchdog Timer Interrupt Detected. ADC Results Register Low Byte (ADRESL) 7 6 5 4 3 2 1 0 Reset Value SFR D9h LSB 00h ADRESL The ADC Results Low Byte. This is the low byte of the ADC results. bits 7−0 Reading from this register clears the ADC interrupt; however, AI in EICON (SFR D8) must also be cleared. ADC Results Register Middle Byte (ADRESM) 7 6 5 4 3 2 1 0 Reset Value SFR DAh 00h ADRESM The ADC Results Middle Byte. This is the middle byte of the ADC results for the MSC1201 and the most significant byte for the MSC1202. bits 7−0 ADC Results Register High Byte (ADRESH) 7 6 5 4 3 2 1 0 Reset Value SFR DBh MSB 00h ADRESH The ADC Results High Byte. This is the high byte and most significant byte of the ADC results for the MSC1201. bits 7−0 This is a sign-extended (Bipolar mode) or zero-padded (Unipolar mode) byte for the MSC1202 (that is, all 0s for positive ADC or unipolar results and all 1s for negative ADC results).

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com ADC Control Register 0 (ADCON0) 7 6 5 4 3 2 1 0 Reset Value SFR DCh — BOD EVREF VREFH EBUF PGA2 PGA1 PGA0 30h BOD Burnout Detect. When enabled, this connects a positive current source to the positive channel and a negative bit 6 current source to the negative channel. If the channel is open circuit, then the ADC results will be full-scale (buffer must be enabled). 0 = Burnout Current Sources Off (default). 1 = Burnout Current Sources On. EVREF Enable Internal Voltage Reference. If an external voltage is used, the internal voltage reference should be disabled. bit 5 0 = Internal Voltage Reference Off for external reference. 1 = Internal Voltage Reference On (default). Note that REFIN− must be connected to AGND. VREFH Voltage Reference High Select. The internal voltage reference can be selected to be 2.5V or 1.25V. bit 4 0 = REFOUT/REF IN+ is 1.25V. 1 = REFOUT/REF IN+ is 2.5V (default). EBUF Enable Buffer. Enables the input buffer to provide higher input impedance but limits the input voltage range and bit 3 dissipates more power. 0 = Buffer disabled (default). 1 = Buffer enabled. Input signal limited to AV DD − 1.5V. PGA2−0 Programmable Gain Amplifier. Sets the gain for the PGA from 1 to 128. bits 2−0 PGA2 PGA1 PGA0 GAIN 0 0 0 1 (default) 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com ADC Control Register 1 (ADCON1) 7 6 5 4 3 2 1 0 Reset Value SFR DDh OF_UF POL SM1 SM0 — CAL2 CAL1 CAL0 00h OF_UF Overflow/Underflow. If this bit is set, the data in the Summation register is invalid; either an overflow or underflow bit 6 occurred. This bit is cleared by writing a ‘0’ to it. POL Polarity. Polarity of the ADC result and Summation register. bit 6 0 = Bipolar. 1 = Unipolar. DIGITAL OUTPUT POL ANALOG INPUT MSC1201 MSC1202 (1) +FSR 0x7FFFFF 0x7FFF

0 ZERO 0x000000 0x0000 0

−FSR 0x800000 0x8000 +FSR 0xFFFFFF 0xFFFF

1 ZERO 0x000000 0x00001

−FSR 0x000000 0x0000 (1)The MSC1202 ADC result is sign-extended into ADRESH. SM1−0 Settling Mode. Selects the type of filter or auto select which defines the digital filter settling characteristics. bits 5−4 SM1 SM0 SETTLING MODE 0 0 Auto 0 1 Fast Settling Filter 1 0 Sinc2 Filter 1 1 Sinc3 Filter CAL2−0 Calibration Mode Control Bits. Writing to this register initiates calibration. bits 2−0 CAL2 CAL1 CAL0 CALIBRATION MODE 0 0 0 No Calibration (default) 0 0 1 Self-Calibration, Offset and Gain 0 1 0 Self-Calibration, Offset only 0 1 1 Self-Calibration, Gain only 1 0 0 System Calibration, Offset only (requires external connection) 1 0 1 System Calibration, Gain only (requires external connection) 1 1 0 Reserved 1 1 1 Reserved NOTE : Read value—000B.

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com ADC Control Register 2 (ADCON2) 7 6 5 4 3 2 1 0 Reset Value SFR DEh DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 1Bh DR7−0 Decimation Ratio LSB (refer to ADCON3, SFR DFh). bits 7−0 ADC Control Register 3 (ADCON3) 7 6 5 4 3 2 1 0 Reset Value SFR DFh — — — — — DR10 DR9 DR8 06h DR10−8 Decimation Ratio Most Significant 3 Bits. bits 2−0 The ADC output data rate is: fMOD Decimation Ratiowhere fMOD /C0043 fCLK /C0040ACLK /C00411/C0041/C006464 Accumulator (A or ACC) 7 6 5 4 3 2 1 0 Reset Value ACC.7−0 Accumulator. This register serves as the accumulator for arithmetic and logic operations. bits 7−0

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com Summation/Shifter Control (SSCON) 7 6 5 4 3 2 1 0 Reset Value SFR E1h SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 00h The Summation register is powered down when the ADC is powered down. If all zeroes are written to this register the 32-bit SUMR3−0 registers will be cleared. The Summation registers will do sign extend if Bipolar Mode is selected in ADCON1. SSCON1−0 Summation/Shift Count. bits 7−6 SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 DESCRIPTION 0 0 0 0 0 0 0 0 Clear Summation Register 0 0 0 1 0 0 0 0 CPU Summation on Write to SUMR0 (sum count/shift ignored) 0 0 1 0 0 0 0 0 CPU Subtraction on Write to SUMR0 (sum count/shift ignored) 1 0 x x x Note (1) Note (1) Note (1) CPU Shift only 0 1 Note (1) Note (1) Note (1) x x x ADC Summation only 1 1 Note (1) Note (1) Note (1) Note (1) Note (1) Note (1) ADC Summation completes then shift completes (1)Refer to register bit definition. SCNT2−0 Summation Count. When the summation is complete an interrupt will be generated unless masked. Reading the bits 5−3 SUMR0 register clears the interrupt. SCNT2 SCNT1 SCNT0 SUMMATION COUNT 0 0 0 2 0 0 1 4 0 1 0 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 256 SHF2−0 Shift Count. bits 2−0 SHF2 SHF1 SHF0 SHIFT DIVIDE 0 0 0 1 2 0 0 1 2 4 0 1 0 3 8 0 1 1 4 16 1 0 0 5 32 1 0 1 6 64 1 1 0 7 128 1 1 1 8 256

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com Summation Register 0 (SUMR0) 7 6 5 4 3 2 1 0 Reset Value SFR E2h LSB 00h SUMR0 Summation Register 0. This is the least significant byte of the 32-bit summation register or bits 0 to 7. bits 7−0 Write: Will cause values in SUMR3−0 to be added to the summation register. Read: Will clear the Summation Interrupt. Summation Register 1 (SUMR1) 7 6 5 4 3 2 1 0 Reset Value SFR E3h 00h SUMR1 Summation Register 1. This is the most significant byte of the lowest 16 bits of the summation register or bits 8−15. bits 7−0 Summation Register 2 (SUMR2) 7 6 5 4 3 2 1 0 Reset Value SFR E4h 00h SUMR2 Summation Register 2. This is the most significant byte of the lowest 24 bits of the summation register or bits 16−23. bits 7−0 Summation Register 3 (SUMR3) 7 6 5 4 3 2 1 0 Reset Value SFR E5h MSB 00h SUMR3 Summation Register 3. This is the most significant byte of the 32-bit summation register or bits 24−31. bits 7−0 Offset DAC Register (ODAC) 7 6 5 4 3 2 1 0 Reset Value SFR E6h 00h ODAC Offset DAC Register. This register will shift the input by up to half of the ADC full-scale input range. The Offset DAC bits 7−0 value is summed into the ADC prior to conversion. Writing 00h or 80h to ODAC turns off the Offset DAC. bit 7 Offset DAC Sign Bit. 0 = Positive 1 = Negative bit 6−0 Offset /C0043/C0042V REF 2 /C0064PGA /C0064/C0466ODAC [6 : 0] 127 /C0467/C0064(/C00421)bit7

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com Low Voltage Detect Control (LVDCON) 7 6 5 4 3 2 1 0 Reset Value SFR E7h ALVDIS 0 0 0 1 1 1 1 8Fh ALVDIS Analog Low Voltage Detect Disable. bit 7 0 = Enable Detection of Low Analog Supply Voltage (ALVD flag and interrupt are set when AVDD < 2.8V). 1 = Disable Detection of Low Analog Supply Voltage. Extended Interrupt Enable (EIE) 7 6 5 4 3 2 1 0 Reset Value SFR E8h 1 1 1 EWDI EX5 EX4 EX3 EX2 E0h EWDI Enable Watchdog Interrupt. This bit enables/disables the watchdog interrupt. The Watchdog timer is enabled by bit 4 the WDTCON (SFR FFh) and PDCON (SFR F1h) registers. 0 = Disable the Watchdog Interrupt 1 = Enable Interrupt Request Generated by the Watchdog Timer EX5 External Interrupt 5 Enable. This bit enables/disables external interrupt 5. bit 3 0 = Disable External Interrupt 5 1 = Enable External Interrupt 5 EX4 External Interrupt 4 Enable. This bit enables/disables external interrupt 4. bit 2 0 = Disable External Interrupt 4 1 = Enable External Interrupt 4 EX3 External Interrupt 3 Enable. This bit enables/disables external interrupt 3. bit 1 0 = Disable External Interrupt 3 1 = Enable External Interrupt 3 EX2 External Interrupt 2 Enable. This bit enables/disables external interrupt 2. bit 0 0 = Disable External Interrupt 2 1 = Enable External Interrupt 2 Hardware Product Code Register 0 (HWPC0) (read-only) 7 6 5 4 3 2 1 0 Reset Value SFR E9h 0 0 0 0 0 0 DEVICE MEMORY 0000_00xxb HWPC0.7−0 Hardware Product Code LSB. Read-only. bits 7−0 DEVICE MEMORY MODEL FLASH MEMORY 0 0 MSC1201Y2 4kB 0 1 MSC1201Y3 8kB 1 0 MSC1202Y2 4kB 1 1 MSC1202Y3 8kB Hardware Product Code Register 1 (HWPC1) (read-only) 7 6 5 4 3 2 1 0 Reset Value SFR EAh 0 0 1 0 0 0 0 0 20h HWPC1.7−0 Hardware Product Code MSB. Read-only. bits 7−0

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com Hardware Version Register (HWVER) 7 6 5 4 3 2 1 0 Reset Value SFR EBh Flash Memory Control (FMCON) 7 6 5 4 3 2 1 0 Reset Value SFR EEh 0 PGERA 0 FRCM 0 BUSY 1 0 02h PGERA Page Erase. Available in both user and program modes. bit 6 0 = Disable Page Erase Mode 1 = Enable Page Erase Mode FRCM Frequency Control Mode. The bypass is only used for slow clocks to save power. bit 4 0 = Bypass (default) 1 = Use Delay Line. Saves power (recommended). BUSY Write/Erase BUSY Signal. bit 2 0 = Idle or Available 1 = Busy Flash Memory Timing Control Register (FTCON) 7 6 5 4 3 2 1 0 Reset Value SFR EFh FER3 FER2 FER1 FER0 FWR3 FWR2 FWR1 FWR0 A5h Refer to Flash Timing Characteristics FER3−0 Set Erase. Flash Erase Time = (1 + FER) • (MSEC + 1) • tCLK . bits 7−4 11ms industrial temperature range. 5ms commercial temperature range. FWR3−0 Set Write. Set Flash Write Time = (1 + FWR) • (USEC + 1) • 5 • tCLK . bits 3−0 30 µs to 40µs. B Register (B) 7 6 5 4 3 2 1 0 Reset Value SFR F0h 00h B.7−0 B Register. This register serves as a second accumulator for certain arithmetic operations. bits 7−0

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com Power-Down Control Register (PDCON) 7 6 5 4 3 2 1 0 Reset Value SFR F1h PDICLK PDIDAC PDI2C 0 PDADC PDWDT PDST PDSPI 6Fh Turning peripheral modules off puts the MSC1201/02 in the lowest power mode. PDICLK Internal Clock Control. bit 6 0 = Internal Oscillator and PLL On (Internal Oscillator or PLL mode) 1 = Internal Oscillator and PLL Power Down (External Clock mode) PDIDAC IDAC Control. bit 6 0 = IDAC On 1 = IDAC Power Down (default) PDI2C I2C Control. bit 5 0 = I 2C On (only when PDSPI = 1) 1 = I2C Power Down (default) PDADC ADC Control. bit 3 0 = ADC On 1 = ADC, VREF , and Summation registers are powered down (default). PDWDT Watchdog Timer Control. bit 2 0 = W atchdog Timer On 1 = Watchdog Timer Power Down (default) PDST System Timer Control. bit 1 0 = System Timer On 1 = System Timer Power Down (default) PDSPI SPI System Control. bit 0 0 = SPI System On 1 = SPI System Power Down (default)

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com PSEN /ALE Select (PASEL) 7 6 5 4 3 2 1 0 Reset Value SFR F2h PSEN4 PSEN3 PSEN2 PSEN1 PSEN0 0 0 0 00h PSEN2−0 PSEN Mode Select. Defines the output on P3.6 in User Application mode or Serial Flash Programming mode. bits 7−3 00000: General-purpose I/O (default) 00001: SYSCLK 00011: Internal PSEN (refer to Figure 5 for timing) 00101: Internal ALE (refer to Figure 5 for timing) 00111: f OSC (buffered XIN oscillator clock) 01001: Memory WR (MOVX write) 01011: T0 Out (overflow)(1) 01101: T1 Out (overflow)(1) 01111: fMOD (2) 10001: SYSCLK/2 (toggles on rising edge)(2) 10011: Internal PSEN/2(2) 10101: Internal ALE/2(2) 10111: fOSC (2) 11001: Memory WR/2 (MOVX write)(2) 11011: T0 Out/2 (overflow)(2) 11101: T1 Out/2 (overflow)(2) 11111: fMOD /2(2) (1)One period of these signals equal to tCLK . (2)Duty cycle is 50%. Phase Lock Loop Low Register (PLLL) 7 6 5 4 3 2 1 0 Reset Value SFR F4h PLL7 PLL6 PLL5 PLL4 PLL3 PLL2 PLL1 PLL0 xxh PLL7−0 PLL Counter V alue Least Significant Bit. bits 7−0 PLL Frequency = External Crystal Frequency • PLL9:0.

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com Phase Lock Loop High Register (PLLH) 7 6 5 4 3 2 1 0 Reset Value SFR F5h CLKSTAT2 CLKSTAT1 CLKSTAT0 PLLLOCK 0 0 PLL9 PLL8 xxh CLKSTAT2−0 Active Clock Status (read-only). Derived from HCR2 setting; refer to Table 3. bits 7−5 000: Reserved 001: Reserved 010: Reserved 011: External Clock Mode 100: PLL High-Frequency (HF) Mode (must read PLLLOCK to determine active clock status) 101: PLL Low-Frequency (LF) Mode (must read PLLLOCK to determine active clock status) 110: Internal Oscillator High-Frequency (HF) Mode 111: Internal Oscillator Low-Frequency (LF) Mode PLLLOCK PLL Lock Status and Status Enable. bit 4 For Write (PLL Lock Status Enable): 0 = No Effect 1 = Enable PLL Lock Detection (must wait 20ms before PLLLOCK read status is valid). For Read (PLL Lock Status): 0 = PLL Not Locked (PLL may be inactive; refer to Table 3 for active clock mode) 1 = PLL Locked (PLL is active clock). PLL9−8 PLL Counter Value Most Significant 2 Bits (refer to PLLL, SFR F4h). bits 1−0 Analog Clock (ACLK) 7 6 5 4 3 2 1 0 Reset Value SFR F6h 0 FREQ6 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03h FREQ6−0 Clock Frequency − 1. This value + 1 divides the system clock to create the ADC clock. bits 6−0 fACLK /C0043 fCLK ACLK /C00411 , where fCLK /C0043 fOSC SYSCLK divider fMOD /C0043 fACLK ADC Data Rate/C0043fDATA /C0043 fMOD Decimation Ratio System Reset Register (SRST) 7 6 5 4 3 2 1 0 Reset Value SFR F7h 0 0 0 0 0 0 0 RSTREQ 00h RSTREQ Reset Request. Setting this bit to 1 and then clearing to 0 will generate a system reset. bit 0

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com Extended Interrupt Priority (EIP) 7 6 5 4 3 2 1 0 Reset Value SFR F8h 1 1 1 PWDI PX5 PX4 PX3 PX2 E0h PWDI Watchdog Interrupt Priority. This bit controls the priority of the watchdog interrupt. bit 4 0 = The watchdog interrupt is low priority. 1 = The watchdog interrupt is high priority. PX5 External Interrupt 5 Priority. This bit controls the priority of external interrupt 5. bit 3 0 = External interrupt 5 is low priority. 1 = External interrupt 5 is high priority. PX4 External Interrupt 4 Priority. This bit controls the priority of external interrupt 4. bit 2 0 = External interrupt 4 is low priority. 1 = External interrupt 4 is high priority. PX3 External Interrupt 3 Priority. This bit controls the priority of external interrupt 3. bit 1 0 = External interrupt 3 is low priority. 1 = External interrupt 3 is high priority. PX2 External Interrupt 2 Priority. This bit controls the priority of external interrupt 2. bit 0 0 = External interrupt 2 is low priority. 1 = External interrupt 2 is high priority. Seconds Timer Interrupt (SECINT) 7 6 5 4 3 2 1 0 Reset Value SFR F9h WRT SECINT6 SECINT5 SECINT4 SECINT3 SECINT2 SECINT1 SECINT0 7Fh This system clock is divided by the value of the 16-bit register MSECH:MSECL. Then, that 1ms timer tick is divided by the register HMSEC which provides the 100ms signal used by this seconds timer. Therefore, this seconds timer can generate an interrupt which occurs from 100ms to 12.8 seconds. Reading this register will clear the Seconds Interrupt. This Interrupt can be monitored in the AIE register. WRT Write Control. Determines whether to write the value immediately or wait until the current count is finished. bit 7 Read = 0. 0 = Delay Write Operation. The SEC value is loaded when the current count expires. 1 = Write Immediately. The counter is loaded once the CPU completes the write operation. SECINT6−0 Seconds Count. Normal operation would use 100ms as the clock interval. bits 6−0 Seconds Interrupt = (1 + SEC) • (HMSEC + 1) • (MSEC + 1) • t CLK .

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com Milliseconds Interrupt (MSINT) 7 6 5 4 3 2 1 0 Reset Value SFR FAh WRT MSINT6 MSINT5 MSINT4 MSINT3 MSINT2 MSINT1 MSINT0 7Fh The clock used for this timer is the 1ms clock which results from dividing the system clock by the values in registers MSECH:MSECL. Reading this register is necessary for clearing the interrupt; however, AI in EICON (SFR D8h) must also be cleared. WRT Write Control. Determines whether to write the value immediately or wait until the current count is finished. bit 7 Read = 0. 0 = Delay Write Operation. The MSINT value is loaded when the current count expires. 1 = Write Immediately. The MSINT counter is loaded once the CPU completes the write operation. MSINT6−0 Milliseconds Count. Normal operation would use 1ms as the clock interval. bits 6−0 MS Interrupt Interval = (1 + MSINT) • (MSEC + 1) • t CLK One Microsecond Register (USEC) 7 6 5 4 3 2 1 0 Reset Value SFR FBh 0 0 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03h FREQ5−0 Clock Frequency − 1. This value + 1 divides the system clock to create a 1µs Clock. bits 5−0 USEC = CLK/(FREQ + 1). This clock is used to set Flash write time. See FTCON (SFR EFh). One Millisecond Low Register (MSECL) 7 6 5 4 3 2 1 0 Reset Value SFR FCh MSECL7 MSECL6 MSECL5 MSECL4 MSECL3 MSECL2 MSECL1 MSECL0 9Fh MSECL7−0 One Millisecond Low. This value in combination with the next register is used to create a 1ms clock. bits 7−0 1ms = (MSECH • 256 + MSECL + 1) • tCLK . This clock is used to set Flash erase time. See FTCON (SFR EFh). One Millisecond High Register (MSECH) 7 6 5 4 3 2 1 0 Reset Value SFR FDh MSECH7 MSECH6 MSECH5 MSECH4 MSECH3 MSECH2 MSECH1 MSECH0 0Fh MSECH7−0 One Millisecond High. This value in combination with the previous register is used to create a 1ms clock. bits 7−0 1ms = (MSECH • 256 + MSECL + 1) • tCLK . One Hundred Millisecond Register (HMSEC) 7 6 5 4 3 2 1 0 Reset Value SFR FEh HMSEC7 HMSEC6 HMSEC5 HMSEC4 HMSEC3 HMSEC2 HMSEC1 HMSEC0 63h WRT Write Control. Determines whether to write the value immediately or wait until the current count is finished. Read = 0. HMSEC7−0 One Hundred Millisecond. This clock divides the 1ms clock to create a 100ms clock. bits 7−0 100ms = (MSECH • 256 + MSECL + 1) • (HMSEC + 1) • tCLK .

/C0077/C0083/C0067/C0049/C0050/C0048/C0049 /C0077/C0083/C0067/C0049/C0050/C0048/C0050 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com Watchdog Timer Register (WDTCON) 7 6 5 4 3 2 1 0 Reset Value SFR FFh EWDT DWDT RWDT WDCNT4 WDCNT3 WDCNT2 WDCNT1 WDCNT0 00h EWDT Enable Watchdog (R/W). bit 7 Write 1/Write 0 sequence sets the Watchdog Enable Counting bit. DWDT Disable Watchdog (R/W). bit 6 Write 1/Write 0 sequence clears the Watchdog Enable Counting bit. RWDT Reset Watchdog (R/W). bit 5 Write 1/Write 0 sequence restarts the Watchdog Counter. WDCNT4−0 Watchdog Count (R/W). bits 4−0 Watchdog expires in (WDCNT + 1) • HMSEC to (WDCNT + 2) • HMSEC, if the sequence is not asserted. There is an uncertainty of 1 count. NOTE: If HCR0.3 (EWDR) is set and the watchdog timer expires, a system reset is generated. If HCR0.3 (EWDR) is cleared and the watchdog timer expires, an interrupt is generated (see Table 7).

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) MSC1201Y2RHHR ACTIVE QFN RHH 36 2500 TBD CU SNPB Level-1-235C-UNLIM MSC1201Y2RHHT ACTIVE QFN RHH 36 250 TBD CU SNPB Level-1-235C-UNLIM MSC1201Y3RHHR ACTIVE QFN RHH 36 2500 TBD CU SNPB Level-1-235C-UNLIM MSC1201Y3RHHT ACTIVE QFN RHH 36 250 TBD CU SNPB Level-1-235C-UNLIM MSC1202Y2RHHR ACTIVE QFN RHH 36 2500 TBD CU SNPB Level-1-235C-UNLIM MSC1202Y2RHHT ACTIVE QFN RHH 36 250 TBD CU SNPB Level-1-235C-UNLIM MSC1202Y3RHHR ACTIVE QFN RHH 36 2500 TBD CU SNPB Level-1-235C-UNLIM MSC1202Y3RHHT ACTIVE QFN RHH 36 250 TBD CU SNPB Level-1-235C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 19-May-2005 Addendum-Page 1

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright  2005, Texas Instruments Incorporated

Product Information

MSC1202Y3RHHT specifications and overview.

Summary

Precision, Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with 8051 Microcontroller and Flash Memory

Description

Precision, Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with 8051 Microcontroller and Flash Memory

Source title MSC1202Y3RHHT Datasheet(PDF) - Burr-Brown (TI)

Related Parts

More parts from the same family.

Browse manufacturer