MSC1200Y2

MSC1200 TI | Alldatasheet

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SBAS289E – JUNE 2003 – REVISED NOVEMBER 2004 www.ti.com Copyright © 2003-2004, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Precision Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with 8051 Microcontroller and Flash Memory

FEATURES

G 24-BITS NO MISSING CODES G 22-BITS EFFECTIVE RESOLUTION AT 10Hz Low Noise: 75nV G PGA FROM 1 TO 128 G PRECISION ON-CHIP VOLTAGE REFERENCE G 8 DIFFERENTIAL/SINGLE-ENDED CHANNELS G ON-CHIP OFFSET/GAIN CALIBRATION G OFFSET DRIFT: 0.02ppm/°C G GAIN DRIFT: 0.5ppm/°C G ON-CHIP TEMPERATURE SENSOR G SELECTABLE BUFFER INPUT G BURNOUT DETECT G 8-BIT CURRENT DAC DIGITAL FEATURES Microcontroller Core G 8051-COMPATIBLE G HIGH-SPEED CORE:

4 Clocks per Instruction Cycle

G PLL WITH 32kHz CAPABILITY G SINGLE INSTRUCTION 121ns G DUAL DATA POINTER Memory G 4kB OR 8kB OF FLASH MEMORY G FLASH MEMORY PARTITIONING G ENDURANCE 1M ERASE/WRITE CYCLES,

100 YEAR DATA RETENTION

G IN-SYSTEM SERIALLY PROGRAMMABLE G FLASH MEMORY SECURITY G 1kB BOOT ROM Peripheral Features G 16 DIGITAL I/O PINS G ADDITIONAL 32-BIT ACCUMULATOR G TWO 16-BIT TIMER/COUNTERS G SYSTEM TI MERS G PROGRAMMABLE WATCHDOG TIMER G FULL DUPLEX USART G BASIC SPI™ G BASIC I2C ™ G POWER MANAGEMENT CONTROL G INTERNAL CLOCK DIVIDER G IDLE MODE CURRENT < 200 µA G STOP MODE CURRENT < 100nA G DIGITAL BROWNOUT RESET G ANALOG LOW VOLTAGE DETECT G 20 INTERRUPT SOURCES GENERAL FEATURES G PACKAGE: TQFP-48 G LOW POWER: 3mW G INDUSTRIAL TEMPERATURE RANGE: –40°C to +85°C G POWER SUPPLY: 2.7V to 5.25V

APPLICATIONS

G INDUSTRIAL PROCESS CONTROL G INSTRUMENTATION G LIQUID/GAS CHROMATOGRAPHY G BLOOD ANALYSIS G SMART TRANSMITTERS G PORTABLE INSTRUMENTS G WEIGH SCALES G PRESSURE TRANSDUCERS G INTELLIGENT SENSORS G PORTABLE APPLICATIONS G DAS SYSTEMS PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

SBAS289Ewww.ti.com PACKAGE/ORDERING INFORMATION (1) SPECIFIED FLASH PACKAGE TEMPERATURE PACKAGE PRODUCT MEMORY PACKAGE-LEAD DESIGNATOR RANGE MARKING MSC1200Y2 4k TQFP-48 PFB –40 °C to +85°C MSC1200Y2 MSC1200Y2 4k "" " " MSC1200Y3 8k TQFP-48 PFB –40 °C to +85°C MSC1200Y3 MSC1200Y3 8k "" " " NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or refer to our web site at www.ti.com/msc. ABSOLUTE MAXIMUM RATINGS (1) Analog Inputs DD + 0.3V Power Supply V Thermal Resistance, Junction-to-Ambient Digital Outputs NOTE: (1) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute-maximum- rated conditions for extended periods may affect device reliability. FEATURES (1) MSC1200Y2 (2) MSC1200Y3 (2) Flash Program Memory (Bytes) Up to 4k Up to 8k Flash Data Memory (Bytes) Up to 2k Up to 4k Internal Scratchpad RAM (Bytes) 128 128 NOTES: (1) All peripheral features are the same on all devices; the flash memory size is the only difference. (2) The last digit of the part number (N) represents the onboard flash size = (2 N )kBytes. MSC1200Yx FAMILY FEATURES ELECTRICAL CHARACTERISTICS: AV DD = 5V All specifications from TMIN to TMAX , DVDD = +2.7V to 5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise noted. MSC1200Yx PARAMETER CONDITION MIN TYP MAX UNITS ANALOG INPUT (AIN0-AIN7, AINCOM) Analog Input Range Buffer OFF AGND – 0.1 AV DD + 0.1 V Buffer ON AGND + 50mV AV DD – 1.5 V Full-Scale Input Voltage Range (In+) – (In–) ±VREF /PGA V Differential Input Impedance Buffer OFF 7/PGA M Ω Input Current Buffer ON 0.5 nA Bandwidth Fast Settling Filter –3dB 0.469 • f DATA Sinc2 Filter –3dB 0.318 • fDATA Sinc3 Filter –3dB 0.262 • fDATA Programmable Gain Amplifier User-Selectable Gain Ranges 1 128 Input Capacitance Buffer ON 7 pF Input Leakage Current Multiplexer Channel Off, T = +25 °C 0.5 pA Burnout Current Sources Buffer ON ±2 µA ADC OFFSET DAC Offset DAC Range ±VREF /(2 • PGA) V Offset DAC Monotonicity 8 Bits Offset DAC Gain Error ±1.0 % of Range Offset DAC Gain Error Drift 0.6 ppm/ °C ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instru- ments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

SBAS289E www.ti.com SYSTEM PERFORMANCE Resolution 24 Bits ENOB 22 Bits Output Noise See Typical Characteristics No Missing Codes Sinc 3 Filter 24 Bits Integral Nonlinearity End Point Fit, Differential Input ±0.0004 ±0.0015 %FSR Offset Error After Calibration 1.5 ppm of FS Offset Drift (1) Before Calibration 0.02 ppm of FS/ °C Gain Error(2) After Calibration 0.005 % Gain Error Drift(1) Before Calibration 0.5 ppm/ °C System Gain Calibration Range 80 120 % of FS System Offset Calibration Range –50 50 % of FS Common-Mode Rejection At DC 100 120 dB fCM = 60Hz, fDATA = 10Hz 130 dB fCM = 50Hz, fDATA = 50Hz 120 dB fCM = 60Hz, fDATA = 60Hz 120 dB Normal Mode Rejection f SIG = 50Hz, fDATA = 50Hz 100 dB fSIG = 60Hz, fDATA = 60Hz 100 dB Power-Supply Rejection At DC, dB = –20log(∆VOUT /∆VDD )(3) 100 dB VOLTAGE REFERENCE INPUTS Reference Input Range REF IN+, REF IN – AGND AV DD (2) V VREF VREF ≡ (REF IN+) – (REF IN–) 0.3 2.5 AV DD V Common-Mode Rejection At DC 115 dB Input Current V REF = 2.5V, PGA = 1 1 µA ON-CHIP VOLTAGE REFERENCE Output Voltage VREFH = 1 at +25 °C 2.5 V VREFH = 0 1.25 V Short-Circuit Current Source 9m A Short-Circuit Current Sink 10 mA Short-Circuit Duration Sink or Source Indefinite Startup Time from Power ON 0.4 ms Temperature Sensor Temperature Sensor Voltage T = +25 °C1 1 5 m V Temperature Sensor Coefficient 375 µV/°C IDAC OUTPUT CHARACTERISTICS Full-Scale Output Current 1m A Maximum Short-Circuit Current Duration Indefinite Compliance Voltage AV DD – 1.5 V ANALOG POWER-SUPPLY REQUIREMENTS Power-Supply Voltage AV DD 4.75 5.0 5.25 V Analog Current A nalog OFF, ALVD OFF, PDADC = PDIDAC = 1 < 1 nA ADC Current I ADC PGA = 1, Buffer OFF 170 µA PGA = 128, Buffer OFF 430 µA PGA = 1, Buffer ON 230 µA PGA = 128, Buffer ON 770 µA VREF Supply Current I VREF ADC ON 360 µA IDAC Supply Current I IDAC IDAC = 00H 230 µA NOTES: (1) Calibration can minimize these errors. (2) The gain calibration cannot have a REF IN+ of more than AVDD – 1.5V with buffer ON. To calibrate gain, turn buffer off. (3) DVOUT is change in digital result. ELECTRICAL CHARACTERISTICS: AV DD = 5V (Cont.) All specifications from TMIN to TMAX , DVDD = +2.7V to 5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise noted. MSC1200Yx PARAMETER CONDITION MIN TYP MAX UNITS

SBAS289Ewww.ti.com ELECTRICAL CHARACTERISTICS: AV DD = 3V All specifications from TMIN to TMAX , AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and VREF ≡ (REF IN+) – (REF IN–) = +1.25V, unless otherwise noted. MSC1200Yx PARAMETER CONDITION MIN TYP MAX UNITS ANALOG INPUT (AIN0-AIN7, AINCOM) Analog Input Range Buffer OFF AGND – 0.1 AV DD + 0.1 V Buffer ON AGND + 50mV AV DD – 1.5 V Full-Scale Input Voltage Range (In+) – (In–) ±VREF /PGA V Differential Input Impedance Buffer OFF 7/PGA M Ω Input Current Buffer ON 0.5 nA Bandwidth Fast Settling Filter –3dB 0.469 • f DATA Sinc2 Filter –3dB 0.318 • fDATA Sinc3 Filter –3dB 0.262 • fDATA Programmable Gain Amplifier User-Selectable Gain Ranges 1 128 Input Capacitance Buffer On 7 pF Input Leakage Current Multiplexer Channel Off, T = +25 °C 0.5 pA Burnout Current Sources Buffer ON ±2 µA ADC OFFSET DAC Offset DAC Range ±VREF /(2 • PGA) V Offset DAC Monotonicity 8 Bits Offset DAC Gain Error ±1.5 % of Range Offset DAC Gain Error Drift 0.6 ppm/ °C SYSTEM PERFORMANCE Resolution 24 Bits ENOB 22 Bits Output Noise See Typical Characteristics No Missing Codes Sinc 3 Filter 24 Bits Integral Nonlinearity End Point Fit, Differential Input ±0.0004 ±0.0015 %FSR Offset Error After Calibration 1.3 ppm of FS Offset Drift (1) Before Calibration 0.02 ppm of FS/ °C Gain Error(2) After Calibration 0.005 % Gain Error Drift(1) Before Calibration 0.5 ppm/ °C System Gain Calibration Range 80 120 % of FS System Offset Calibration Range –50 50 % of FS Common-Mode Rejection At DC 100 130 dB fCM = 60Hz, fDATA = 10Hz 130 dB fCM = 50Hz, fDATA = 50Hz 120 dB fCM = 60Hz, fDATA = 60Hz 120 dB Normal Mode Rejection f SIG = 50Hz, fDATA = 50Hz 100 dB fSIG = 60Hz, fDATA = 60Hz 100 dB Power-Supply Rejection At DC, dB = –20log(DVOUT /DVDD )(3) 88 dB VOLTAGE REFERENCE INPUTS Reference Input Range REF IN+, REF IN – AGND AV DD (2) V VREF VREF ≡ (REF IN+) – (REF IN–) 0.3 1.25 AV DD V Common-Mode Rejection At DC 110 dB Input Current V REF = 1.25V, PGA = 1 0.5 µA ON-CHIP VOLTAGE REFERENCE Output Voltage VREFH = 0 at +25 °C 1.25 V Short-Circuit Current Source 4m A Short-Circuit Current Sink 5 µA Short-Circuit Duration Sink or Source Indefinite Startup Time from Power ON 0.2 ms Temperature Sensor Temperature Sensor Voltage T = +25 °C 115 mV Temperature Sensor Coefficient 375 µV/°C IDAC OUTPUT CHARACTERISTICS Full-Scale Output Current 1m A Maximum Short-Circuit Current Duration Indefinite Compliance Voltage AV DD – 1.5 V POWER-SUPPLY REQUIREMENTS Power-Supply Voltage AV DD 2.7 3.0 3.6 V Analog Current A nalog OFF, ALVD OFF, PDADC = PDIDAC = 1 < 1 nA ADC Current I ADC PGA = 1, Buffer OFF 150 µA PGA = 128, Buffer OFF 380 µA PGA = 1, Buffer ON 200 µA PGA = 128, Buffer ON 610 µA VREF Supply Current I VREF ADC ON 330 µA IDAC Supply Current I IDAC IDAC = 00H 220 µA NOTES: (1) Calibration can minimize these errors. (2) The gain calibration cannot have a REF IN+ of more than AVDD – 1.5V with buffer ON. To calibrate gain, turn buffer off. (3) DVOUT is change in digital result.

SBAS289E www.ti.com DIGITAL CHARACTERISTICS: DV DD = 2.7V to 5.25V All specifications from TMIN to TMAX , unless otherwise specified. MSC1200Yx PARAMETER CONDITION MIN TYP MAX UNITS POWER-SUPPLY REQUIREMENTS Digital Supply Current DV DD 2.7 3.0 3.6 V Normal Mode, fOSC = 1MHz 0.6 mA Normal Mode, fOSC = 8MHz, All Peripherals ON 5 mA Internal Oscillator LF Mode (12.8MHz nominal) 7.1 mA Stop Mode, DBOR OFF 100 nA DV DD 4.75 5.0 5.25 V Normal Mode, fOSC = 1MHz 1.2 mA Normal Mode, fOSC = 8MHz, All Peripherals ON 9 mA Internal Oscillator LF Mode (12.8MHz nominal) 15 mA Internal Oscillator HF Mode (25.6MHz nominal) 29 mA Stop Mode, DBOR OFF 100 nA DIGITAL INPUT/OUTPUT (CMOS) Logic Level: VIH (except XIN pin) 0.6 • DVDD DV DD V VIL (except XIN pin) DGND 0.2 • DVDD V Ports 1 and 3, Input Leakage Current, Input Mode V IH = DVDD or VIH = 0V 0 µA Pin XIN Input Leakage Current 0 µA I/O Pin Hysteresis 700 mV VOL , Ports 1 and 3, All Output Modes I OL = 1mA DGND 0.4 V VOL , Ports 1 and 3, All Output Modes I OL = 30mA, 3V (20mA) 1.5 V VOH , Ports 1 and 3, Strong Drive Output I OH = 1mA DV DD – 0.4 DV DD – 0.1 DV DD V VOH , Ports 1 and 3, Strong Drive Output I OH = 30mA, 3V (20mA) DV DD – 1.5 V Ports 1 and 3 Pull-Up Resistors 11 k Ω FLASH MEMORY CHARACTERISTICS: DV DD = 2.7V to 5.25V tUSEC = 1µs, tMSEC = 1ms MSC1200Yx PARAMETER CONDITION MIN TYP MAX UNITS Flash Memory Endurance 100,000 1,000,000 cycles Flash Memory Data Retention 100 Years Mass and Page Erase Time Set with FER Value in FTCON 10 ms Flash Memory Write Time Set with FWR Value in FTCON 30 40 µs

SBAS289Ewww.ti.com 2.7V to 3.6V 4.75V to 5.25V SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNITS External Clock Mode fOSC (1) A External Crystal Frequency (f OSC )1 2 0 1 3 3 M H z 1/tOSC (1) A External Clock Frequency (f OSC )0 2 0 0 3 3 M H z fOSC (1) A External Ceramic Resonator Frequency (fOSC )1 1 2 1 1 2 M H z tHIGH A HIGH Time (2) 15 10 ns tLOW A LOW Time (2) 15 10 ns tR A Rise Time (2) 55 n s tF A Fall Time (2) 55 n s NOTES: (1) tCLK = 1/fOSC = one oscillator clock period for clock divider = 1. (2) These values are characterized but not 100% production tested. AC ELECTRICAL CHARACTERISTICS (1): DVDD = 2.7V to 5.25V FIGURE A. External Clock Drive CLK. FIGURE B. Serial Flash Programming Power-On Timing. SYMBOL FIGURE PARAMETER MIN MAX UNIT tRW B RST width 2 t OSC — ns tRRD B RST rise to P1.0 internal pull high — 5 µs tRFD B RST falling to CPU start — 18 ms tRS B Input signal to RST falling setup time t OSC — ns tRH B RST falling to P1.0 hold time 18 — ms NOTE: P1.0 is internally pulled-up with ~11kΩ during RST high. P1.0/PROG RST tRFD , tRHtRStRRD tRW tR tHIGH VIH VIH 0.8V 0.8V VIH VIH 0.8V 0.8VtLOW tOSC tF MSC1200Yx PARAMETER CONDITION MIN TYP MAX UNITS PHASE LOCK LOOP (PLL) Input Frequency Range External Crystal/Clock Frequency (f OSC ) 32.768 kHz PLL LF Mode PLLDIV = 449 (default) 14.7456 MHz PLL HF Mode PLLDIV = 899 (must be set by user) 29.4912 MHz PLL Lock Time Within 1% 2 ms INTERNAL OSCILLATOR (IO) See Typical Characteristics IO LF Mode 12.8 MHz IO HF Mode 25.6 MHz Internal Oscillator Settling Time Within 1% 1 ms NOTE: (1) Parameters are valid over operating temperature range, unless otherwise specified. EXTERNAL CLOCK DRIVE CLK TIMING SERIAL FLASH PROGRAMMING TIMING

SBAS289E www.ti.com PIN CONFIGURATION Top View TQFP DV DD DV DD DGND DGND P1.6/INT4 P1.5/INT3 P1.4/INT2/SS P1.3/DIN P1.2/DOUT P1.1 P1.0/PROG NC DGND NC DV DD P3.7 P3.6/SCK/SCL/CLKS P3.5/T1 P3.4/T0 P3.3/INT1 P3.2/INT0 P3.1/TxD0 P3.0/RxD0 P1.7/INT5 IDAC REFOUT/REFIN+ REFIN – NC AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 NC XIN XOUT DGND RST NC NC CAP AV DD AGND AGND AINCOM 48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 MSC1200

SBAS289Ewww.ti.com PIN # NAME DESCRIPTION 1,6,7,16,25,47 NC No Connection 2 XIN The crystal oscillator pin XIN supports parallel resonant AT cut fundamental frequency crystals and ceramic resonators. XIN can also be an input if there is an external clock source instead of a crystal. 3 XOUT The crystal oscillator pin XOUT supports parallel resonant AT cut fundamental frequency crystals and ceramic resonators. XOUT serves as the output of the crystal amplifier. 4, 33, 34, 48 DGND Digital Ground 5 RST A HIGH on the reset input for two t OSC periods will reset the device.

8 CAP Capacitor (220pF ceramic)

9A V DD Analog Power Supply 10, 11 AGND Analog Ground 12 AINCOM Analog Input (can be analog common for single-ended inputs or analog input for differential inputs)

13 IDAC IDAC Output

14 REFOUT/REF IN+ Internal Voltage Reference Output/Voltage Reference Positive Input

15 REF IN – Voltage Reference Negative Input (tie to AGND for internal voltage reference)

17 AIN7 Analog Input Channel 7

18 AIN6 Analog Input Channel 6

19 AIN5 Analog Input Channel 5

20 AIN4 Analog Input Channel 4

21 AIN3 Analog Input Channel 3

22 AIN2 Analog Input Channel 2

23 AIN1 Analog Input Channel 1

24 AIN0 Analog Input Channel 0

26-32, 37 P1.0-P1.7 Port 1 is a bidirectional I/O port (refer to P1DDRL, SFR AE H , and P1DDRH, SFR AFH , for port pin configuration control). Port 1— Alternate Functions: PIN DESCRIPTIONS 38-45 P3.0-P3.7 Port 3 is a bidirectional I/O port (refer to P3DDRL, SFR B3 H , and P3DDRH, SFR B4H , for port pin configuration control). Port 3— Alternate Functions: 35, 36, 46 DV DD Digital Power Supply PORT ALTERNATE MODE P3.0 RxD0 Serial Port 0 Input P3.1 TxD0 Serial Port 0 Output P3.2 INT0 External Interrupt 0 P3.3 INT1 External Interrupt 1 P3.4 T0 Timer 0 External Input P3.5 T1 Timer 1 External Input P3.6 SCK/SCL/CLKS SCK/SCL/Various Clocks (refer to PASEL, SFR F2 H ) P3.7 N/A PORT ALTERNATE MODE P1.0 PROG Serial Programming Mode P1.1 N/A P1.2 DOUT Serial Data Out P1.3 DIN Serial Data In P1.4 INT2/ SS External Interrupt 2/Slave Select P1.5 INT3 External Interrupt 3 P1.6 INT4 External Interrupt 4 P1.7 INT5 External Interrupt 5

SBAS289E www.ti.com TYPICAL CHARACTERISTICS AV DD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer ON, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified. EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO Decimation Ratio = f MOD fDATA 0 500 1000 1500 2000 PGA4 ENOB (rms) PGA1 PGA2 PGA16 PGA8 PGA32 PGA64 PGA128 Sinc3 Filter, Buffer OFF EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 0 500 1000 1500 2000 ENOB (rms) PGA4 PGA8 PGA1 PGA2 PGA16 PGA32 PGA64 PGA128 Decimation Ratio = fMOD fDATA Sinc3 Filter, Buffer ON EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 0 500 1000 1500 2000 ENOB (rms) PGA4 PGA8PGA1 PGA2 PGA16 PGA32 PGA64 PGA128 Decimation Ratio = fMOD fDATA AV DD = 3V, Sinc3 Filter, VREF = 1.25V, Buffer OFF EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 0 500 1000 1500 2000 ENOB (rms) PGA4 PGA8 PGA1 PGA2 PGA16 PGA32 PGA64 PGA128 AV DD = 3V, Sinc3 Filter, VREF = 1.25V, Buffer ON Decimation Ratio = fMOD fDATA EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 0 500 1000 1500 2000 ENOB (rms) PGA4 PGA8 PGA1 PGA2 PGA32 PGA128PGA16 PGA64 Decimation Ratio = fMOD fDATA Sinc2 Filter EFFECTIVE NUMBER OF BITS vs DATA RATE ENOB (rms) Data Rate (SPS) 1 10 100 1000 Sinc3 Filter, Buffer OFF PGA1 PGA8 PGA32 PGA64 PGA128

SBAS289Ewww.ti.com TYPICAL CHARACTERISTICS (Cont.) AV DD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer ON, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified. FAST SETTLING FILTER EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 0 500 1000 1500 2000 ENOB (rms) 1500 Decimation Ratio = fMOD fDATA Fast Settling Filter EFFECTIVE NUMBER OF BITS vs fMOD (set with ACLK) ENOB (rms) Data Rate (SPS) 1 10 100 1k 10k 100k fMOD = 15.6kHz fMOD = 62.5kHz fMOD = 203kHz fMOD = 110kHz fMOD = 31.25kHz EFFECTIVE NUMBER OF BITS vs fMOD (set with ACLK) WITH FIXED DECIMATION ENOB (rms) Data Rate (SPS) 10 100 1k 10k 100k DEC = 2020 DEC = 255 DEC = 500 DEC = 50 DEC = 20 DEC = 10 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 NOISE vs INPUT SIGNAL V IN (V) Noise (rms, ppm of FS) −10 INTEGRAL NONLINEARITY vs INPUT SIGNAL V IN (V) INL (ppm of FS) –40°C +25°C VREF = 2.5V +85°C −10 −15 INTEGRAL NONLINEARITY vs INPUT SIGNAL V IN (V) VIN = −VREF 0V IN = +VREF INL (ppm of FS) VREF = AVDD = 5V Buffer OFF

SBAS289E www.ti.com TYPICAL CHARACTERISTICS (Cont.) AV DD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer ON, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified. 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 ADC CURRENT vs PGA PGA Setting 18 24 3 2 16 128 64 IADC (µA) AV DD = 5V, Buffer = ON AV DD = 5V, Buffer = OFF AV DD = 3V, Buffer = ON AV DD = 3V, Buffer = OFF 4500 4000 3500 3000 2500 2000 1500 1000 500 HISTOGRAM OF OUTPUT DATA ppm of FS Number of Occurrences ADC INTEGRAL NONLINEARITY vs V REF VREF (V) INL (ppm of FS) VIN = VREF Buffer OFF AV DD = 3V AV DD = 5V INL ERROR vs PGA PGA Setting INL (ppm of FS) 14 21 6 8 128 6432 AV DD = 5V VREF = 2.5V 1.3 1.3 1.2 1.2 1.1 1.1 1.0 1.0 0.9 ANALOG SUPPLY CURRENT Analog Supply Voltage (V) Analog Supply Current (mA) –40°C +25°C +85°C PGA = 128, ADC = ON VREF = ON, DBOR = ON ALVD = ON, IDAC = ON –10 –12 OFFSET DAC: OFFSET vs TEMPERATURE Offset (ppm of FSR) Temperature (°C) –40 +25 +85

SBAS289Ewww.ti.com TYPICAL CHARACTERISTICS (Cont.) AV DD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer ON, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified. 1.00006 1.00004 1.00002 0.99998 0.99996 0.99994 OFFSET DAC: GAIN vs TEMPERATURE Normalized Gain Temperature (°C) –40 +25 +85 DIGITAL SUPPLY CURRENT vs FREQUENCY Clock Frequency (MHz) Digital Supply Current (mA) 1 10 100 100 0.1 DV DD = 5V DIGITAL SUPPLY CURRENT vs CLOCK DIVIDER Clock Frequency (MHz) Digital Supply Current (mA) 1 10 100 100 0.1 1024 Divider Values DIGITAL SUPPLY CURRENT vs SUPPLY VOLTAGE Supply Voltage (V) Digital Supply Current (mA) –40°C +85°C +25°C CMOS DIGITAL OUTPUT Output Current (mA) Output Voltage (V) 02 0 10 40 30 70 6050 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 Low Output Low Output NORMALIZED GAIN vs PGA PGA Setting Normalized Gain (%) 14 21 6 8 128 6432 101 100 Buffer ON

SBAS289E www.ti.com TYPICAL CHARACTERISTICS (Cont.) AV DD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer ON, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified. IO LF MODE vs TEMPERATURE Temperature (°C) IO Frequency (MHz) −40 25 85 2.7V 5.25V 3.3V 4.75V AV DD = DVDD IO HF MODE vs FREQUENCY Temperature (°C) IO Frequency (MHz) −40 25 85 4.75V 5.25V AV DD = DVDD

SBAS289Ewww.ti.com The MSC1200Yx allows the user to uniquely configure the Flash memory map to meet the needs of their application. The Flash is programmable down to 2.7V using serial pro- gramming. Flash endurance is typically 1M Erase/Write cycles. The part has separate analog and digital supplies, which can be independently powered from 2.7V to +5.25V. At +3V operation, the power dissipation for the part is typically less than 4mW. The MSC1200Yx is packaged in a TQFP-48 package. The MSC1200Yx is designed for high-resolution measurement applications in smart transmitters, industrial process control, weigh scales, chromatography, and portable instrumentation. ENHANCED 8051 CORE All instructions in the MSC1200 family perform exactly the same functions as they would in a standard 8051. The effect on bits, flags, and registers is the same. However, the timing is different. The MSC1200 family utilizes an efficient 8051 core which results in an improved instruction execution speed of between 1.5 and 3 times faster than the original core for the same external clock speed (4 clock cycles per instruction versus 12 clock cycles per instruction, as shown in Figure 2). This translates into an effective throughput improvement of more than 2.5 times, using the same code and same external clock speed. Therefore, a device frequency of 33MHz for the MSC1200Yx actually performs at an equivalent execution speed of 82.5MHz compared to the

DESCRIPTION

The MSC1200Yx is a completely integrated family of mixed- signal devices incorporating a high-resolution delta-sigma ADC, 8-bit IDAC, 8-channel multiplexer, burnout detect cur- rent sources, selectable buffered input, offset DAC, program- mable gain amplifier (PGA), temperature sensor, voltage reference, 8-bit microcontroller, Flash Program Memory, Flash Data Memory, and Data SRAM, as shown in Figure 1. On-chip peripherals include an additional 32-bit accumulator, basic SPI, basic I 2C, USART, multiple digital input/output ports, watchdog timer, low-voltage detect, on-chip power-on reset, brownout reset, timer/counters, system clock divider, PLL, on-chip oscillator, and external interrupts. The device accepts low-level differential or single-ended signals directly from a transducer. The ADC provides 24 bits of resolution and 24 bits of no-missing-code performance using a Sinc 3 filter with a programmable sample rate. The ADC also has a selectable filter that allows for high-resolu- tion single-cycle conversion. The microcontroller core is 8051 instruction set compatible. The microcontroller core is an optimized 8051 core that executes up to three times faster than the standard 8051 core, given the same clock source. This makes it possible to run the device at a lower external clock frequency and achieve the same perfor- mance at lower power than the standard 8051 core. ACC MUX AV DD VREF Modulator 4K or 8K FLASH

128 Bytes

EXT (4) PROG USART EXT (2) SCK/SCL/CLKS On-Chip Oscillator 8-Bit Offset DAC 8-Bit IDAC Burnout Detect AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AINCOM IDAC AGND REFOUT/REFIN+ REFIN – DV DD DGND XIN XOUT Temperature Sensor Burnout Detect RST CAP 220pF Ceramic AGND AV DD BUFFER PGA NOTE (1) REF IN− must be tied to AGND when using internal VREF . (1) FIGURE 1. Block Diagram. FIGURE 2. Instruction Cycle Timing.

FIGURE 3. Comparison of MSC1200 Timing to Standard FIGURE 4. MSC1200 Timing Chain and Clock Control.

12 Cycles

4 Cycles

increment or optionally run at 4 clocks per increment. The MSC1200 also provides dual data pointers (DPTRs). cycles through software implementation. difference between family members is the memory configuration. across several application platforms. ware for the MSC1200 with existing 8051 development tools. developers also provide support. clocks to those sections, as shown in Figure 4.

corresponding special function register (SFR) associated with each component. FIGURE 5. MSC1200 ADC Structure.

FIGURE 8. Filter Step Responses. NOTE: (1) With Synchronized Channel Changes. require a 26-bit ADC to resolve 75nV, as shown in Table I. does not reduce the range of the ADC. using the value in the Analog Clock register (ACLK, F6H ). computes a gain value to nullify gain errors in the system. Offset DAC register should be done after calibration. response of each filter is shown in Figure 9.

range for the device, or improper operation may still occur. H ), an interrupt is generated. enabled, the ramp rate can be slower. in HCR2. IOM is the default mode for the device. active clock mode for the various startup conditions. CLKSEL = 111) or HF mode (if HCR2, CLKSEL = 110). FIGURE 11. Clock Block Diagram. NOTE: (1) The trace length connecting the CAP pin to the 220pF ceramic capacitor should be as short as possible. NOTES: (1) Clock detection is only done at startup; refer to Electrical Characteristics parameter tRFD in Figure B. (2) PLL operation requires that both AVDD and DVDD are within their specified operating range. TABLE II. Active Clock Modes.

pin can also be used to control the output of data on DOUT. clock sources can be found by referring to the PASEL SFR.

• Toggle SCK by setting and clearing the port pin.
• Memory Write Pulse ( WR ) which is idle high. Whenever a external memory write command (MOVX) is executed then a pulse is seen on P3.6. This method can be used only if CPOL is set to ‘1’.
• Memory Write Pulse toggle version: In this mode, SCK toggles whenever an external write command (MOVX) is executed.
• T0_Out signal can be used as a clock. A pulse is generated on SCK whenever Timer 0 expires. The idle state of the signal is low, so this can be used only if CPOL is cleared to ‘0’.
• T0_Out Toggle: SCK toggles whenever Timer 0 expires.
• T1_Out signal can be used as a clock. A pulse is generated whenever Timer 1 expires. The idle state of the signal is low, so this can be used only if CPOL is cleared to ‘0’.
• T1_Out Toggle: SCK toggles whenever Timer 1 expires. The SS pin can be used to control the output of data on DOUT when the MSC1200 is in slave mode. The SS function is enabled or disabled by the ESS bit of the SPICON SFR. When enabled, the SS input of a slave device must be externally asserted before a master device can exchange data with the slave device. SS must be low before data transactions and must stay low for the duration of the transaction. When SS is high then data will not be shifted into the shift register nor will the counter increment. When SPI is enabled, SS also controls the drive of the line DOUT (P1.2). When SS is low in slave mode, the DOUT pin will be driven and when SS is high then DOUT will be high impedance. The SPI generates an interrupt ECNT (AIE.2) to indicate that the transfer/reception of the byte is complete. The interrupt goes high whenever the counter value is equal to 8 (indicat- ing that 8 SCKs have occurred). The interrupt is cleared on reading or writing to the SPIDATA register. During the data transfer, the actual counter value can be read from the SPICON SFR. Power Down The SPI is powered down by the PDSPI bit in the power control register (PDCON). This bit needs to be cleared to enable the SPI function. When the SPI is powered down the pins P1.2, P1.3, P1.4, and P3.6 revert to general-purpose I/O pins. Application Flow Explained below are the steps of the typical application usage flow of SPI in master and slave mode: Master Mode Application Flow 1. Configure the port pins. 2. Configure the SPI. 3. Assert SS to enable slave communications (if applicable). 4. Write data to SPIDATA. 5. Generate 8 SCKs. 6. Read the received data from SPIDATA.

FIGURE 16. SPI Timing Diagram.

1. Configure the ports pins.
2. Wait for the Count Interrupt (8 SCKs).
3. Read the data from SPIDATA.

(DOUT should be set high so that the bus is not pulled low). transfer and also after the transfer of the ACK/NACK. detected. The bit counter can be polled or used as an interrupt. written by the software, which will terminate clock stretching. removed and the previous data will be lost. can be generated in software. The serial data must be stable on the bus while SCL is high. allows the master to read the state of ACK/NACK. (1) Generate in software; write 0x7F to I2CDATA. (3) Generate in software. Can enable bit count = 1 interrupt prior to ACK/NACK for interrupt use. Generate ACK by writing 0x7F to I2CDATA; generate NACK by writing 0xFF to I2CDATA. (4) Generate in software; write 0xFF to I2CDATA. FIGURE 17. Timing Diagram for I2C Transmission and Reception.

ACK/NACK from the master can then be read. H (for ACK) or 0xFFH (for NACK) to I2CDATA. only during Flash Memory Programming mode. the MSC1200Y3 contains 8kB of Flash Memory on-chip. Memory (DM), as shown in Tables III and IV and Figure 18. The MSC1200 family offers two memory configurations. FIGURE 18. Memory Map. TABLE IV. Flash Memory Partitioning Addresses. TABLE III. MSC1200Y Flash Partitioning.

SBAS289Ewww.ti.com Working Registers As part of the lower 128 bytes of RAM, there are four banks of Working Registers, as shown in Figure 20. The Working Registers are general-purpose RAM locations that can be addressed in a special way. They are designated R0 through R7. Since there are four banks, the currently selected bank will be used by any instruction using R0-R7. This allows software to change context by simply switching banks. This is controlled via the Program Status Word register (PSW; 0D0 H) in the SFR area described below. The 16 bytes immediately above the R0-R7 registers are bit addressable. So any of the 128 bits in this area can be directly accessed using bit addressable instructions. Stack Another use of the Scratchpad area is for the programmer’s stack. This area is selected using the Stack Pointer (SP; 81H ) SFR. Whenever a call or interrupt is invoked, the return address is placed on the Stack. It also is available to the programmer for variables, etc., since the Stack can be moved and there is no fixed location within the RAM desig- nated as Stack. The Stack Pointer will default to 07 H on reset. The user can then move it as needed. The SP will point to the last used value. Therefore, the next value placed on the Stack is put at SP + 1. Each PUSH or CALL will increment the SP by the appropriate value. Each POP or RET will decrement as well. Program Memory After reset, the CPU begins execution from Program Memory location 0000 H . The standard internal Program Memory size for MSC1200 family members is shown in Table V. If enabled the Boot ROM will appear from address F800 H to FBFFH . STANDARD INTERNAL MODEL NUMBER PROGRAM MEMORY SIZE (BYTES) MSC1200Y3 8k MSC1200Y2 4k TABLE V. MSC1200 Maximum Internal Program Memory Sizes. Boot ROM There is a 1kB Boot ROM that controls operation during serial programming. Additionally, the Boot ROM routines shown in Table VI can be accessed during the user mode if it is enabled. When enabled, the Boot ROM routines will be located at memory addresses F800 H -FBFFH during user mode. HEX ADDRESS ROUTINE C DECLARATIONS DESCRIPTION F802 sfr_rd char sfr_rd(void); Return SFR value pointed to by CADDR (1) F805 sfr_wr void sfr_wr(char d); Write to SFR pointed to by CADDR (1) FBD8 monitor_isr void monitor_isr() interrupt 6; Push registers and call cmd_parser FBDA cmd_parser void cmd_parser(void); See SBAA076B.pdf FBDC put_string void put_string(char code *string); Output string FBDE page_erase char page_erase (int faddr, char fdata, char fdm); Erase flash page FBE0 write_flash Assembly only; DPTR = address, ACC = data Flash write (2) FBE2 write_flash_chk char write_flash_chk (int faddr, char fdata, char fdm); Write flash byte, verify FBE4 write_flash_byte void write_flash_byte (int faddr, char fdata); Write flash byte (2) FBE6 faddr_data_read char faddr_data_read(char faddr); Read HW config byte from faddr FBE8 data_x_c_read char data_x_c_read(int faddr, char fdm); Read xdata or code byte FBEA tx_byte void tx_byte(char); Send byte to USART0 FBEC tx_hex void tx_hex(char); Send hex value to USART0 FBEE putx void putx(char); Send “x” to USART0 on R7 = 1 FBF0 rx_byte char rx_byte(void); Read byte from USART0 FBF2 rx_byte_echo char rx_byte_echo(void); Read and echo byte on USART0 FBF4 rx_hex_echo char rx_hex_echo(void); Read and echo hex on USART0 FBF6 rx_hex_dbl_echo int rx_hex_dbl_echo(void); Read int as hex and echo: USART0 FBF8 rx_hex_word_echo int rx_hex_word_echo(void); Read int reversed as hex and echo: USART0 FBFA autobaud void autobaud(void); Set baud with received CR (3) FBFC putspace1 void putspace1(void); Output 1 space to USART0 FBFE putcr void putcr(void); Output CR, LF to USART0 NOTES: (1) CADDR must be set using the faddr_data_read routine. (2) MWS register (SFR 8FH ) defines Data Memory or Program Memory write. (3) SFR registers CKCON and TCON must be initialized: CKCON = 0x10 and TCON = 0x00. TABLE VI. MSC1200 Boot ROM Routines.

code execution can occur from Boot ROM while programming. service routine is vectored to. If level triggered, the flag follows the state of the pin. (3) Cleared automatically by hardware when interrupt vector occurs. (4) Globally enabled by EA (IE.7). TABLE VII. Interrupt Summary. nal 8051 family. All of the standard interrupts are available. Flash Memory including the 64 configuration bytes. FIGURE 21. Serial Programming Mode. programming mode on power-up.

SBAS289Ewww.ti.com bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CADDR 3F H EPMA PML RSL EBR EWDR 1 DFSEL1 DFSEL0 Hardware Configuration Register 0 (HCR0)— Accessed Using SFR Registers CADDR and CDATA. To read this register during normal operation, refer to the register descriptions for CADDR and CDATA. EPMA Enable Programming Memory Access (Security Bit). bit 7 0: After reset in programming modes, Flash Memory can only be accessed in UAM mode until a mass erase is done. 1: Fully Accessible (default) PML Program Memory Lock (PML has Priority Over RSL). bit 6 0: Enable all Flash Programming Modes in Program Memory; can be written in UAM. 1: Enable read only for Program Memory; cannot be written in UAM (default). RSL Reset Sector Lock. The reset sector can be used to provide another method of Flash Memory programming. This bit 5 will allow Program Memory updates without changing the jumpers for in-circuit code updates or program development. The code in this boot sector would then provide the monitor and programming routines with the ability to jump into the main Flash code when programming is finished. 0: Enable Reset Sector Writing 1: Enable Read Only Mode for Reset Sector (4kB) (default) EBR Enable Boot ROM. Boot ROM is 1kB of code located in ROM, not to be confused with the 4kB Boot Sector located bit 4 in Flash Memory. 0: Disable Internal Boot ROM 1: Enable Internal Boot ROM (default) EWDR Enable Watchdog Reset. bit 3 0: Disable Watchdog Reset 1: Enable Watchdog Reset (default) DFSEL1-0 Data Flash Memory Size (see Table II). bits 1-0 00: 4kB Data Flash Memory (MSC1200Y3 Only) 01: 2kB Data Flash Memory 10: 1kB Data Flash Memory 11: No Data Flash Memory (default)

SBAS289E www.ti.com 76 54 32 1 0 CADDR 3E H 11 11 1 D D B 1 1 Hardware Configuration Register 1 (HCR1) To read this register during normal operation, refer to the register descriptions for CADDR and CDATA. DDB Disable Digital Brownout Detection bit 2 0: Enable Digital Brownout Detection (2.7V) 1: Disable Digital Brownout Detection (default) Hardware Configuration Register 2 (HCR2) 76 54 32 1 0 CADDR 3D H 0 0 0 0 0 CLKSEL2 CLKSEL1 CLKSEL0 To read this register during normal operation, refer to the register descriptions for CADDR and CDATA. CLKSEL2-0 Clock Select bits 2-0 000: Reserved 001: Reserved 010: Reserved 011: External Clock Mode 100: PLL High-Frequency (HF) Mode 101: PLL Low-Frequency (LF) Mode 110: Internal Oscillator High-Frequency (HF) Mode 111: Internal Oscillator Low-Frequency (LF) Mode Configuration Memory Programming Certain key functions such as Brownout Reset and Watchdog Timer are controlled by the hardware configuration bits. These bits are nonvolatile and can only be changed through serial flash programming. Other peripheral control and status functions, such as ADC configuration timer setup, and Flash control are controlled through the SFRs.

SBAS289Ewww.ti.com SFR Definitions ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET VALUES 80H 81H SP 07H 82H DPL0 00H 83H DPH0 00H 84H DPL1 00H 85H DPH1 00H 86H D P S 0000000S E L 0 0 H 87H PCON SMOD 011G F 1 G F 0 STOP IDLE 30 H 88H TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00 H GATE C/T M1 M0 GATE C/T M1 M0 8AH TL0 00H 8BH TL1 00H 8C H TH0 00H 8D H TH1 00H 8EH CKCON 0 0 0 T1M T0M MD2 MD1 MD0 01 H 8FH M W S 0000000M X W S 0 0 H INT5 INT4 INT3 INT2/SS DIN DOUT 91H E X I FI E 5 I E 4 I E 3 I E 2 1000 0 8 H 92H 93H CADDR 00H 94H CDATA 00H 95H 96H 97H 98H SCON0 SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00 H 99H SBUF0 00H 9AH SPICON SBIT3 SBIT2 SBIT1 SBIT0 ORDER CPHA ESS CPOL 00 H I2CCON SBIT3 SBIT2 SBIT1 SBIT0 STOP START DCS CNTSEL 9BH SPIDATA 00H I2CDATA 9C H 9D H 9EH 9FH A0H A1H A2H A3H A4H AIPOL SECIP SUMIP ADCIP MSECIP I2CIP CNTIP ALVDIP 0 00 H A5H P A I 0000P A I 3 P A I 2 P A I 1 P A I 0 0 0 H A6H AIE ESEC ESUM EADC EMSEC EI2C ECNT EALV 0 00 H A7H AISTAT SEC SUM ADC MSEC I2C CNT ALVD 0 00 H A8H IE EA 0 0 ES0 ET1 EX1 ET0 EX0 00 H A9H AA H AB H AC H AD H AE H P1DDRL P13H P13L P12H P12L P11H P11L P10H P10L 00 H AF H P1DDRH P17H P17L P16H P16L P15H P15L P14H P14L 00 H SCK/SCL/CLKS T1 T0 INT1 INT0 TXD0 RXD0 B1H B2H B3H P3DDRL P33H P33L P32H P32L P31H P31L P30H P30L 00 H B4H P3DDRH P37H P37L P36H P36L P35H P35L P34H P34L 00 H B5H IDAC 00H B6H B7H B8H IP 1 0 0 PS0 PT1 PX1 PT0 PX0 80 H B9H BA H BB H BC H BD H BE H

SBAS289E www.ti.com ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET VALUES BF H C0 H C1 H C2 H C3 H C4 H C5 H C6 H EWU EWUWDT EWUEX1 EWUEX0 00 H C7 H SYSCLK 0 0 DIVMOD1 DIVMOD0 0 DIV2 DIV1 DIV0 00 H C8 H C9 H CA H CB H CC H CD H CE H CF H D0 H PSW CY AC F0 RS1 RS0 OV F1 P 00 H D1 H OCL LSB 00 H D2 H OCM 00H D3 H OCH MSB 00H D4 H GCL LSB 5A H D5 H GCM EC H D6 H GCH MSB 5FH D7 H ADMUX INP3 INP2 INP1 INP0 INN3 INN2 INN1 INN0 01 H D8 H EICON 0 1 EAI AI WDTI 0 0 0 40 H D9 H ADRESL LSB 00 H DA H ADRESM 00H DB H ADRESH MSB 00H DC H ADCON0 — BOD EVREF VREFH EBUF PGA2 PGA1 PGA0 30 H DD H ADCON1 OF_UF POL SM1 SM0 — CAL2 CAL1 CAL0 00 H DE H ADCON2 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 1B H DF H ADCON3 00000D R 1 0 D R 9 D R 8 0 6 H E0H ACC 00H E1H SSCON SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 00 H E2H SUMR0 LSB 00 H E3H SUMR1 00H E4H SUMR2 00H E5H SUMR3 MSB 00H E6H ODAC 00H E7H LVDCON ALVDIS 0001111 8 F H E8H E I E 111E W D I E X 5 E X 4 E X 3 E X 2 E 0 H E9H H W P C 0 0000000M E M O R Y 0000_000xB EA H H W P C 1 00100000 2 0 H EB H HWVER EC H Reserved ED H Reserved EE H FMCON 0 PGERA 0 FRCM 0 BUSY 1 0 02 H EF H FTCON FER3 FER2 FER1 FER0 FWR3 FWR2 FWR1 FWR0 A5 H F0H B 00H F1H PDCON PDICLK PDIDAC PDI2C 0 PDADC PDWDT PDST PDSPI 6F H F2H PASEL PSEN4 PSEN3 PSEN2 PSEN1 PSEN0 0 0 0 00 H F3H Reserved F4H PLLL PLL7 PLL6 PLL5 PLL4 PLL3 PLL2 PLL1 PLL0 C1 H F5H PLLH CLKSTAT2 CLKSTAT1 CLKSTAT0 PLLLOCK 0 0 PLL9 PLL8 x1 H F6H ACLK 0 FREQ6 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03 H F7H SRST 0000000 RSTREQ 00 H F8H E I P 111P W D I P X 5 P X 4 P X 3 P X 2 E 0 H F9H SECINT WRT SECINT6 SECINT5 SECINT4 SECINT3 SECINT2 SECINT1 SECINT0 7F H FA H MSINT WRT MSINT6 MSINT5 MSINT4 MSINT3 MSINT2 MSINT1 MSINT0 7F H FB H USEC 0 0 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03 H FC H MSECL MSECL7 MSECL6 MSECL5 MSECL4 MSECL3 MSECL2 MSECL1 MSECL0 9F H FD H MSECH MSECH7 MSECH6 MSECH5 MSECH4 MSECH3 MSECH2 MSECH1 MSECH0 0F H FE H HMSEC HMSEC7 HMSEC6 HMSEC5 HMSEC4 HMSEC3 HMSEC2 HMSEC1 HMSEC0 63 H FFH WDTCON EWDT DWDT RWDT WDCNT4 WDCNT3 WDCNT2 WDCNT1 WDCNT0 00 H SFR Definitions (Cont.)

SBAS289Ewww.ti.com 7 6 5 4 3 2 1 0 Reset Value SP.7-0 Stack Pointer . The stack pointer identifies the location where the stack will begin. The stack pointer is incremented before bits 7-0 every PUSH or CALL operation and decremented after each POP or RET/RETI. This register defaults to 07H after reset. Data Pointer Low 0 (DPL0) Stack Pointer (SP) DPL0.7-0 Data Pointer Low 0. This register is the low byte of the standard 8051 16-bit data pointer. DPL0 and DPH0 bits 7-0 are used to point to non-scratchpad data RAM. The current data pointer is selected by DPS (SFR 86H ). Data Pointer High 0 (DPH0) 7 6 5 4 3 2 1 0 Reset Value DPH0.7-0 Data Pointer High 0. This register is the high byte of the standard 8051 16-bit data pointer. DPL0 and DPH0 bits 7-0 are used to point to non-scratchpad data RAM. The current data pointer is selected by DPS (SFR 86H ). Data Pointer Low 1 (DPL1) 7 6 5 4 3 2 1 0 Reset Value DPL1.7-0 Data Pointer Low 1. This register is the low byte of the auxiliary 16-bit data pointer. When the SEL bit (DPS.0) bits 7-0 (SFR 86 H ) is set, DPL1 and DPH1 are used in place of DPL0 and DPH0 during DPTR operations. Data Pointer High 1 (DPH1) 7 6 5 4 3 2 1 0 Reset Value DPH1.7-0 Data Pointer High. This register is the high byte of the auxiliary 16-bit data pointer. When the SEL bit (DPS.0) bits 7-0 (SFR 86 H ) is set, DPL1 and DPH1 are used in place of DPL0 and DPH0 during DPTR operations. Data Pointer Select (DPS) 7 6 5 4 3 2 1 0 Reset Value 7 6 5 4 3 2 1 0 Reset Value SFR 86 H 0 0 0 0 0 0 0 SEL 00 H SEL Data Pointer Select. This bit selects the active data pointer. bit 0 0: Instructions that use the DPTR will use DPL0 and DPH0. 1: Instructions that use the DPTR will use DPL1 and DPH1.

SBAS289E www.ti.com SMOD Serial Port 0 Baud Rate Doubler Enable. The serial baud rate doubling function for Serial Port 0. bit 7 0: Serial Port 0 baud rate will be a standard baud rate. 1: Serial Port 0 baud rate will be double that defined by baud rate generation equation. GF1 General-Purpose User Flag 1. This is a general-purpose flag for software control. bit 3 GF0 General-Purpose User Flag 0. This is a general-purpose flag for software control. bit 2 STOP Stop Mode Select. Setting this bit will halt the oscillator and block external clocks. This bit will always read as a 0. bit 1 Exit with RESET. In this mode, internal peripherals are frozen and I/O pins are held in their current state. The ADC is frozen, but IDAC and VREF remain active. IDLE Idle Mode Select. Setting this bit will freeze the CPU, Timer 0 and 1, and the USART; other peripherals remain bit 0 active. This bit will always be read as a 0. Exit with AIE (A6H ) and EWU (C6H ) interrupts (refer to Figure 4 for clocks affected during IDLE). Timer/Counter Control (TCON) 7 6 5 4 3 2 1 0 Reset Value SFR 87 H SMOD 0 1 1 GF1 GF0 STOP IDLE 30 H TF1 Timer 1 Overflow Flag. This bit indicates when Timer 1 overflows its maximum count as defined by the current bit 7 mode. This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine. 0: No Timer 1 overflow has been detected. 1: Timer 1 has overflowed its maximum count. TR1 Timer 1 Run Control. This bit enables/disables the operation of Timer 1. Halting this timer will preserve the current bit 6 count in TH1, TL1. 0: Timer is halted. 1: Timer is enabled. TF0 Timer 0 Overflow Flag. This bit indicates when Timer 0 overflows its maximum count as defined by the current bit 5 mode. This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 0 interrupt service routine. 0: No Timer 0 overflow has been detected. 1: Timer 0 has overflowed its maximum count. TR0 Timer 0 Run Control. This bit enables/disables the operation of Timer 0. Halting this timer will preserve the bit 4 current count in TH0, TL0. 0: Timer is halted. 1: Timer is enabled. IE1 Interrupt 1 Edge Detect. This bit is set when an edge/level of the type defined by IT1 is detected. If IT1 = 1, this bit 3 bit will remain set until cleared in software or the start of the External Interrupt 1 service routine. If IT1 = 0, this bit will inversely reflect the state of the INT1 pin. IT1 Interrupt 1 Type Select. This bit selects whether the INT1 pin will detect edge or level triggered interrupts. bit 2 0: INT1 is level triggered. 1: INT1 is edge triggered. IE0 Interrupt 0 Edge Detect. This bit is set when an edge/level of the type defined by IT0 is detected. If IT0 = 1, this bit 3 bit will remain set until cleared in software or the start of the External Interrupt 0 service routine. If IT0 = 0, this bit will inversely reflect the state of the INT0 pin. IT0 Interrupt 0 Type Select. This bit selects whether the INT0 pin will detect edge or level triggered interrupts. bit 2 0: INT0 is level triggered. 1: INT0 is edge triggered. Power Control (PCON) 7 6 5 4 3 2 1 0 Reset Value SFR 88 H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00 H

SBAS289Ewww.ti.com Timer Mode Control (TMOD) 7 6 5 4 32 10 TIMER 1 TIMER 0 Reset Value SFR 89H GATE C/T M1 M0 GATE C/T M1 M0 00 H GATE Timer 1 Gate Control. This bit enables/disables the ability of Timer 1 to increment. bit 7 0: Timer 1 will clock when TR1 = 1, regardless of the state of pin INT1. 1: Timer 1 will clock only when TR1 = 1 and pin INT1 = 1. C/T Timer 1 Counter/Timer Select. bit 6 0: Timer is incremented by internal clocks. 1: Timer is incremented by pulses on T1 pin when TR1 (TCON.6, SFR 88H ) is 1. M1, M0 Timer 1 Mode Select. These bits select the operating mode of Timer 1. bits 5-4 TL0.7-0 Timer 0 LSB. This register contains the least significant byte of Timer 0. bits 7-0 Timer 1 LSB (TL1) 7 6 5 4 3 2 1 0 Reset Value TL1.7-0 Timer 1 LSB. This register contains the least significant byte of Timer 1. bits 7-0 Timer 0 MSB (TH0) 7 6 5 4 3 2 1 0 Reset Value TH0.7-0 Timer 0 MSB. This register contains the most significant byte of Timer 0. bits 7-0 7 6 5 4 3 2 1 0 Reset Value GATE Timer 0 Gate Control. This bit enables/disables the ability of Timer 0 to increment. bit 3 0: Timer 0 will clock when TR0 = 1, regardless of the state of pin INT0 (software control). 1: Timer 0 will clock only when TR0 = 1 and pin INT0 = 1 (hardware control). C/T Timer 0 Counter/Timer Select. bit 2 0: Timer is incremented by internal clocks. 1: Timer is incremented by pulses on pin T0 when TR0 (TCON.4, SFR 88H ) is 1. M1, M0 Timer 0 Mode Select. These bits select the operating mode of Timer 0. bits 1-0 M1 M0 MODE 0 0 Mode 0: 8-bit counter with 5-bit prescale. 0 1 Mode 1: 16 bits. 1 0 Mode 2: 8-bit counter with auto reload. 1 1 Mode 3: Two 8-bit counters. M1 M0 MODE 0 0 Mode 0: 8-bit counter with 5-bit prescale. 0 1 Mode 1: 16 bits. 1 0 Mode 2: 8-bit counter with auto reload. 1 1 Mode 3: Two 8-bit counters. Timer 0 LSB (TL0)

SBAS289E www.ti.com Port 1 (P1) 7 6 5 4 3 2 1 0 Reset Value INT5 INT4 INT3 INT2/SS DIN DOUT PROG P1.7-0 General-Purpose I/O Port 1. This register functions as a general-purpose I/O port. In addition, all the pins have bits 7-0 an alternative function listed below. Each of the functions is controlled by several other SFRs. The associated Port 1 latch bit must contain a logic ‘1’ before the pin can be used in its alternate function capacity. To use the alternate function, set the appropriate mode in P1DDRL (SFR AEH ), P1DDRH (SFR AFH ). INT5 External Interrupt 5.A falling edge on this pin will cause an external interrupt 5 if enabled. bit 7 INT4 External Interrupt 4. A rising edge on this pin will cause an external interrupt 4 if enabled. bit 6 INT3 External Interrupt 3.A falling edge on this pin will cause an external interrupt 3 if enabled. bit 5 INT2/SS External Interrupt 2. A rising edge on this pin will cause an external interrupt 2 if enabled. This pin can be used bit 4 as slave select ( SS ) in SPI slave mode. DIN Serial Data In. This pin receives serial data in SPI and I2C modes (in I2C mode, this pin should be configured bit 3 as an input) or standard 8051. DOUT Serial Data Out. This pin transmits serial data in SPI and I2C modes (in I2C mode, this pin should be configured bit 2 as an open drain) or standard 8051. PROG Program Mode. When this pin is pulled low at power-up, the device enters Serial Programming mode (refer to bit 0 Figure B). Timer 1 MSB (TH1) 7 6 5 4 3 2 1 0 Reset Value 7 6 5 4 3 2 1 0 Reset Value SFR 8E H 0 0 0 T1M T0M MD2 MD1 MD0 01 H TH1.7-0 Timer 1 MSB. This register contains the most significant byte of Timer 1. bits 7-0 Clock Control (CKCON) T1M Timer 1 Clock Select. This bit controls the division of the system clock that drives Timer 1. Clearing this bit to 0 bit 4 maintains 8051 compatibility. This bit has no effect on instruction cycle timing. 0: Timer 1 uses a divide by 12 of the crystal frequency. 1: Timer 1 uses a divide by 4 of the crystal frequency. T0M Timer 0 Clock Select. This bit controls the division of the system clock that drives Timer 0. Clearing this bit to 0 bit 3 maintains 8051 compatibility. This bit has no effect on instruction cycle timing. 0: Timer 0 uses a divide by 12 of the crystal frequency. 1: Timer 0 uses a divide by 4 of the crystal frequency. MD2, MD1, MD0 Stretch MOVX Select. These bits select the time by which MOVX cycles are to be stretched. Since the MSC1200 bit 3 does not allow external memory access, these bits should be set to 000B to allow for the fastest flash data memory access. Memory Write Select (MWS) MXWS MOVX Write Select. This allows writing to the internal Flash program memory. bit 0 0: No writes are allowed to the internal Flash program memory. 1: Writing is allowed to the internal Flash program memory, unless PML (HCR0) or RSL (HCR0) are on. 7 6 5 4 3 2 1 0 Reset Value SFR 8F H 00 0 0 0 0 0 M X W S 0 0 H

SBAS289Ewww.ti.com IE5 External Interrupt 5 Flag. This bit will be set when a falling edge is detected on INT5. This bit must be bit 7 cleared manually by software. Setting this bit in software will cause an interrupt if enabled. IE4 External Interrupt 4 Flag. This bit will be set when a rising edge is detected on INT4. This bit must be cleared bit 6 manually by software. Setting this bit in software will cause an interrupt if enabled. IE3 External Interrupt 3 Flag. This bit will be set when a falling edge is detected on INT3. This bit must be cleared bit 5 manually by software. Setting this bit in software will cause an interrupt if enabled. IE2 External Interrupt 2 Flag. This bit will be set when a rising edge is detected on INT2. This bit must be cleared bit 4 manually by software. Setting this bit in software will cause an interrupt if enabled. Configuration Address Register (CADDR) (write only) 7 6 5 4 3 2 1 0 Reset Value SFR 94H 00H 7 6 5 4 3 2 1 0 Reset Value SFR 93H 00H CADDR Configuration Address Register. This register supplies the address for reading bytes in the 64 bytes of Flash Configuration bits 7-0 Memory. Al ways use the Boot ROM CADDR access routine. This register is also used for SFR read and write routines. WARNING: If this register is written to while executing from Flash Memory, the CDATA register will be incorrect. Configuration Data Register (CDATA) CDATA Configuration Data Register. This register will contain the data in the 64 bytes of Flash Configuration Memory bits 7-0 that is located at the last written address in the CADDR register. This is a read-only register. 7 6 5 4 3 2 1 0 Reset Value SFR 91 H IE5 IE4 IE3 IE2 1 0 0 0 08 H External Interrupt Flag (EXIF)

SBAS289E www.ti.com 7 6 5 4 3 2 1 0 Reset Value SFR 99 H 00H SBUF0 Serial Data Buffer 0. Data for Serial Port 0 is read from or written to this location. The serial transmit and bits 7-0 receive buffers are separate registers, but both are addressed at this location. Serial Data Buffer 0 (SBUF0) SM0-2 Serial Port 0 Mode. These bits control the mode of serial Port 0. Modes 1, 2, and 3 have 1 start and 1 stop bit bits 7-5 in addition to the 8 or 9 data bits. 7 6 5 4 3 2 1 0 Reset Value SFR 98 H SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00 H REN_0 Receive Enable. This bit enables/disables the serial Port 0 received shift register. bit 4 0: Serial Port 0 reception disabled. 1: Serial Port 0 received enabled (modes 1, 2, and 3). Initiate synchronous reception (mode 0). TB8_0 9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial Port 0 modes 2 and 3. bit 3 RB8_0 9th Received Bit State. This bit identifies the state of the 9th reception bit of received data in serial Port 0 modes bit 2 2 and 3. In serial port mode 1, when SM2_0 = 0, RB8_0 is the state of the stop bit. RB8_0 is not used in mode 0. TI_0 Transmitter Interrupt Flag. This bit indicates that data in the serial Port 0 buffer has been completely shifted bit 1 out. In serial port mode 0, TI_0 is set at the end of the 8th data bit. In all other modes, this bit is set at the end of the last data bit. This bit must be manually cleared by software. RI_0 Receiver Interrupt Flag. This bit indicates that a byte of data has been received in the serial Port 0 buffer. In bit 0 serial port mode 0, RI_0 is set at the end of the 8th bit. In serial port mode 1, RI_0 is set after the last sample of the incoming stop bit subject to the state of SM2_0. In modes 2 and 3, RI_0 is set after the last sample of RB8_0. This bit must be manually cleared by software. MODE SM0 SM1 SM2 FUNCTION LENGTH PERIOD 0 0 0 0 Synchronous 8 bits 12 p CLK (1) 0 0 0 1 Synchronous 8 bits 4 p CLK (1) 1 0 1 0 Asynchronous 10 bits Timer 1 Baud Rate Equation 1 0 1 1 Asynchronous — Valid Stop Required(2) 10 bits Timer 1 Baud Rate Equation 2 1 0 0 Asynchronous 11 bits 64 p CLK (1) (SMOD = 0) 32 pCLK (1) (SMOD = 1) 2 1 0 1 Asynchronous with Multiprocessor Communication 11 bits 64 p CLK (1) (SMOD = 0) 32 pCLK (1) (SMOD = 1) 3 1 1 0 Asynchronous 11 bits Timer 1 Baud Rate Equation 3 1 1 1 Asynchronous with Multiprocessor Communication (3) 11 bits Timer 1 Baud Rate Equation NOTES: (1) pCLK will be equal to tCLK , except that pCLK will stop for IDLE. (2) RI_0 will only be activated when a valid stop is received. (3) RI_0 will not be activated if bit 9 = 0. Serial Port 0 Control (SCON0)

SBAS289Ewww.ti.com SPI Control (SPICON) (SERSEL bit determines SPICON control) SBIT3-0 Serial Bit Count. Number of bits transferred (read only). bits 7-4 SBIT3:0 COUNT 0x00 0 0x01 1 0x03 2 0x02 3 0x06 4 0x07 5 0x05 6 0x04 7 0x0C 8 7 6 5 4 3 2 1 0 Reset Value SFR 9A H SBIT3 SBIT2 SBIT1 SBIT0 ORDER CPHA ESS CPOL 00 H ORDER Set Bit Order for Transmit and Receive. bit 3 0: Most Significant Bits First 1: Least Significant Bits First CPHA Serial Clock Phase Control. bit 2 0: Valid data starting from half SCK period before the first edge of SCK 1: Valid data starting from the first edge of SCK ESS Enable Slave Select. bit 1 0: SS (P1.4) is configured as a general-purpose I/O (default). 1: SS (P1.4) is configured as SS for SPI mode. DOUT (P1.2) drives when SS is low, and DOUT (P1.2) is high- impedance when SS is high. CPOL Serial Clock Polarity. bit 0 0: SCK idle at logic LOW 1: SCK idle at logic HIGH 7 6 5 4 3 2 1 0 Reset Value SFR 9A H SBIT3 SBIT2 SBIT1 SBIT0 STOP START DCS CNTSEL 00 H I2C Control (I2CCON) (SERSEL bit determines I2CCON control) SBIT3-0 Serial Bit Count. Number of bits transferred (read only). bits 7-4 SBIT3:0 COUNT 0x00 0 0x01 1 0x03 2 0x02 3 0x06 4 0x07 5 0x05 6 0x04 7 0x0C 8 STOP Stop-Bit Status. bit 3 0: No Stop 1: Stop Condition Received and I2CCNT set (cleared on write to I2CDATA) START Start-Bit Status . bit 2 0: No Stop 1: Start or Repeated Start Condition Received and I2CCNT set (cleared on write to I2CDATA)

SBAS289E www.ti.com 7 6 5 4 3 2 1 0 Reset Value SFR A4 H SECIP SUMIP ADCIP MSECIP I2CIP CNTIP ALVDIP Unused 00 H SECIP Second System Timer Interrupt Poll (before IRQ masking). bit 7 0 = Seconds System Timer Interrupt Poll Inactive 1 = Seconds System Timer Interrupt Poll Active SUMIP Accumulator Interrupt Poll (before IRQ masking). bits 6 0 = Accumulator Interrupt Poll Inactive 1 = Accumulator Interrupt Poll Active ADCIP ADC Interrupt Poll (before IRQ masking). bits 5 0 = ADC Interrupt Poll Inactive 1 = ADC Interrupt Poll Active MSECIP Millisecond System Timer Interrupt Poll (before IRQ masking). bits 4 0 = Millisecond System Timer Interrupt Poll Inactive 1 = Millisecond System Timer Interrupt Poll Active I2CIP I 2C Interrupt Poll (before IRQ masking). bits 3 0 = I 2C Interrupt Poll Inactive 1 = I2C Interrupt Poll Active CNTIP Serial Bit Count Interrupt Poll (before IRQ masking). bits 2 0 = Serial Bit Count Interrupt Poll Inactive 1 = Serial Bit Count Interrupt Poll Active ALVDIP Analog Low Voltage Detect Interrupt Poll (before IRQ masking). bits 1 0 = Analog Low Voltage Detect Interrupt Poll Inactive 1 = Analog Low Voltage Detect Interrupt Poll Active Auxilliary Interrupt Poll (AIPOL) 7 6 5 4 3 2 1 0 Reset Value SFR 9B H 00H SPIDATA SPI Data Register. Data for SPI is read from or written to this location. The SPI transmit and receive buffers bits 7-0 are separate registers, but both are addressed at this location. I2CDATA I2C Data Register. Data for I2C is read from or written to this location. The I2C transmit and receive buffers bits 7-0 are separate registers, but both are addressed at this location. SPI Data Register (SPIDATA) / I2C Data Register (I2CDATA) DCS Disable Serial Clock Stretch. bit 1 0: Enable SCL Stretch (cleared by firmware or START condition) 1: Disable SCL Stretch CNTSEL Counter Select. bit 0 0: Counter IRQ Set for Bit Counter = 8 (default) 1: Counter IRQ Set for Bit Counter = 1

SBAS289Ewww.ti.com 7 6 5 4 3 2 1 0 Reset Value SFR A6 H ESEC ESUM EADC EMSEC EI2C ECNT EALV 0 00 H Auxiliary Interrupt Enable (AIE) Interrupts are enabled by EICON.4 (SFR D8H ). The other interrupts are controlled by the IE and EIE registers. ESEC Enable Second System Timer Interrupt (lowest priority auxiliary interrupt). bit 7 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: Second Timer Interrupt mask. ESUM Enable Summation Interrupt. bit 6 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: Summation Interrupt mask. EADC Enable ADC Interrupt. bit 5 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: ADC Interrupt mask. EMSEC Enable Millisecond System Timer Interrupt. bit 4 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: Millisecond System Timer Interrupt mask. EI2C Enable I 2C Start/Stop Bit. bit 3 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: I2C Start/Stop Bit mask. ECNT Enable Serial Bit Count Interrupt. bit 2 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: Serial Bit Count Interrupt mask. EALV Enable Analog Low Voltage Interrupt. bit 1 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: Analog Low Voltage Detect Interrupt mask. 7 6 5 4 3 2 1 0 Reset Value SFR A5 H 0 0 0 0 PAI3 PAI2 PAI1 PAI0 00H PAI3 PAI2 PAI1 PAI0 AUXILIARY INTERRUPT STATUS 0 0 0 0 No Pending Auxiliary IRQ 0 0 0 1 Reserved 0 0 1 0 Analog Low Voltage Detect IRQ and Possible Lower Priority Pending 00 11 I 2C IRQ and Possible Lower Priority Pending 0 1 0 0 Serial Bit Count Interrupt and Possible Lower Priority Pending 0 1 0 1 Millisecond System Timer IRQ and Possible Lower Priority Pending 0 1 1 0 ADC IRQ and Possible Lower Priority Pending 0 1 1 1 Accumulator IRQ and Possible Lower Priority Pending 1 0 0 0 Second System Timer IRQ and Possible Lower Priority Pending Pending Auxiliary Interrupt (PAI) PAI Pending Auxiliary Interrupt Register. The results of this register can be used as an index to vector to the appropriate bits 3-0 interrupt routine. All of these interrupts vector through address 0033H.

SBAS289E www.ti.com Interrupt Enable (IE) EA Global Interrupt Enable. This bit controls the global masking of all interrupts except those in AIE (SFR A6H ). bit 7 0: Disable interrupt sources. This bit overrides individual interrupt mask settings for this register. 1: Enable all individual interrupt masks. Individual interrupts in this register will occur if enabled. ES0 Enable Serial port 0 interrupt. This bit controls the masking of the serial Port 0 interrupt. bit 4 0: Disable all serial Port 0 interrupts. 1: Enable interrupt requests generated by the RI_0 (SCON0.0, SFR 98H ) or TI_0 (SCON0.1, SFR 98H ) flags. ET1 Enable Timer 1 Interrupt. This bit controls the masking of the Timer 1 interrupt. bit 3 0: Disable Timer 1 interrupt. 1: Enable interrupt requests generated by the TF1 flag (TCON.7, SFR 88H ). EX1 Enable External Interrupt 1. This bit controls the masking of external interrupt 1. bit 2 0: Disable external interrupt 1. 1: Enable interrupt requests generated by the INT1 pin. ET0 Enable Timer 0 Interrupt. This bit controls the masking of the Timer 0 interrupt. bit 1 0: Disable all Timer 0 interrupts. 1: Enable interrupt requests generated by the TF0 flag (TCON.5, SFR 88H ). EX0 Enable External Interrupt 0. This bit controls the masking of external interrupt 0. bit 0 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the INT0 pin. Auxiliary Interrupt Status Register (AISTAT) 7 6 5 4 3 2 1 0 Reset Value SFR A7 H SEC SUM ADC MSEC I2C CNT ALVD 0 00 H SEC Second System Timer Interrupt Status Flag (lowest priority AI). bit 7 0: SEC Interrupt cleared or masked. 1: SEC Interrupt active (it is cleared by reading SECINT, SFR F9H ). SUM Summation Register Interrupt Status Flag. bit 6 0: SUM Interrupt cleared or masked. 1: SUM Interrupt active (it is cleared by reading the lowest byte of SUMR0, SFR E2H ). ADC ADC Interrupt Status Flag. bit 5 0: ADC Interrupt cleared or masked. 1: ADC Interrupt active (it is cleared by reading the lowest byte of ADRESL, SFR D9H ; if active, no new data will be written to the ADC Results registers). MSEC Millisecond System Timer Interrupt Status Flag. bit 4 0: MSEC Interrupt cleared or masked. 1: MSEC Interrupt active (it is cleared by reading MSINT, SFR FAH ). I2C I 2C Start/Stop Interrupt Status Flag. bit 3 0: I 2C Start/stop Interrupt cleared or masked. 1: I2C Start/stop Interrupt active (it is cleared by writing to I2CDATA, SFR 9BH ). CNT CNT Interrupt Status Flag. bit 2 0: CNT Interrupt cleared or masked. 1: CNT Interrupt active (it is cleared by reading from or writing to SPIDATA/I2CDATA, SFR 9BH ). ALVD Analog Low Voltage Detect Interrupt Status Flag. bit 1 0: ALVD Interrupt cleared or masked. 1: ALVD Interrupt active (cleared in HW if AVDD exceeds ALVD threshold). NOTE: If an interrupt is masked, the status can be read in AIPOL, SFR A4H . 7 6 5 4 3 2 1 0 Reset Value SFR A8 H EA 0 0 ES0 ET1 EX1 ET0 EX0 00 H

SBAS289Ewww.ti.com P1.1 Port 1 bit 1 control. bits 3-2 Port 1 Data Direction High Register (P1DDRH) P1.0 Port 1 bit 0 control. bits 1-0 P11H P11L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P1.7 Port 1 bit 7 control. bits 7-6 7 6 5 4 3 2 1 0 Reset Value SFR AF H P17H P17L P16H P16L P15H P15L P14H P14L 00 H P17H P17L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P1.6 Port 1 bit 6 control. bits 5-4 P16H P16L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P1.5 Port 1 bit 5 control. bits 3-2 P15H P15L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P1.4 Port 1 bit 4 control. bits 1-0 P14H P14L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 1 Data Direction Low Register (P1DDRL) P1.3 Port 1 bit 3 control. bits 7-6 7 6 5 4 3 2 1 0 Reset Value SFR AE H P13H P13L P12H P12L P11H P11L P10H P10L 00 H P13H P13L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P1.2 Port 1 bit 2 control. bits 5-4 P12H P12L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P10H P10L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input

SBAS289E www.ti.com 7 6 5 4 3 2 1 0 Reset Value SFR B3 H P33H P33L P32H P32L P31H P31L P30H P30L 00 H P33H P33L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P32H P32L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P31H P31L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P30H P30L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input 7 6 5 4 3 2 1 0 Reset Value SCK/SCL/CLKS T1 T0 INT1 INT0 TXD0 RXD0 Port 3 (P3) P3.7-0 General-Purpose I/O Port 3 . This register functions as a general-purpose I/O port. In addition, all the pins have bits 7-0 an alternative function listed below. Each of the functions is controlled by several other SFRs. The associated Port 3 latch bit must contain a logic ‘1’ before the pin can be used in its alternate function capacity. SCK/SCL/CLKS Clock Source Select. Refer to PASEL (SFR F2H ). bit 6 T1 Timer/Counter 1 External Input. A 1 to 0 transition on this pin will increment Timer 1. bit 5 T0 Timer/Counter 0 External Input. A 1 to 0 transition on this pin will increment Timer 0. bit 4 INT1 External Interrupt 1. A falling edge/low level on this pin will cause an external interrupt 1 if enabled. bit 3 INT0 External Interrupt 0. A falling edge/low level on this pin will cause an external interrupt 0 if enabled. bit 2 TXD0 Serial Port 0 Transmit. This pin transmits the serial Port 0 data in serial port modes 1, 2, 3, and emits the bit 1 synchronizing clock in serial port mode 0. RXD0 Serial Port 0 Receive. This pin receives the serial Port 0 data in serial port modes 1, 2, 3, and is a bidirectional bit 0 data transfer pin in serial port mode 0. Port 3 Data Direction Low Register (P3DDRL) P3.3 Port 3 bit 3 control. bits 7-6 P3.2 Port 3 bit 2 control. bits 5-4 P3.1 Port 3 bit 1 control. bits 3-2 P3.0 Port 3 bit 0 control. bits 1-0

SBAS289Ewww.ti.com Port 3 Data Direction High Register (P3DDRH) 7 6 5 4 3 2 1 0 Reset Value SFR B4 H P37H P37L P36H P36L P35H P35L P34H P34L 00 H P3.7 Port 3 bit 7 control. bits 7-6 P3.6 Port 3 bit 6 control. bits 5-4 P3.5 Port 3 bit 5 control. bits 3-2 P3.4 Port 3 bit 4 control. bits 1-0 P36H P36L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P35H P35L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P34H P34L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P37H P37L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input 7 6 5 4 3 2 1 0 Reset Value SFR B5 H 00H NOTE: Port 3.7 also controlled by EA and Memory Access Control HCR1.1. NOTE: Port 3.6 also controlled by EA and Memory Access Control HCR1.1. IDAC Register IDAC IDAC Register. bits 7-0 IDAC OUT = IDAC • 3.8µA (~1mA full-scale). Setting (PDCON.PDIDAC) will shut down IDAC and float the IDAC pin. Interrupt Priority (IP) PS0 Serial Port 0 Interrupt. This bit controls the priority of the serial Port 0 interrupt. bit 4 0 = Serial Port 0 priority is determined by the natural priority order. 1 = Serial Port 0 is a high priority interrupt. PT1 Timer 1 Interrupt. This bit controls the priority of the Timer 1 interrupt. bit 3 0 = Timer 1 priority is determined by the natural priority order. 1 = Timer 1 priority is a high priority interrupt. PX1 External Interrupt 1. This bit controls the priority of external interrupt 1. bit 2 0 = External interrupt 1 priority is determined by the natural priority order. 1 = External interrupt 1 is a high priority interrupt. PT0 Timer 0 Interrupt. This bit controls the priority of the Timer 0 interrupt. bit 1 0 = Timer 0 priority is determined by the natural priority order. 1 = Timer 0 priority is a high priority interrupt. PX0 External Interrupt 0. This bit controls the priority of external interrupt 0. bit 0 0 = External interrupt 0 priority is determined by the natural priority order. 1 = External interrupt 0 is a high priority interrupt. 7 6 5 4 3 2 1 0 Reset Value SFR B8 H 1 0 0 PS0 PT1 PX1 PT0 PX0 80 H

SBAS289E www.ti.com Auxiliary interrupts will wake up from IDLE. They are enabled with EAI (EICON.5). EWUWDT Enable Wake Up Watchdog Timer. Wake up using watchdog timer interrupt. bit 2 0 = Don ’t wake up on watchdog timer interrupt. 1 = Wake up on watchdog timer interrupt. EWUEX1 Enable Wake Up External 1. Wake up using external interrupt source 1. bit 1 0 = Don ’t wake up on external interrupt source 1. 1 = Wake up on external interrupt source 1. EWUEX0 Enable Wake Up External 0. Wake up using external interrupt source 0. bit 0 0 = Don ’t wake up on external interrupt source 0. 1 = Wake up on external interrupt source 0. System Clock Divider Register (SYSCLK) Enable Wake Up (EWU) Waking Up from IDLE Mode 7 6 5 4 3 2 1 0 Reset Value SFR C6 H —— — — — EWUWDT EWUEX1 EWUEX0 00 H 7 6 5 4 3 2 1 0 Reset Value SFR C7 H 0 0 DIVMOD1 DIVMOD0 0 DIV2 DIV1 DIV0 00 H DIVMOD DIVIDE MODE

00 Normal mode (default, no divide)

01 Immediate mode: start divide immediately, return to Normal mode on IDLE wakeup condition or Normal mode write. 10 Delay mode: same as Immediate mode, except that the mode changes with the millisecond interrupt (MSINT). If MSINT is enabled, the divide will start on the next MSINT and return to normal mode on the following MSINT. If MSINT is not enabled, the divide will start on the next MSINT condition (even if masked) but will not leave the divide mode until the MSINT counter overflows, which follows a wakeup condition. Can exit on Normal mode write. 11 Manual mode: start divide immediately; exit mode only on write to DIVMOD. DIVMOD DIVISION MODE STATUS

00 No divide

01 Divider is in Immediate mode

10 Divider is in Delay mode

11 Reserved

000 Divide by 2 (default) f CLK = fSYS /2

001 Divide by 4 f CLK = fSYS /4

010 Divide by 8 f CLK = fSYS /8

011 Divide by 16 f CLK = fSYS /16

100 Divide by 32 f CLK = fSYS /32

101 Divide by 1024 f CLK = fSYS /1024

110 Divide by 2048 f CLK = fSYS /2048

111 Divide by 4096 f CLK = fSYS /4096

DIVMOD1-0 Clock Divide Mode bits 5-4 Write: Read: DIV2-0 Divide Mode bit 2-0

SBAS289Ewww.ti.com ADC Offset Calibration Register Middle Byte (OCM) 7 6 5 4 3 2 1 0 Reset Value SFR D2 H 00H OCM ADC Offset Calibration Register Middle Byte. This is the middle byte of the 24-bit word that contains the ADC bits 7-0 offset calibration. A value which is written to this location will set the ADC offset calibration value. ADC Offset Calibration Register High Byte (OCH) 7 6 5 4 3 2 1 0 Reset Value SFR D3 H MSB 00H OCH ADC Offset Calibration Register High Byte. This is the high byte of the 24-bit word that contains the bits 7-0 ADC offset calibration. A value which is written to this location will set the ADC offset calibration value. Program Status Word (PSW) CY Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (during addition) or a borrow bit 7 (during subtraction). Otherwise it is cleared to 0 by all arithmetic operations. AC Auxiliary Carry Flag. This bit is set to 1 if the last arithmetic operation resulted in a carry into (during addition), bit 6 or a borrow (during substraction) from the high order nibble. Otherwise it is cleared to 0 by all arithmetic operations. F0 User Flag 0. This is a bit-addressable, general-purpose flag for software control. bit 5 RS1, RS0 Register Bank Select 1-0. These bits select which register bank is addressed during register accesses. bits 4-3 OV Overflow Flag. This bit is set to 1 if the last arithmetic operation resulted in a carry (addition), borrow bit 2 (subtraction), or overflow (multiply or divide). Otherwise it is cleared to 0 by all arithmetic operations. F1 User Flag 1. This is a bit-addressable, general-purpose flag for software control. bit 1 P Parity Flag. This bit is set to 1 if the modulo-2 sum of the 8 bits of the accumulator is 1 (odd parity); and bit 0 cleared to 0 on even parity. ADC Offset Calibration Register Low Byte (OCL) 7 6 5 4 3 2 1 0 Reset Value SFR D0 H CY AC F0 RS1 RS0 OV F1 P 00 H RS1 RS0 REGISTER BANK ADDRESS 00 0 0 0 H -07H 01 1 0 8 H -0FH 10 2 1 0 H -17H 11 3 1 8 H -1FH OCL ADC Offset Calibration Register Low Byte. This is the low byte of the 24-bit word that contains the bits 7-0 ADC offset calibration. A value which is written to this location will set the ADC offset calibration value. 7 6 5 4 3 2 1 0 Reset Value SFR D1 H LSB 00 H

SBAS289E www.ti.com GCM ADC Gain Calibration Register Middle Byte. This is the middle byte of the 24-bit word that contains bits 7-0 the ADC gain calibration. A value which is written to this location will set the ADC gain calibration value. ADC Gain Calibration Register High Byte (GCH) 7 6 5 4 3 2 1 0 Reset Value SFR D5 H EC H GCH ADC Gain Calibration Register High Byte. This is the high byte of the 24-bit word that contains the bits 7-0 ADC gain calibration. A value which is written to this location will set the ADC gain calibration value. ADC Multiplexer Register (ADMUX) 7 6 5 4 3 2 1 0 Reset Value SFR D6 H MSB 5FH INP3-0 Input Multiplexer Positive Channel. This selects the positive signal input. bits 7-4 7 6 5 4 3 2 1 0 Reset Value SFR D7 H INP3 INP2 INP1 INP0 INN3 INN2 INN1 INN0 01 H INP3 INP2 INP1 INP0 POSITIVE INPUT

0000 A I N 0 (default)

0001 A I N 1

0010 A I N 2

0011 A I N 3

0100 A I N 4

0101 A I N 5

0110 A I N 6

0111 A I N 7

1000 A I NCOM

1111 T e m perature Sensor (Requires ADMUX = FF

H ) INN3-0 Input Multiplexer Negative Channel. This selects the negative signal input. bits 3-0 INN3 INN2 INN1 INN0 NEGATIVE INPUT

0000 A I N 0

0001 A I N 1 (default)

H ) ADC Gain Calibration Register Middle Byte (GCM) GCL ADC Gain Calibration Register Low Byte. This is the low byte of the 24-bit word that contains the ADC bits 7-0 gain calibration. A value which is written to this location will set the ADC gain calibration value. 7 6 5 4 3 2 1 0 Reset Value SFR D4 H LSB 5A H ADC Gain Calibration Register Low Byte (GCL)

SBAS289Ewww.ti.com ADRESL The ADC Results Low Byte. This is the low byte of the 24-bit word that contains the ADC bits 7-0 Results. Reading from this register clears the ADC interrupt; however, AI in EICON (SFR D8) must also be cleared. ADC Results Register Middle Byte (ADRESM) 7 6 5 4 3 2 1 0 Reset Value SFR D9 H LSB 00 H 7 6 5 4 3 2 1 0 Reset Value SFR DA H 00H ADRESM The ADC Results Middle Byte. This is the middle byte of the 24-bit word that contains the ADC bits 7-0 Results. ADC Results Register High Byte (ADRESH) ADRESH The ADC Results High Byte. This is the high byte of the 24-bit word that contains the ADC bits 7-0 Results. 7 6 5 4 3 2 1 0 Reset Value SFR DB H MSB 00H 7 6 5 4 3 2 1 0 Reset Value SFR D8 H 0 1 EAI AI WDTI 0 0 0 40 H Enable Interrupt Control (EICON) EAI Enable Auxiliary Interrupt. The Auxiliary Interrupt accesses nine different interrupts which are masked and bit 5 identified by SFR registers PAI (SFR A5H ), AIE (SFR A6H ), and AISTAT (SFR A7H ). 0 = Auxiliary Interrupt disabled (default). 1 = Auxiliary Interrupt enabled. AI Auxiliary Interrupt Flag. AI must be cleared by software before exiting the interrupt service routine, bit 4 after the source of the interrupt is cleared. Otherwise, the interrupt occurs again. Setting AI in software generates an Auxiliary Interrupt, if enabled. 0 = No Auxiliary Interrupt detected (default). 1 = Auxiliary Interrupt detected. WDTI Watchdog Timer Interrupt Flag. WDTI must be cleared by software before exiting the interrupt service routine. bit 3 Otherwise, the interrupt occurs again. Setting WDTI in software generates a watchdog time interrupt, if enabled. The Watchdog timer can generate an interrupt or reset. The interrupt is available only if the reset action is disabledin HCR0. 0 = No Watchdog Timer Interrupt Detected (default). 1 = Watchdog Timer Interrupt Detected. ADC Results Register Low Byte (ADRESL)

SBAS289E www.ti.com ADC Control Register 0 (ADCON0) 7 6 5 4 3 2 1 0 Reset Value SFR DC H — BOD EVREF VREFH EBUF PGA2 PGA1 PGA0 30 H BOD Burnout Detect. When enabled this connects a positive current source to the positive channel and a negative current bit 6 source to the negative channel. If the channel is open circuit then the ADC results will be full-scale (buffer must be enabled). 0 = Burnout Current Sources Off (default). 1 = Burnout Current Sources On. EVREF Enable Internal Voltage Reference. If an external voltage reference is used, the internal voltage reference should bit 5 be disabled. 0 = Internal Voltage Reference Off. 1 = Internal Voltage Reference On (default). VREFH Voltage Reference High Select. The internal voltage reference can be selected to be 2.5V or 1.25V. bit 4 0 = REFOUT/REFIN+ is 1.25V. 1 = REFOUT/REFIN+ is 2.5V (default). EBUF Enable Buffer. Enable the input buffer to provide higher input impedance but limits the input voltage range and bit 3 dissipates more power. 0 = Buffer disabled (default). 1 = Buffer enabled. PGA2-0 Programmable Gain Amplifier. Sets the gain for the PGA from 1 to 128. bits 2-0 PGA2 PGA1 PGA0 GAIN 0 0 0 1 (default) 00 1 2 01 0 4 01 1 8 10 0 1 6 10 1 3 2 11 0 6 4 1 1 1 128

SBAS289Ewww.ti.com SM1 SM0 SETTLING MODE 0 0 Auto 0 1 Fast Settling Filter 1 0 Sinc 2 Filter 1 1 Sinc 3 Filter ADC Control Register 1 (ADCON1) OF_UF Overflow/Underflow. If this bit is set, the data in the summation register is invalid. Either an overflow or an bit 7 underflow occurred. The bit is cleared by writing a 0 to it. POL Polarity. Polarity of the ADC result and Summation register. bit 6 0 = Bipolar. 1 = Unipolar. 7 6 5 4 3 2 1 0 Reset Value SFR DD H OF_UF POL SM1 SM0 — CAL2 CAL1 CAL0 x000 0000 B POL ANALOG INPUT DIGITAL OUTPUT +FSR 0x7FFFFF

0 ZERO 0x000000

–FSR 0x800000 +FSR 0xFFFFFF

1 ZERO 0x000000

–FSR 0x000000 SM1-0 Settling Mode. Selects the type of filter or auto select which defines the digital filter settling characteristics. bits 5-4 CAL2-0 Calibration Mode Control Bits. Writing to this register initiates calibration. bits 2-0 ADC Control Register 2 (ADCON2) CAL2 CAL1 CAL0 CALIBRATION MODE 0 0 0 No Calibration (default) 0 0 1 Self Calibration, Offset and Gain 0 1 0 Self Calibration, Offset Only 0 1 1 Self Calibration, Gain Only 1 0 0 System Calibration, Offset Only 1 0 1 System Calibration, Gain Only 1 1 0 Reserved 1 1 1 Reserved DR7-0 Decimation Ratio LSB (refer to ADCON3, SFR DF H ). bits 7-0 ADC Control Register 3 (ADCON3) 7 6 5 4 3 2 1 0 Reset Value SFR DE H DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 1B H DR10-8 Decimation Ratio Most Significant 3 Bits. The output data rate = f DecimationRatio MOD where fMOD = f ACLK CLK () +•16 4 . bits 2-0 Accumulator (A or ACC) 7 6 5 4 3 2 1 0 Reset Value ACC.7-0 Accumulator. This register serves as the accumulator for arithmetic and logic operations. bits 7-0 Summation/Shifter Control (SSCON) 7 6 5 4 3 2 1 0 Reset Value SFR E1 H SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 00 H Read Value— 000B. 7 6 5 4 3 2 1 0 Reset Value SFR DF H —— — — — DR10 DR9 DR8 06 H The Summation register is powered down when the ADC is powered down. If all zeroes are written to this register the 32-bit SUMR3-0 registers will be cleared. The Summation registers will do sign extend if Bipolar is selected in ADCON1.

SBAS289E www.ti.com SHF2-0 Shift Count. bits 2-0 SUMR0 Summation Register 0. This is the least significant byte of the 32-bit summation register or bits 0 to 7. bits 7-0 Write: will cause values in SUMR3-0 to be added to or subtracted from the summation register. Read: will clear the Summation Interrupt. Summation Register 1 (SUMR1) SHF2 SHF1 SHF0 SHIFT DIVIDE 000 1 2 001 2 4 010 3 8 011 4 1 6 100 5 3 2 101 6 6 4 1 1 0 7 128 1 1 1 8 256 7 6 5 4 3 2 1 0 Reset Value SFR E2 H LSB 00 H SUMR1 Summation Register 1. This is the most significant byte of the lowest 16 bits of the summation register or bits 8-15. bits 7-0 Summation Register 2 (SUMR2) 7 6 5 4 3 2 1 0 Reset Value SFR E3 H 00H SUMR2 Summation Register 2. This is the most significant byte of the lowest 24 bits of the summation register or bits 16-23. bits 7-0 7 6 5 4 3 2 1 0 Reset Value SFR E4 H 00H SSCON1-0 Summation/Shift Control. bits 7-6 SCNT2-0 Summation Count. When the summation is complete an interrupt will be generated unless masked. Reading the bits 5-3 SUMR0 register clears the interrupt. SCNT2 SCNT1 SCNT0 SUMMATION COUNT 00 0 2 00 1 4 01 0 8 01 1 1 6 10 0 3 2 10 1 6 4 1 1 0 128 1 1 1 256 SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 DESCRIPTION 0 0 0 0 0 0 0 0 Clear Summation Register 0 0 0 1 0 0 0 0 CPU Summation on Write to SUMR0 0 0 1 0 0 0 0 0 CPU Subtraction on Write to SUMR0 1 0 x x x Note (1) Note (1) Note (1) CPU Shift Only 0 1 Note (1) Note (1) Note (1) x x x ADC Summation Only 1 1 Note (1) Note (1) Note (1) Note (1) Note (1) Note (1) ADC Summation Completes then Shift Completes NOTES: (1) Refer to register bit definition. 7 6 5 4 3 2 1 0 Reset Value SFR E5 H MSB 00H Summation Register 3 (SUMR3) SUMR3 Summation Register 3. This is the most significant byte of the 32-bit summation register or bits 24-31. bits 7-0 Summation Register 0 (SUMR0)

SBAS289Ewww.ti.com Low Voltage Detect Control (LVDCON) ALVDIS Analog Low Voltage Detect Disable. bit 7 0 = Enable Detection of Low Analog Supply Voltage (ALVD interrupt set when AVDD < 2.8V). 1 = Disable Detection of Low Analog Supply Voltage. 7 6 5 4 3 2 1 0 Reset Value SFR E7 H ALVDIS 0 0 0 1 1 1 1 8F H Extended Interrupt Enable (EIE) 7 6 5 4 3 2 1 0 Reset Value SFR E8 H 1 1 1 EWDI EX5 EX4 EX3 EX2 E0 H EWDI Enable Watchdog Interrupt. This bit enables/disables the watchdog interrupt. The Watchdog timer is enabled by the WDTCON (SFR FF H ) and PDCON (SFR F1H ) registers. bit 4 0 = Disable the Watchdog Interrupt 1 = Enable Interrupt Request Generated by the Watchdog Timer EX5 External Interrupt 5 Enable. This bit enables/disables external interrupt 5. bit 3 0 = Disable External Interrupt 5 1 = Enable External Interrupt 5 EX4 External Interrupt 4 Enable. This bit enables/disables external interrupt 4. bit 2 0 = Disable External Interrupt 4 1 = Enable External Interrupt 4 EX3 External Interrupt 3 Enable. This bit enables/disables external interrupt 3. bit 1 0 = Disable External Interrupt 3 1 = Enable External Interrupt 3 EX2 External Interrupt 2 Enable. This bit enables/disables external interrupt 2. bit 0 0 = Disable External Interrupt 2 1 = Enable External Interrupt 2 Offset DAC Register (ODAC) ODAC Offset DAC Register. This register will shift the input by up to half of the ADC full-scale input range. The offset bit7-0 DAC value is summed with the ADC input prior to conversion. Writing 00H or 80H to ODAC turns off the Offset DAC. bit 7 Offset DAC Sign bit. 0 = Positive 1 = Negative bit 6-0 Offset =

• •    •−V PGA ODACREF bit 127 1 7[:] () NOTE: ODAC cannot be used to offset the input so that the buffer can be used for AGND signals. 7 6 5 4 3 2 1 0 Reset Value SFR E6 H 00H

SBAS289E www.ti.com Hardware Product Code Register 0 (HWPC0) HWPC0.7-0 Hardware Product Code LSB. Read only. bits 7-0 7 6 5 4 3 2 1 0 Reset Value SFR E9 H 0 0 0 0 0 0 0 MEMORY 0000_000x B 7 6 5 4 3 2 1 0 Reset Value SFR EA H 0 0 1000 00 2 0 H HWPC1.7-0 Hardware Product Code MSB. Read only. bits 7-0 Hardware Version Register (HWVER) PGERA Page Erase. Available in both user and program modes. bit 6 0 = Disable Page Erase Mode 1 = Enable Page Erase Mode FRCM Frequency Control Mode. The bypass is only used for slow clocks to save power. bit 4 0 = Bypass (default) 1 = Use Delay Line. Saves power (Recommended). BUSY Write/Erase BUSY Signal. bit 2 0 = Idle or Available 1 = Busy Flash Memory Timing Control Register (FTCON) 7 6 5 4 3 2 1 0 Reset Value SFR EE H 0 PGERA 0 FRCM 0 BUSY 1 0 02 H 7 6 5 4 3 2 1 0 Reset Value SFR EF H FER3 FER2 FER1 FER0 FWR3 FWR2 FWR1 FWR0 A5 H MEMORY SIZE MODEL FLASH MEMORY

0 MSC1200Y2 4kB

1 MSC1200Y3 8kB

Hardware Product Code Register 1 (HWPC1) Refer to Flash Timing Characteristics FER3-0 Set Erase. Flash Erase Time = (1 + FER) • (MSEC + 1) • tCLK . bits 7-4 11ms industrial temperature range. 5ms commercial temperature range. FWR3-0 Set Write. Flash Write Time = (1 + FWR) • (USEC + 1) • 5 • tCLK . bits 3-0 30 µs to 40µs. 7 6 5 4 3 2 1 0 Reset Value SFR EB H Flash Memory Control (FMCON) B Register (B) B B Register. This register serves as a second accumulator for certain arithmetic operations. bits 7-0 7 6 5 4 3 2 1 0 Reset Value SFR F0 H 00H

SBAS289Ewww.ti.com PSEN4-0 PSEN Mode Select. Defines the output on P3.6 in User Application mode or Serial Flash Programming mode. bits 7-3 00000: General-Purpose I/O (default) 00001: SYSCLK 00011: Internal PSEN (refer to Figure 3 for timing) 00101: Internal ALE (refer to Figure 3 for timing) 00111: f OSC (buffered XIN oscillator clock) 01001: Memory WR (MOVX write) 01011: T0 Out (overflow)(1) 01101: T1 Out (overflow)(1) 01111: fMOD (2) 10001: SYSCLK/2 (toggles on rising edge)(2) 10011: Internal PSEN /2(2) 10101: Internal ALE/2(2) 10111: fOSC /2(2) 11001: Memory WR /2 (MOVX write)(2) 11011: T0 Out/2 (overflow)(2) 11101: T1 Out/2 (overflow)(2) 11111: fMOD /2(2) NOTES: (1) On period of these signals equal to tCLK . (2) Duty cycle is 50%. 7 6 5 4 3 2 1 0 Reset Value SFR F1 H PDICLK PDIDAC PDI2C 0 PDADC PDWDT PDSPI PDSPI 6F H Turning peripheral modules off puts the MSC1200 in the lowest power mode. PDICLK Internal Clock Control. bit 7 0 = Internal Oscillator and PLL On (Internal Oscillator or PLL mode) 1 = Internal Oscillator and PLL Power Down (External Clock mode) PDIDAC IDAC Control. bit 6 0 = IDAC On 1 = IDAC Power Down (default) PDI2C I 2C Control. bit 5 0 = I 2C On (only when PDSPI = 1) 1 = I2C Power Down (default) PDADC ADC Control. bit 3 0 = ADC On 1 = ADC, VREF , and Summation registers are powered down (default). PDWDT Watchdog Timer Control. bit 2 0 = Watchdog Timer On 1 = Watchdog Timer Power Down (default) PDST System Timer Control. bit 1 0 = System Timer On 1 = System Timer Power Down (default) PDSPI SPI Control. bit 0 0 = SPI System On 1 = SPI System Power Down (default) PSEN /ALE Select (PASEL) 7 6 5 4 3 2 1 0 Reset Value SFR F2 H PSEN4 PSEN3 PSEN2 PSEN1 PSEN0 0 0 0 00 H Power-Down Control Register (PDCON)

SBAS289E www.ti.com Analog Clock (ACLK) FREQ6-0 Clock Frequency – 1. This value + 1 divides the system clock to create the ADC clock. bits 6-0 f ACLK = f ACLK CLK () + 1 , where fCLK = f SYSCLK Divider OSC fMOD = fACLK ADC Data Rate = fDATA = f DecimationRatio MOD System Reset Register (SRST) 7 6 5 4 3 2 1 0 Reset Value SFR F7 H 0 0 0 0 0 0 0 RSTREQ 00 H 7 6 5 4 3 2 1 0 Reset Value SFR F6 H 0 FREQ6 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03 H RSTREQ Reset Request. Setting this bit to 1 and then clearing to 0 will generate a system reset. bit 0 PLL7-0 PLL Counter Value Least Significant Bit. bits 7-0 PLL Frequency = External Crystal Frequency • PLL9:0 Phase Lock Loop High Register (PLLH) 7 6 5 4 3 2 1 0 Reset Value SFR F4 H PLL7 PLL6 PLL5 PLL4 PLL3 PLL2 PLL1 PLL0 C1 H Phase Lock Loop Low Register (PLLL) 7 6 5 4 3 2 1 0 Reset Value SFR F5 H CLKSTAT2 CLKSTAT1 CLKSTAT0 PLLLOCK 0 0 PLL9 PLL8 x1 H CLKSTAT2-0 Active Clock Status (read only). Derived from HCR2 setting; refer to Table II. bits 7-5 000: Reserved 001: Reserved 010: Reserved 011: External Clock Mode 100: PLL High-Frequency (HF) Mode (must read PLLLOCK to determine active clock status) 101: PLL Low-Frequency (LF) Mode (must read PLLLOCK to determine active clock status) 110: Internal Oscillator High-Frequency (HF) Mode 111: Internal Oscillator Low-Frequency (LF) Mode PLLLOCK PLL Lock Status and Status Enable. bit 4 For Write (PLL Lock Status Enable): 0 = No Effect 1 = Enable PLL Lock Detection (must wait 20ms before PLLLOCK read status is valid). For Read (PLL Lock Status): 0 = PLL Not Locked (PLL may be inactive; refer to Table II for active clock mode) 1 = PLL Locked (PLL is active clock) PLL9-8 PLL Counter Value Most Significant 2 Bits (refer to PLLL, SFR F4 H ) bits 1-0

SBAS289Ewww.ti.com The clock used for this timer is the 1ms clock which results from dividing the system clock by the values in registers MSECH:MSECL. Reading this register will clear MSINT. WRT Write Control. Determines whether to write the value immediately or wait until the current count is finished. Read = 0. bit 7 0 = Delay Write Operation. The MSINT value is loaded when the current count expires. 1 = Write Immediately. The MSINT counter is loaded once the CPU completes the write operation. MSINT6-0 Seconds Count. Normal operation would use 1ms as the clock interval. bits 6-0 MS Interrupt Interval = (1 + MSINT) • (MSEC + 1) • tCLK 7 6 5 4 3 2 1 0 Reset Value SFR FA H WRT MSINT6 MSINT5 MSINT4 MSINT3 MSINT2 MSINT1 MSINT0 7F H Milliseconds Interrupt (MSINT) 7 6 5 4 3 2 1 0 Reset Value SFR F8 H 1 1 1 PWDI PX5 PX4 PX3 PX2 E0 H 7 6 5 4 3 2 1 0 Reset Value SFR F9 H WRT SECINT6 SECINT5 SECINT4 SECINT3 SECINT2 SECINT1 SECINT0 7F H This system clock is divided by the value of the 16-bit register MSECH:MSECL. Then that 1ms timer tick is divided by the register HMSEC which provides the 100ms signal used by this seconds timer. Therefore, this seconds timer can generate an interrupt which occurs from 100ms to 12.8 seconds. Reading this register will clear the Seconds Interrupt. This Interrupt can be monitored in the AIE register. WRT Write Control. Determines whether to write the value immediately or wait until the current count is finished. bit 7 Read = 0. 0 = Delay Write Operation. The SEC value is loaded when the current count expires. 1 = Write Immediately. The counter is loaded once the CPU completes the write operation. SECINT6-0 Seconds Count. Normal operation would use 100ms as the clock interval. bits 6-0 Seconds Interrupt = (1 + SEC) • (HMSEC + 1) • (MSEC + 1) • t CLK . PWDI Watchdog Interrupt Priority. This bit controls the priority of the watchdog interrupt. bit 4 0 = The watchdog interrupt is low priority. 1 = The watchdog interrupt is high priority. PX5 External Interrupt 5 Priority. This bit controls the priority of external interrupt 5. bit 3 0 = External interrupt 5 is low priority. 1 = External interrupt 5 is high priority. PX4 External Interrupt 4 Priority. This bit controls the priority of external interrupt 4. bit 2 0 = External interrupt 4 is low priority. 1 = External interrupt 4 is high priority. PX3 External Interrupt 3 Priority. This bit controls the priority of external interrupt 3. bit 1 0 = External interrupt 3 is low priority. 1 = External interrupt 3 is high priority. PX2 External Interrupt 2 Priority. This bit controls the priority of external interrupt 2. bit 0 0 = External interrupt 2 is low priority. 1 = External interrupt 2 is high priority. Seconds Timer Interrupt (SECINT) Extended Interrupt Priority (EIP)

SBAS289E www.ti.com FREQ5-0 Clock Frequency – 1. This value + 1 divides the system clock to create a 1µs Clock. bits 5-0 USEC = CLK/(FREQ + 1). This clock is used to set Flash write time. See FTCON (SFR EFH ). One Millisecond Low Register (MSECL) MSECL7-0 One Millisecond Low. This value in combination with the next register is used to create a 1ms Clock. bits 7-0 1ms Clock = (MSECH • 256 + MSECL + 1) • tCLK . This clock is used to set Flash erase time. See FTCON (SFR EFH ). One Millisecond High Register (MSECH) 7 6 5 4 3 2 1 0 Reset Value SFR FB H 0 0 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03 H 7 6 5 4 3 2 1 0 Reset Value SFR FD H MSECH7 MSECH6 MSECH5 MSECH4 MSECH3 MSECH2 MSECH1 MSECH0 0F H 7 6 5 4 3 2 1 0 Reset Value SFR FC H MSECL7 MSECL6 MSECL5 MSECL4 MSECL3 MSECL2 MSECL1 MSECL0 9F H MSECH7-0 One Millisecond High. This value in combination with the previous register is used to create a 1ms clock. bits 7-0 1ms = (MSECH • 256 + MSECL + 1) • tCLK . One Hundred Millisecond Register (HMSEC) 7 6 5 4 3 2 1 0 Reset Value SFR FE H HMSEC7 HMSEC6 HMSEC5 HMSEC4 HMSEC3 HMSEC2 HMSEC1 HMSEC0 63 H 7 6 5 4 3 2 1 0 Reset Value SFR FF H EWDT DWDT RWDT WDCNT4 WDCNT3 WDCNT2 WDCNT1 WDCNT0 00 H HMSEC7-0 One Hundred Millisecond. This clock divides the 1ms clock to create a 100ms clock. bits 7-0 100ms = (MSECH • 256 + MSECL + 1) • (HMSEC + 1) • tCLK . Watchdog Timer Register (WDTCON) EWDT Enable Watchdog (R/W). bit 7 Write 1/Write 0 sequence sets the Watchdog Enable Counting bit. DWDT Disable Watchdog (R/W). bit 6 Write 1/Write 0 sequence clears the Watchdog Enable Counting bit. RWDT Reset Watchdog (R/W). bit 5 Write 1/Write 0 sequence restarts the Watchdog Counter. WDCNT4-0 Watchdog Count (R/W). bits 4-0 Watchdog expires in (WDCNT + 1) • HMSEC to (WDCNT + 2) • HMSEC, if the sequence is not asserted. There is an uncertainty of 1 count. NOTE: If HCR0.3 (EWDR) is set and the watchdog timer expires, a system reset is generated. If HCR0.3 (EWDR) is cleared and the watchdog timer expires, an interrupt is generated (see Table VII). One Microsecond Register (USEC)

ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY MSC1200Y2PFBR ACTIVE TQFP PFB 48 2000 MSC1200Y2PFBT ACTIVE TQFP PFB 48 250 MSC1200Y3PFBR ACTIVE TQFP PFB 48 2000 MSC1200Y3PFBT ACTIVE TQFP PFB 48 250 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. PACKAGE OPTION ADDENDUM www.ti.com 25-Nov-2004

MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 4073176/B 10/96 Gage Plane 0,13 NOM 0,25 0,45 0,75 Seating Plane 0,05 MIN 0,17 0,27 SQ 7,20 6,80 5,50 TYP SQ8,80 9,20 1,05 0,95 1,20 MAX 0,08 0,50 M0,08 0°–7° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026

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