MSA24

ADC12H030 NSC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 41

Technical content

Features

n Serial I/O (MICROWIRE Compatible) n 2, 4, or 8 channel differential or single-ended multiplexer n Analog input sample/hold function n Power down mode n Variable resolution and conversion rate n Programmable acquisition time n Variable digital output word length and format n No zero or full scale adjustment required n Fully tested and guaranteed with a 4.096V reference n 0V to 5V analog input range with single 5V power supply n No Missing Codes over temperature Key Specifications j Resolution 12-bit plus sign j 12-bit plus sign conversion time – ADC12H30 family 5.5 µs (max) – ADC12030 family 8.8 µs (max) j 12-bit plus sign throughput time – ADC12H30 family 8.6 µs (max) – ADC12030 family 14 µs (max) j Integral linearity error ±1 LSB (max) j single supply 5V ±10% j Power consumption 33 mW (max) – Power down 100 µW (typ) June 2002 ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold © 2002 National Semiconductor Corporation DS011354 www.national.com

ADC12038 Simplified Block Diagram 01135401 Connection Diagrams 16-Pin Wide Body SO Packages 20-Pin Wide Body SO Packages 01135406 Top View 01135407 Top View ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 www.national.com 2

Connection Diagrams (Continued) 24-Pin Wide Body SO, SSOP-EIAJ Packages 28-Pin Wide Body SO Packages 01135408 Top View 01135409 Top View

Ordering Information

Industrial Temperature Range Package ADC12H030CIWM, ADC12030CIWM M16B ADC12H032CIWM, ADC12032CIWM M20B ADC12H034CIN, ADC12034CIN N24C ADC12H034CIWM, ADC12034CIWM M24B ADC12H034CIMSA MSA24 ADC12H038CIWM, ADC12038CIWM M28B Pin Descriptions CCLK The clock applied to this input controls the sucessive approximation conversion time in- terval and the acquisition time. The rise and fall times of the clock edges should not ex- ceed 1 µs. SCLK This is the serial data clock input. The clock applied to this input controls the rate at which the serial data exchange occurs. The rising edge loads the information on the DI pin into the multiplexer address and mode select shift register. This address controls which channel of the analog input multi- plexer (MUX) is selected and the mode of operation for the A/D. With CS low the falling edge of SCLK shifts the data resulting from the previous ADC conversion out on DO, with the exception of the first bit of data. When CS is low continously, the first bit of the data is clocked out on the rising edge of EOC (end of conversion). When CS is toggled the falling edge of CS always clocks out the first bit of data. CS should be brought low when SCLK is low. The rise and fall times of the clock edges should not exceed 1 µs. DI This is the serial data input pin. The data applied to this pin is shifted by the rising edge of SCLK into the multiplexer address and mode select register. Table 2 through Table 5 show the assignment of the multi- plexer address and the mode select data. DO The data output pin. This pin is an active push/pull output when CS is low. When CS is high, this output is TRI-STATE. The A/D conversion result (D0–D12) and converter status data are clocked out by the falling edge of SCLK on this pin. The word length and format of this result can vary (see Table 1). The word length and format are con- trolled by the data shifted into the multiplexer address and mode select register (seeTable 5). EOC This pin is an active push/pull output and indicates the status of the ADC12030/2/4/8. When low, it signals that the A/D is busy with a conversion, auto-calibration, auto-zero or power down cycle. The rising edge of EOC signals the end of one of these cycles. CS This is the chip select pin. When a logic low ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 www.national.com3

Pin Descriptions (Continued) is applied to this pin, the rising edge of SCLK shifts the data on DI into the address regis- ter. This low also brings DO out of TRI-STATE. With CS low the falling edge of SCLK shifts the data resulting from the pre- vious ADC conversion out on DO, with the exception of the first bit of data. When CS is low continously, the first bit of the data is clocked out on the rising edge of EOC (end of conversion). When CS is toggled the fall- ing edge of CS always clocks out the first bit of data. CS should be brought low when SCLK is low. The falling edge of CS resets a conversion in progress and starts the se- quence for a new conversion. When CS is brought back low during a conversion, that conversion is prematurely terminated. The data in the output latches may be corrupted. Therefore, when CS is brought back low dur- ing a conversion in progress the data output at that time should be ignored. CS may also be left continuously low. In this case it is imperative that the correct number of SCLK pulses be applied to the ADC in order to remain synchronous. After the ADC supply power is applied it expects to see 13 clock pulses for each I/O sequence. The number of clock pulses the ADC expects is the same as the digital output word length. This word length can be modified by the data shifted in on the DO pin. Table 5 details the data required. DOR This is the data output ready pin. This pin is an active push/pull output. It is low when the conversion result is being shifted out and goes high to signal that all the data has been shifted out. CONV A logic low is required on this pin to program any mode or change the ADC’s configuration as listed in the Mode Programming Table 5 such as 12-bit conversion, 8-bit conversion, Auto Cal, Auto Zero etc. When this pin is high the ADC is placed in the read data only mode. While in the read data only mode, bringing CS low and pulsing SCLK will only clock out on DO any data stored in the ADCs output shift register. The data on DI will be neglected. A new conversion will not be started and the ADC will remain in the mode and/or configuration previously pro- grammed. Read data only cannot be per- formed while a conversion, Auto-Cal or Auto-Zero are in progress. PD This is the power down pin. When PD is high the A/D is powered down; when PD is low the A/D is powered up. The A/D takes a maximum of 250 µs to power up after the command is given. CH0–CH7 These are the analog inputs of the MUX. A channel input is selected by the address in- formation at the DI pin, which is loaded on the rising edge of SCLK into the address register (See Tables 2, 3, 4). The voltage applied to these inputs should not exceed V A+ or go below GND. Exceed- ing this range on an unselected channel will corrupt the reading of a selected channel. COM This pin is another analog input pin. It is used as a pseudo ground when the analog multiplexer is single-ended. MUXOUT1, MUXOUT2 These are the multiplexer output pins. A/DIN1, /DIN2 These are the converter input pins. MUX- OUT1 is usually tied to A/DIN1. MUXOUT2 is usually tied to A/DIN2. If external circuitry is placed between MUXOUT1 and A/DIN1, or MUXOUT2 and A/DIN2 it may be neces- sary to protect these pins. The voltage at these pins should not exceed V A + or go be- low AGND (see Figure 5). VREF+ This is the positive analog voltage reference input. In order to maintain accuracy, the volt- age range of V REF (VREF =V REF+−V REF−) is 1 VDC to 5.0 VDC and the voltage at VREF+ cannot exceed VA+. See Figure 6for recom- mended bypassing. VREF− The negative voltage reference input. In or- der to maintain accuracy, the voltage at this pin must not go below GND or exceed V A+. (See Figure 6). VA+, VD+ These are the analog and digital power sup- ply pins. V A + and V D + are not connected together on the chip. These pins should be tied to the same power supply and bypassed separately (see Figure 6). The operating voltage range of V A+ and VD+ is 4.5 VDC to 5.5 VDC. DGND This is the digital ground pin (see Figure 6). AGND This is the analog ground pin (see Figure 6). ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 www.national.com 4

Absolute Maximum Ratings (Notes 1, If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Positive Supply Voltage + =V A+=V D+) 6.5V Voltage at Inputs and Outputs except CH0–CH7 and COM −0.3V to V + +0.3V Voltage at Analog Inputs CH0–CH7 and COM GND −5V to V + +5V |VA+−V D+| 300 mV Input Current at Any Pin (Note 3) ±30 mA Package Input Current (Note 3) ±120 mA Package Dissipation at TA = 25˚C (Note 4) 500 mW ESD Susceptability (Note 5) Human Body Model 1500V Soldering Information N Packages (10 seconds) 260˚C Vapor Phase (60 seconds) 215˚C Infrared (15 seconds) 220˚C Storage Temperature −65˚C to +150˚C Operating Ratings (Notes 1, 2) Operating Temperature Range T MIN ≤ TA ≤ TMAX ADC12030CIWM, ADC12H030CIWM, ADC12032CIWM, ADC12H032CIWM, ADC12034CIN, ADC12034CIWM, ADC12H034CIN, ADC12H034CIWM, ADC12H034CIMSA, ADC12038CIWM, ADC12H038CIWM −40˚C ≤ T A ≤ +85˚C Supply Voltage (V+ =V A+=V D+) +4.5V to +5.5V |VA+−V D+| ≤ 100 mV VREF+ 0 Vt oV A+ VREF− 0 Vt oV REF+ VREF (VREF+−V REF−) 1V to V A+ VREF Common Mode Voltage Range 0.1 VA+ to 0.6 V A+ A/DIN1, A/DIN2, MUXOUT1 and MUXOUT2 Voltage Range 0V to V A+ A/D IN Common Mode Voltage Range 0V to VA+ Converter Electrical Characteristics The following specifications apply for V + =V A+=V D+ = +5.0 V DC,V REF+ = +4.096 V DC,V REF−=0V DC, 12-bit + sign conver- sion mode, fCK =f SK = 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f CK =f SK = 5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R S =2 5Ω, source impedance for V REF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.048V common-mode voltage, and 10(t CK) acquisition time unless otherwise specified. Boldface limits apply for TA =T J =T MIN to TMAX; all other limits T A =T J = 25˚C. (Notes 7, 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits (Note 11) Units (Limits) STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes 12 + sign Bits (min) +ILE Positive Integral Linearity Error After Auto-Cal (Notes 12, 18) ±1/2 ±1 LSB (max) −ILE Negative Integral Linearity Error After Auto-Cal (Notes 12, 18) ±1/2 ±1 LSB (max) DNL Differential Non-Linearity After Auto-Cal ±1 LSB (max) Positive Full-Scale Error After Auto-Cal (Notes 12, 18) ±1/2 ±3.0 LSB (max) Negative Full-Scale Error After Auto-Cal (Notes 12, 18) ±1/2 ±3.0 LSB (max) Offset Error After Auto-Cal (Notes 5, 18) ±1/2 ±2 LSB (max) VIN( + )=V IN (−) = 2.048V DC Common Mode Error After Auto-Cal (Note 15) ±2 ±3.5 LSB (max) TUE Total Unadjusted Error After Auto-Cal ±1 LSB (Notes 12, 13, 14) Resolution with No Missing Codes 8-bit + sign mode 8 + sign Bits (min) ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 www.national.com5

Converter Electrical Characteristics (Continued) The following specifications apply for V + =V A+=V D+ = +5.0 V DC,V REF+ = +4.096 V DC,V REF−=0V DC, 12-bit + sign conver- sion mode, fCK =f SK = 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f CK =f SK = 5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R S =2 5Ω, source impedance for V REF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.048V common-mode voltage, and 10(t CK) acquisition time unless otherwise specified. Boldface limits apply for TA =T J =T MIN to TMAX; all other limits T A =T J = 25˚C. (Notes 7, 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits (Note 11) Units (Limits) STATIC CONVERTER CHARACTERISTICS +INL Positive Integral Linearity Error 8-bit + sign mode (Note 12) ±1/2 LSB (max) −INL Negative Integral Linearity Error 8-bit + sign mode (Note 12) ±1/2 LSB (max) DNL Differential Non-Linearity 8-bit + sign mode ±3/4 LSB (max) Positive Full-Scale Error 8-bit + sign mode (Note 12) ±1/2 LSB (max) Negative Full-Scale Error 8-bit + sign mode (Note 12) ±1/2 LSB (max) Offset Error 8-bit + sign mode, after Auto-Zero (Note 13) ±1/2 LSB (max) VIN( + )=V IN(−) = + 2.048V TUE Total Unadjusted Error 8-bit + sign mode after Auto-Zero ±3/4 LSB (max) (Notes 12, 13, 14) Multiplexer Channel to Channel Matching ±0.05 LSB Power Supply Sensitivity V + = +5V ±10% VREF = +4.096V Offset Error ±0.5 ±1 LSB (max) + Full-Scale Error ±0.5 ±1.5 LSB (max) − Full-Scale Error ±0.5 ±1.5 LSB (max) + Integral Linearity Error ±0.5 LSB − Integral Linearity Error ±0.5 LSB Output Data from (Note 20) +10 LSB (max) “12-Bit Conversion of Offset” −10 LSB (min) (see Table 5) Output Data from (Note 20) 4095 LSB (max) “12-Bit Conversion of Full-Scale” 4093 LSB (min) (see Table 5) UNIPOLAR DYNAMIC CONVERTER CHARACTERISTICS S/(N+D) Signal-to-Noise Plus f IN = 1 kHz, V IN =5V PP,V REF + = 5.0V 69.4 dB Distortion Ratio f IN = 20 kHz, V IN =5V PP,V REF + = 5.0V 68.3 dB fIN = 40 kHz, V IN =5V PP,V REF+ = 5.0V 65.7 dB −3 dB Full Power Bandwidth V IN =5V PP, where S/(N+D) drops 3 dB 31 kHz DIFFERENTIAL DYNAMIC CONVERTER CHARACTERISTICS S/(N+D) Signal-to-Noise Plus f IN = 1 kHz, V IN = ±5V, VREF + = 5.0V 77.0 dB Distortion Ratio f IN = 20 kHz, V IN = ±5V, VREF + = 5.0V 73.9 dB fIN = 40 kHz, V IN = ±5V, VREF + = 5.0V 67.0 dB −3 dB Full Power Bandwidth V IN = ±5V, where S/(N+D) drops 3 dB 40 kHz REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS C REF Reference Input Capacitance 85 pF CA/D A/DIN1 and A/DIN2 Analog 75 pF Input Capacitance A/DIN1 and A/DIN2 Analog V IN = +5.0V or ±0.1 ±1.0 µA (max) Input Leakage Current V IN =0 V CH0–CH7 and COM GND − 0.05 V (min) Input Voltage VA+ + 0.05 V (max) ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 www.national.com 6

Converter Electrical Characteristics (Continued) The following specifications apply for V + =V A+=V D+ = +5.0 V DC,V REF+ = +4.096 V DC,V REF−=0V DC, 12-bit + sign conver- sion mode, fCK =f SK = 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f CK =f SK = 5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R S =2 5Ω, source impedance for V REF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.048V common-mode voltage, and 10(t CK) acquisition time unless otherwise specified. Boldface limits apply for TA =T J =T MIN to TMAX; all other limits T A =T J = 25˚C. (Notes 7, 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits (Note 11) Units (Limits) REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS C CH CH0–CH7 and COM Input Capacitance 10 pF CMUXOUT MUX Output Capacitance 20 pF Off Channel Leakage (Note 16) On Channel = 5V and −0.01 −0.3 µA (min) CH0–CH7 and COM Pins Off Channel = 0V On Channel = 0V and 0.01 0.3 µA (max) Off Channel = 5V On Channel Leakage (Note 16) On Channel = 5V and 0.01 0.3 µA (max) CH0–CH7 and COM Pins Off Channel = 0V On Channel = 0V and −0.01 −0.3 µA (min) Off Channel = 5V MUXOUT1 and MUXOUT2 V MUXOUT = 5.0V or 0.01 0.3 µA (max) Leakage Current V MUXOUT =0 V RON MUX On Resistance V IN = 2.5V and 850 1150 Ω (max) VMUXOUT = 2.4V RON Matching Channel V IN = 2.5V and 5 % to Channel V MUXOUT = 2.4V Channel to Channel Crosstalk V IN =5V PP,f IN = 40 kHz −72 dB MUX Bandwidth 90 kHz DC and Logic Electrical Characteristics The following specifications apply for V + =V A+=V D+ = +5.0 V DC,V REF+ = +4.096 V DC,V REF−=0V DC, 12-bit + sign conver- sion mode, fCK =f SK = 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f CK =f SK = 5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R S =2 5Ω, source impedance for V REF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.048V common-mode voltage, and 10(t CK) acquisition time unless otherwise specified. Bold- face limits apply for T A =T J =T MIN to TMAX; all other limits T A =T J = 25˚C. (Notes 7, 8, 9) Symbol Parameter Conditions Typical Limits Units (Note 10) (Note 11) (Limits) CCLK, CS, CONV, DI, PD AND SCLK INPUT CHARACTERISTICS VIN(1) Logical “1” Input Voltage V + = 5.5V 2.0 V (min) VIN(0) Logical “0” Input Voltage V + = 4.5V 0.8 V (max) IIN(1) Logical “1” Input Current V IN = 5.0V 0.005 1.0 µA (max) IIN(0) Logical “0” Input Current V IN = 0V −0.005 −1.0 µA (min) DO, EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS VOUT(1) Logical “1” Output Voltage V + = 4.5V, I OUT = −360 µA 2.4 V (min) V+ = 4.5V, I OUT = − 10 µA 4.25 V (min) VOUT(0) Logical “0” Output Voltage V + = 4.5V, I OUT = 1.6 mA 0.4 V (max) IOUT TRI-STATE® Output Current V OUT = 0V −0.1 −3.0 µA (max) VOUT = 5V 0.1 3.0 µA (max) +ISC Output Short Circuit Source Current V OUT =0 V 1 4 6.5 mA (min) −ISC Output Short Circuit Sink Current V OUT =V D+1 6 8.0 mA (min) POWER SUPPLY CHARACTERISTICS I D+ Digital Supply Current Awake 1.6 2.5 mA (max) ADC12030, ADC12032, ADC12034 CS = HIGH, Powered Down, CCLK on 600 µA ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 www.national.com7

DC and Logic Electrical Characteristics (Continued) The following specifications apply for V + =V A+=V D+ = +5.0 V DC,V REF+ = +4.096 V DC,V REF−=0V DC, 12-bit + sign conver- sion mode, fCK =f SK = 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f CK =f SK = 5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R S =2 5Ω, source impedance for V REF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.048V common-mode voltage, and 10(t CK) acquisition time unless otherwise specified. Bold- face limits apply for T A =T J =T MIN to TMAX; all other limits T A =T J = 25˚C. (Notes 7, 8, 9) Symbol Parameter Conditions Typical Limits Units (Note 10) (Note 11) (Limits) POWER SUPPLY CHARACTERISTICS and ADC12038 CS = HIGH, Powered Down, CCLK off 20 µA Digital Supply Current Awake 2.3 3.2 mA ADC12H030, ADC12H032, CS = HIGH, Powered Down, CCLK on 0.9 mA ADC12H034 and ADC12H038 CS = HIGH, Powered Down, CCLK off 20 µA IA+ Positive Analog Supply Current Awake 2.7 4.0 mA (max) CS = HIGH, Powered Down, CCLK on 10 µA CS = HIGH, Powered Down, CCLK off 0.1 µA IREF Reference Input Current Awake 70 µA CS = HIGH, Powered Down 0.1 µA The following specifications apply for V + =V A+=V D+ = +5.0 V DC,V REF+ = +4.096 V DC,V REF−=0V DC, 12-bit + sign conver- sion mode, tr =t f = 3 ns, f CK =f SK = 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f CK =f SK =5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R S =2 5Ω, source impedance for V REF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.048V common-mode voltage, and 10(t CK) acquisition time unless otherwise specified. Bold- face limits apply for T A =T J =T MIN to TMAX; all other limits T A =T J = 25˚C. (Note 17) Symbol Parameter Conditions Typical (Note 10) ADC12H030/2/4/8 ADC12030/2/4/8 Units (Limits)Limits Limits (Note 11) (Note 11) fCK Conversion Clock 10 85 MHz (max) (CCLK) Frequency 1 MHz (min) fSK Serial Data Clock 10 85 MHz (max) SCLK Frequency 0 Hz (min) Conversion Clock 40 40 % (min) Duty Cycle 60 60 % (max) Serial Data Clock 40 40 % (min) Duty Cycle 60 60 % (max) t C Conversion Time 12-Bit + Sign or 12-Bit 44(t CK) 44(tCK) 44(t CK) (max) 5.5 8.8 µs (max) 8-Bit + Sign or 8-Bit 21(t CK) 21(tCK) 21(t CK) (max) 2.625 4.2 µs (max) ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 www.national.com 8

The following specifications apply for V + =V A+=V D+ = +5.0 V DC,V REF+ = +4.096 V DC,V REF−=0V DC, 12-bit + sign conver- sion mode, tr =t f = 3 ns, f CK =f SK = 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f CK =f SK =5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R S =2 5Ω, source impedance for V REF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.048V common-mode voltage, and 10(t CK) acquisition time unless otherwise specified. Bold- face limits apply for T A =T J =T MIN to TMAX; all other limits T A =T J = 25˚C. (Note 17) Symbol Parameter Conditions Typical (Note 10) ADC12H030/2/4/8 ADC12030/2/4/8 Units (Limits)Limits Limits (Note 11) (Note 11) tA Acquisition Time 6 Cycles Programmed 6(t CK) 6(tCK) 6(t CK) (min) (Note 19) 7(tCK) 7(t CK) (max) 0.75 1.2 µs (min) 0.875 1.4 µs (max)

10 Cycles Programmed 10(t CK) 10(tCK) 10(t CK) (min)

11(tCK) 11(t CK) (max) 1.25 2.0 µs (min) 1.375 2.2 µs (max)

18 Cycles Programmed 18(t CK) 18(tCK) 18(t CK) (min)

19(tCK) 19(t CK) (max) 2.25 3.6 µs (min) 2.375 3.8 µs (max)

34 Cycles Programmed 34(t CK) 34(tCK) 34(t CK) (min)

35(tCK) 35(t CK) (max) 4.25 6.8 µs (min) 4.375 7.0 µs (max) tCKAL Self-Calibration Time 4944(t CK) 4944(tCK) 4944(t CK) (max) 618.0 988.8 µs (max) tAZ Auto-Zero Time 76(t CK) 76(tCK) 76(t CK) (max) 9.5 15.2 µs (max) tSYNC Self-Calibration 2(t CK) 2(tCK) 2(t CK) (min) or Auto-Zero 3(tCK) 3(t CK) (max) Synchronization Time 0.250 0.40 µs (min) from DOR 0.375 0.60 µs (max) tDOR DOR High Time 9(t SK) 9(tSK) 9(t SK) (max) when CS is Low 1.125 1.8 µs (max) Continuously for Read Data and Software Power Up/Down t CONV CONV Valid Data Time 8(tSK) 8(tSK) 8(t SK) (max) 1.0 1.6 µs (max) The following specifications apply for V + =V A+=V D+ = +5.0 V DC,V REF+ = +4.096 V DC,V REF−=0V DC, 12-bit + sign conver- sion mode, tr =t f = 3 ns, f CK =f SK = 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f CK =f SK =5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R S =2 5Ω, source impedance for V REF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.048V common-mode voltage, and 10(t CK) acquisition time unless otherwise specified. Bold- face limits apply for T A =T J =T MIN to TMAX; all other limits T A =T J = 25˚C. (Note 17) Symbol Parameter Conditions Typical (Note 10) Limits (Note 11) Units (Limits) tHPU Hardware Power-Up Time, Time from 140 250 µs (max) PD Falling Edge to EOC Rising Edge tSPU Software Power-Up Time, Time from Serial Data Clock Falling Edge to 140 250 µs (max) ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 www.national.com9

The following specifications apply for V + =V A+=V D+ = +5.0 V DC,V REF+ = +4.096 V DC,V REF−=0V DC, 12-bit + sign conver- sion mode, tr =t f = 3 ns, f CK =f SK = 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f CK =f SK =5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R S =2 5Ω, source impedance for V REF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.048V common-mode voltage, and 10(t CK) acquisition time unless otherwise specified. Bold- face limits apply for T A =T J =T MIN to TMAX; all other limits T A =T J = 25˚C. (Note 17) Symbol Parameter Conditions Typical (Note 10) Limits (Note 11) Units (Limits) EOC Rising Edge tACC Access Time Delay from 20 50 ns (max) CS Falling Edge to DO Data Valid tSET-UP Set-Up Time of CS Falling Edge to 30 ns (min) Serial Data Clock Rising Edge tDELAY Delay from SCLK Falling 0 5 ns (min) Edge to CS Falling Edge t1H,t 0H Delay from CS Rising Edge to RL = 3k, C L = 100 pF 40 100 ns (max) DO TRI-STATE tHDI DI Hold Time from Serial Data 5 15 ns (min) Clock Rising Edge tSDI DI Set-Up Time from Serial Data 5 10 ns (min) Clock Rising Edge tHDO DO Hold Time from Serial Data R L = 3k, C L = 100 pF 25 50 ns (max) Clock Falling Edge 5 ns (min) tDDO Delay from Serial Data Clock 35 50 ns (max) Falling Edge to DO Data Valid tRDO DO Rise Time, TRI-STATE to High R L = 3k, C L = 100 pF 10 30 ns (max) DO Rise Time, Low to High 10 30 ns (max) tFDO DO Fall Time, TRI-STATE to Low R L = 3k, C L = 100 pF 12 30 ns (max) DO Fall Time, High to Low 12 30 ns (max) tCD Delay from CS Falling Edge 25 45 ns (max) to DOR Falling Edge tSD Delay from Serial Data Clock Falling 25 45 ns (max) Edge to DOR Rising Edge CIN Capacitance of Logic Inputs 10 pF COUT Capacitance of Logic Outputs 20 pF Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characterist ics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the lis ted test conditions. Note 2: All voltages are measured with respect to GND, unless otherwise specified. Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > VA+o rV D+), the current at that pin should be limited to 30 mA. The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four. Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, θJA and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD =( TJmax − TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJmax = 150˚C. The typical thermal resistance ( θJA) of these parts when board mounted follow: Thermal Part Number Resistance θJA ADC12H030CIWM, ADC12030CIWM 70˚C/W ADC12H032CIWM, ADC12032CIWM 64˚C/W ADC12H034CIN, ADC12034CIN 42˚C/W ADC12H034CIWM, ADC12034CIWM 57˚C/W ADC12H034CIMSA 97˚C/W ADC12H038CIWM, ADC12038CIWM 50˚C/W ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 www.national.com 10

Note 5: The human body model is a 100 pF capacitor discharged through a 1.5 k Ω resistor into each pin. Semiconductor Linear Data Book for other methods of soldering surface mount devices. VDC to ensure accurate conversions. Note 9: With the test condition for V REF (VREF+−V REF−) given as +4.096V, the 12-bit LSB is 1.0 mV and the 8-bit LSB is 16.0 mV. Note 10: Typicals are at TJ =T A = 25˚C and represent most likely parametric norm. Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). full-scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero (see Figures 2, 3). between 1 to 0 and 0 to +1 (see Figure 4). Note 14: Total unadjusted error includes offset, full-scale, linearity and multiplexer errors. Note 15: The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together. Note 16: Channel leakage current is measured after the channel selection. result in a maximum repeatability uncertainty of 0.2 LSB. Note 19: If SCLK and CCLK are driven from the same clock source, then t A is 6, 10, 18 or 34 clock periods minimum and maximum. data from these modes are not an indication of the accuracy of a conversion result. FIGURE 1. Transfer Characteristic

Typical Performance Characteristics The following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified. The performance for 8-bit + sign mode is equal to or better than shown. (Note 9) Linearity Error Change vs Clock Frequency Linearity Error Change vs Temperature Linearity Error Change vs Reference Voltage 01135453 01135454 01135455 Linearity Error Change vs Supply Voltage Full-Scale Error Change vs Clock Frequency Full-Scale Error Change vs Temperature 01135456 01135457 01135458 Full-Scale Error Change vs Reference Voltage Full-Scale Error Change vs Supply Voltage Zero Error Change vs Clock Frequency 01135459 01135460 01135461 Zero Error Change vs Temperature Zero Error Change vs Reference Voltage Zero Error Change vs Supply Voltage 01135462 01135463 01135464 ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 www.national.com13

Typical Performance Characteristics The following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified. The performance for 8-bit + sign mode is equal to or better than shown. (Note 9) (Continued) Analog Supply Current vs Temperature Digital Supply Current vs Clock Frequency Digital Supply Current vs Temperature 01135465 01135466 01135467 Typical Dynamic Performance Characteristics The following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified. Bipolar Spectral Response with 1 kHz Sine Wave Input Bipolar Spectral Response with 10 kHz Sine Wave Input Bipolar Spectral Response with 20 kHz Sine Wave Input 01135468 01135469 01135470 Bipolar Spectral Response with 30 kHz Sine Wave Input Bipolar Spectral Response with 40 kHz Sine Wave Input Bipolar Spectral Response with 50 kHz Sine Wave Input 01135471 01135472 01135473 ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 www.national.com 14

Typical Dynamic Performance Characteristics The following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified. (Continued) Bipolar Spurious Free Dynamic Range Unipolar Signal-to-Noise Ratio vs Input Frequency Unipolar Signal-to-Noise + Distortion Ratio vs Input Frequency 01135474 01135475 01135476 Unipolar Signal-to-Noise + Distortion Ratio vs Input Signal Level Unipolar Spectral Response with 1 kHz Sine Wave Input Unipolar Spectral Response with 10 kHz Sine Wave Input 01135477 01135478 01135479 Unipolar Spectral Response with 20 kHz Sine Wave Input Unipolar Spectral Response with 30 kHz Sine Wave Input Unipolar Spectral Response with 40 kHz Sine Wave Input 01135480 01135481 01135482 ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 www.national.com15

Typical Dynamic Performance Characteristics The following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified. (Continued) Unipolar Spectral Response with 50 kHz Sine Wave Input 01135483 Test Circuits DO “TRI-STATE” (t1H,t OH) DO except “TRI-STATE” 01135403 01135404 Leakage Current 01135405 Timing Diagrams DO Falling and Rising Edge DO “TRI-STATE” Falling and Rising Edge 01135418 01135419 ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 www.national.com 16

Timing Diagrams (Continued) DI Data Input Timing 01135420 DO Data Output Timing Using CS 01135421 DO Data Output Timing with CS Continuously Low 01135422 ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 www.national.com17

Timing Diagrams (Continued) ADC12038 Auto Cal or Auto Zero 01135423 Note: DO output data is not valid during this cycle. ADC12038 Read Data without Starting a Conversion Using CS 01135424 ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 www.national.com 18

Timing Diagrams (Continued) ADC12038 Read Data without Starting a Conversion with CS Continuously Low 01135425 ADC12038 Conversion Using CS with 8-Bit Digital Output Format 01135426 ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 www.national.com19

Timing Diagrams (Continued) ADC12038 Conversion Using CS with 16-Bit Digital Output Format 01135451 ADC12038 Conversion with CS Continuously Low and 8-Bit Digital Output Format 01135428 ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 www.national.com 20

Timing Diagrams (Continued) ADC12038 Conversion with CS Continuously Low and 16-Bit Digital Output Format 01135429 ADC12038 Software Power Up/Down Using CS with 16-Bit Digital Output Format 01135452 ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 www.national.com21

Timing Diagrams (Continued) ADC12038 Software Power Up/Down with CS Continuously Low and 16-Bit Digital Output Format 01135431 ADC12038 Hardware Power Up/Down 01135432 Note: Hardware power up/down may occur at any time. If PD is high while a conversion is in progress that conversion will be corrupted and erroneous data will be stored in the output shift register. ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 www.national.com 22

sign, 12 bits, 12 bits plus sign, or greater. FIGURE 5. Protecting the MUXOUT1, MUXOUT2, A/DIN1 and A/DIN2 Analog Pins

TABLE 1. Data Out Formats

17 X X X X Sign MSB 10 9 8 7 654321 L S B

9 Sign MSB 6 5 4 3 2 1 LSB

17 LSB 1 2 3 4 5 6 7 8 9 10 MSB Sign X X X X

9 LSB 1 2 3 4 5 6 MSB Sign

FIGURE 6. Recommended Power Supply Bypassing and Grounding

TABLE 1. Data Out Formats (Continued)

8 M S B 65 43 21 L S B

8 L S B 12 34 56 M S B

TABLE 2. ADC12038 Multiplexer Addressing

TABLE 3. ADC12034 Multiplexer Addressing TABLE 4. ADC12032 and ADC12030 Multiplexer Addressing TABLE 5. Mode Programming

TABLE 5. Mode Programming (Continued) Note: The A/D powers up with no Auto Cal, no Auto Zero, 10 CCLK acquisition time, 12-bit + sign conversion, power up, 12- or 13-bit MSB first, and user mode. TABLE 6. Conversion/Read Data Only Mode Programming L H L Read Only (Previous DO Format). No Conversion. TABLE 7. Status Register

1.0 DIGITAL INTERFACE

1.1 Interface Concepts

The first instruction input to the A/D via DI initiates Auto Cal. during a conversion, that conversion is prematurely ended. instruction is issued to the A/D. FIGURE 7. Typical Power Supply Power Up Sequence

Application Hints (Continued)

1.2 Changing Configuration

The configuration of the ADC12030/2/4/8 on power up de- faults to 12-bit plus sign resolution, 12- or 13-bit MSB First,

10 CCLK acquisition time, user mode, no Auto Cal, no Auto

Zero, and power up mode. Changing the aquisition time and turning the sign bit on and off requires an 8-bit instruction to be issued to the ADC. This instruction will not start a con- version. The instructions that select a multiplexer address and format the output data do start a conversion. Figure 8 describes an example of changing the configuration of the ADC12030/2/4/8. During I/O sequence 1, the instruction on DI configures the ADC12030/2/4/8 to do a conversion with 12-bit +sign reso- lution. Notice that when the 6 CCLK Acquisition and Data Out without Sign instructions are issued to the ADC, I/O sequences 2 and 3, a new conversion is not started. The data output during these instructions is from conversion N which was started during I/O sequence 1. The Configuration Modification timing diagram describes in detail the sequence of events necessary for a Data Out without Sign, Data Out with Sign, or 6/10/18/34 CCLK Acquisition time mode selec- tion. Table 5describes the actual data necessary to be input to the ADC to accomplish this configuration modification. The next instruction, shown in Figure 8, issued to the A/D starts conversion N+1 with 8 bits of resolution formatted MSB first. Again the data output during this I/O cycle is the data from conversion N. The number of SCLKs applied to the A/D during any conver- sion I/O sequence should vary in accord with the data out word format chosen during the previous conversion I/O se- quence. The various formats and resolutions available are shown in Table 1.I n Figure 8, since 8-bit without sign MSB first format was chosen during I/O sequence 4, the number of SCLKs required during I/O sequence 5 is 8. In the follow- ing I/O sequence the format changes to 12-bit without sign MSB first; therefore the number of SCLKs required during I/O sequence 6 changes accordingly to 12.

1.3 CS Low Continuously Considerations

When CS is continuously low, it is important to transmit the exact number of SCLK pulses that the ADC expects. Not doing so will desynchronize the serial communications to the ADC. When the supply power is first applied to the ADC, it will expect to see 13 SCLK pulses for each I/O transmission. The number of SCLK pulses that the ADC expects to see is the same as the digital output word length. The digital output word length is controlled by the Data Out (DO) format. The DO format maybe changed any time a conversion is started or when the sign bit is turned on or off. The table below details out the number of clock periods required for different DO formats: Number of DO Format SCLKs Expected 8-Bit MSB or LSB First SIGN OFF 8 SIGN ON 9 12-Bit MSB or LSB First SIGN OFF 12 SIGN ON 13 16-Bit MSB or LSB first SIGN OFF 16 SIGN ON 17 If erroneous SCLK pulses desynchronize the communica- tions, the simplest way to recover is by cycling the power supply to the device. Not being able to easily resynchronize the device is a shortcoming of leaving CS low continuously. The number of clock pulses required for an I/O exchange may be different for the case when CS is left low continu- ously vs the case when CS is cycled. Take the I/O sequence detailed in Figure 7(Typical Power Supply Sequence) as an example. The table below lists the number of SCLK pulses required for each instruction: Instruction CS Low CS Strobed Continuously Auto Cal 13 SCLKs 8 SCLKs Read Status 13 SCLKs 8 SCLKs Read Status 13 SCLKs 8 SCLKs 12-Bit + Sign Conv 1 13 SCLKs 8 SCLKs 12-Bit + Sign Conv 2 13 SCLKs 13 SCLKs

1.4 Analog Input Channel Selection

The data input on DI also selects the channel configuration for a particular A/D conversion (see Tables 2, 3, 4and Table 5). In Figure 8the only times when the channel configuration could be modified would be during I/O sequences 1, 4, 5 and 6. Input channels are reselected before the start of each new conversion. Shown below is the data bit stream required on DI, during I/O sequence number 4 in Figure 8, to set CH1 as the positive input and CH0 as the negative input for the different versions of ADCs: Part DI Data Number DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 ADC12H030 LHLLHLXX ADC12030 ADC12H032 LHLLHLXX ADC12032 ADC12H034 LHLLLHLX ADC12034 ADC12H038 LHLLLLHL ADC12038 Where X can be a logic high (H) or low (L).

1.5 Power Up/Down

The ADC may be powered down at any time by taking the PD pin HIGH or by the instruction input on DI (see Tables 5, 6, and the Power Up/Down timing diagrams). When the ADC is powered down in this way, the circuitry necessary for an A/D conversion is deactivated. The circuitry necessary for digital I/O is kept active. Hardware power up/down is con- trolled by the state of the PD pin. Software power-up/down is controlled by the instruction issued to the ADC. If a software power up instruction is issued to the ADC while a hardware power down is in effect (PD pin high) the device will remain in the power-down state. If a software power down instruc- tion is issued to the ADC while a hardware power up is in effect (PD pin low), the device will power down. When the device is powered down by software, it may be powered up by either issuing a software power up instruction or by taking PD pin high and then low. If the power down command is issued during an A/D conversion, that conversion is dis- rupted. Therefore, the data output after power up cannot be relied upon. ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 www.national.com 28

1.6 User Mode and Test Mode

instruction sequence must be issued to the ADC using CS. the required state before a conversion is started.

1.7 Reading the Data Without Starting a Conversion

2.0 DESCRIPTION OF THE ANALOG MULTIPLEXER

FIGURE 8. Changing the ADC’s Conversion Configuration

4 Differential

8 Single-Ended Channels

signed positive or negative polarity. the different versions of A/Ds.

2.1 Biasing for Various Multiplexer Configurations

One LSB is equal to 1 mV (4.1V/4096 LSBs). FIGURE 11. Single-Ended Biasing

shown in Figure 12shows a signal AC coupled to the ADC. periods, the input biasing resistor needs to be 600 Ω or less.

5 MHz CCLK frequency) would allow the 600Ω to increase to

upon the current required by the op amp biasing circuitry. for this case is equal to (4.1V/4096) = 1 mV. FIGURE 12. Pseudo-Differential Biasing with the Signal Source AC Coupled Directly into the ADC

3.0 REFERENCE VOLTAGE

input voltage and the ADC reference voltage move together. age induced full-scale errors. reference ladder should not go below 0.5V or above 3.0V. FIGURE 15. Fully Differential Biasing FIGURE 16. Low Drift Extremely

4.0 ANALOG INPUT VOLTAGE RANGE

5.0 INPUT CURRENT

on resistance is typically 750 Ω.

6.0 INPUT SOURCE RESISTANCE

12 Bit + Sign N

and ended by a rising edge of CCLK (see timing diagrams).

7.0 INPUT BYPASS CAPACITANCE

grade the conversion accuracy.

8.0 NOISE

9.0 POWER SUPPLIES

conversion errors; the comparator will respond to the noise. close as possible to these pins. FIGURE 17. VREF Operating Range

10.0 GROUNDING

mount capacitors and 10 µF (C3) tantalum capacitor.

11.0 CLOCK SIGNAL LINE ISOLATION

12.0 THE CALIBRATION CYCLE

sampled data comparator and any linearity and gain errors. offset, and linearity errors down to the specified limits. the Typical Performance Characteristics).

13.0 THE AUTO-ZERO CYCLE

14.0 DYNAMIC PERFORMANCE

sures of the A/D converter’s capability. FIGURE 18. Ideal Ground Plane

Application Hints (Continued) are shown in the table of Electrical Characteristics, and spectral plots of S/(N + D) are included in the typical perfor- mance curves. The A/D converter’s noise and distortion levels will change with the frequency of the input signal, with more distortion and noise occurring at higher signal frequencies. This can be seen in the S/(N + D) versus frequency curves. Effective number of bits can also be useful in describing the A/D’s noise performance. An ideal A/D converter will have some amount of quantization noise, determined by its reso- lution, which will yield an optimum S/N ratio given by the following equation: S/N = (6.0 2xn+ 1.76) dB where n is the A/D’s resolution in bits. S/(N + D) (or SINAD) is a combination of S/N (or SNR) and distortion and is considered to be an overall measure of an A/D converter performance. S/(N + D) is defined as: and the effective number of Bits (ENOB) is defined as: As an example, this device with a differential signed 5V, 1 kHz sine wave input signal will typically have a S/(N + D) of 77 dB, which is equivalent to 12.5 effective bits.

15.0 AN RS232 SERIAL INTERFACE

Shown on the following page is a schematic for an RS232 interface to any IBM and compatible PCs. The DTR, RTS, and CTS RS232 signal lines are buffered via level transla- tors and connected to the ADC12038’s DI, SCLK, and DO pins, respectively. The D flip flop drives the CS control line. 01135444 Note: VA+,V D+, and VREF+ on the ADC12038 each have 0.01 µF and 0.1 µF chip caps, and 10 µF tantalum caps. All logic devices are bypassed with 0.1 µF caps. The assignment of the RS232 port is shown below B7 B6 B5 B4 B3 B2 B1 B0 COM1 Input Address 3FE X X X CTS X X X X Output Address 3FC X X X 0 X X RTS DTR A sample program, written in Microsoft QuickBasic, is shown on the next page. The program prompts for data mode select instruction to be sent to the A/D. This can be found from the Mode Programming table shown earlier. The data should be entered in “1”s and “0”s as shown in the table with DI0 first. Next the program prompts for the number of SCLKs required for the programmed mode select instruction. For instance, to send all “0”s to the A/D, selects CH0 as the +input, CH1 as the −input, 12-bit conversion, and 13-bit MSB first data output format (if the sign bit was not turned off by a previous instruction). This would require 13 SCLK periods since the output data format is 13 bits. The part powers up with No Auto Cal, No Auto Zero, 10 CCLK Acquisition Time, 12-bit conversion, data out with sign, power up, 12- or 13-bit MSB first, and user mode. Auto Cal, Auto Zero, Power Up and ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 www.national.com 36

Application Hints (Continued) Power Down instructions do not change these default set- tings. The following power up sequence should be followed: 1. Run the program 2. Prior to responding to the prompt apply the power to the ADC12038 3. Respond to the program prompts It is recommended that the first instruction issued to the ADC12038 be Auto Cal (see Section 1.1). ’variables DOL=Data Out word length, DI=Data string for A/D DI input,⇒ ’ DO=A/D result string ’SET CS# HIGH OUT &H3FC, (&H2 OR INP (&H3FC)) ’set RTS HIGH⇒ OUT &H3FC, (&HFE AND INP(&H3FC)) ’set DTR LOW⇒ OUT &H3FC, (&HFD AND INP(&H3FC)) ’set RTS LOW⇒ OUT &H3FC, (&HEF AND INP(&H3FC)) ’set B4 low⇒ LINE INPUT <&ldquo>DI data for ADC12038 (see Mode Table on data sheet)”; DI$⇒ INPUT <&ldquo>ADC12038 output word length ’SET CS# HIGH OUT &H3FC, (&H2 OR INP (&H3FC)) ’set RTS HIGH⇒ OUT &H3FC, (&HFE AND INP(&H3FC)) ’set DTR LOW⇒ OUT &H3FC, (&HFD AND INP(&H3FC)) ’set RTS LOW⇒ ’SET CS# LOW OUT &H3FC, (&H2 OR INP (&H3FC)) ’set RTS HIGH⇒ OUT &H3FC, (&H1 OR INP(&H3FC)) ’set DTR HIGH⇒ OUT &H3FC, (&HFD AND INP(&H3FC)) ’set RTS LOW⇒ DO$= <&ldquo> ” ’reset DO variable OUT &H3FC, (&H1 OR INP(&H3FC)) ’SET DTR HIGH⇒ OUT &H3FC, (&HFD AND INP(&H3FC)) ’SCLK low⇒ FOR N=1 TO 8 Temp$=MID$(DI$,N,1) OUT &H3FC,(&H1 OR INP(&H3FC)) ELSE OUT &H3FC, (&HFE AND INP(&H3FC)) END IF ’out DI⇒ OUT &H3FC, (&H2 OR INP(&H3FC)) ’SCLK high⇒ IF (INP(&H3FE) AND 16)=16 THEN ELSE END IF ’input DO OUT &H3FC, (&H1 OR INP(&H3FC)) ’SET DTR HIGH⇒ OUT &H3FC, (&HFD AND INP(&H3FC)) ’SCLK low⇒ NEXT N IF DOL>8 THEN FOR N=9 TO DOL OUT &H3FC, (&H1 OR INP(&H3FC)) ’SET DTR HIGH⇒ OUT &H3FC, (&HFD AND INP(&H3FC)) ’SCLK low⇒ OUT &H3FC, (&H2 OR INP(&H3FC)) ’SCLK high⇒ IF (INP(&H3FE) AND &H10)=&H10 THEN ELSE END IF NEXT N END IF OUT &H3FC, (&HFA AND INP(&H3FC)) ’SCLK low and DI high⇒ FOR N=1 TO 500 NEXT N PRINT DO$ INPUT <&ldquo>Enter <&ldquo>C” to convert else <&ldquo>RETURN” to alter DI data”; s$⇒ GOTO 20 ELSE GOTO 10 END IF END ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 www.national.com37

Physical Dimensions inches (millimeters) unless otherwise noted Order Number ADC12030CIWM or ADC12H030CIWM Order Number ADC12032CIWM or ADC12H032CIWM ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 www.national.com 38

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Order Number ADC12034CIWM or ADC12H034CIWM Order Number ADC12H034CIMSA ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 www.national.com39

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Order Number ADC12038CIWM or ADC12H038CIWM Order Number ADC12034CIN or ADC12H034CIN ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 www.national.com 40

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the righ t at any time without notice to change said circuitry and specifications.