MSA20

74ABT245 FAIRCHILD | Alldatasheet

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I Bidirectional non-inverting buffers I A and B output sink capability of 64 mA, source capability of 32 mA I Guaranteed output skew I Guaranteed multiple output switching specifications I Output switching specified for both 50 pF and 250 pF loads I Guaranteed simultaneous switching, noise level and dynamic threshold performance I Guaranteed latchup protection I High impedance glitch-free bus loading during entire power up and power down cycle I Non-destructive hot insertion capability I Disable time is less than enable time to avoid bus contention Ordering Code: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. Order Number Package Package DescriptionNumber 74ABT245CSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74ABT245CSJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ABT245CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74ABT245CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ABT245CMTCX_NL (Note 1) MTC20 Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ABT245CPC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

www.fairchildsemi.com 2 74ABT245 Connection Diagram Pin Descriptions Logic Symbol Truth Table H /c32 HIGH Voltage Level L /c32 LOW Voltage Level X /c32 Immaterial Logic Diagram Pin Names Description OE Output Enable Input (Active LOW) T/R Transmit/Receive Input A0–A7 Side A Inputs or 3-STATE Outputs B0–B7 Side B Inputs or 3-STATE Outputs Inputs Output OE T/R L L Bus B Data to Bus A L H Bus A Data to Bus B H X HIGH Z State

3 www.fairchildsemi.com 74ABT245 Absolute Maximum Ratings(Note 2) Recommended Operating Conditions Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs Storage Temperature /c16 65/c113 C to /c14 150/c113 C Ambient Temperature under Bias /c16 55/c113 C to /c14 125/c113 C Junction Temperature under Bias /c16 55/c113 C to /c14 150/c113 C VCC Pin Potential to Ground Pin /c16 0.5V to /c14 7.0V Input Voltage (Note 3) /c16 0.5V to /c14 7.0V Input Current (Note 3) /c16 30 mA to /c14 5.0 mA Voltage Applied to Any Output in the Disabled or Power-off State /c16 0.5V to 5.5V in the HIGH State /c16 0.5V to VCC Current Applied to Output in LOW State (Max) twice the rated I OL (mA) DC Latchup Source Current /c16 500 mA Over Voltage Latchup (I/O) 10V Free Air Ambient Temperature /c16 40/c113 C to /c14 85/c113 C Supply Voltage /c14 4.5V to /c14 5.5V Minimum Input Edge Rate (/c39 V//c39 t) Data Input 50 mV/ns Enable Input 20 mV/ns Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized HIGH Signal VIL Input LOW Voltage 0.8 V Recognized LOW Signal VCD Input Clamp Diode Voltage /c16 1.2 V Min I IN /c32 /c16 18 mA (OE, T/R) VOH Output HIGH Voltage 2.5 V Min I OH /c32 /c16 3 mA (An, Bn)

2.0 V Min I OH /c32 /c16 32 mA (An, Bn)

VOL Output LOW Voltage 0.55 V Min I OL /c32 64 mA (An, Bn) IIH Input HIGH Current 1 /c80 AM a x VIN /c32 2.7V (OE, T/R) 1V IN /c32 VCC (OE, T/R) IBVI Input HIGH Current Breakdown Test 7 /c80 AM a x V IN /c32 7.0V (OE, T/R) IBVIT Input HIGH Current Breakdown Test (I/O) 100 /c80 AM a x V IN /c32 5.5V (An, Bn) IIL Input LOW Current /c16 1 /c80 AM a x VIN /c32 0.5V (OE, T/R) /c16 1V IN /c32 0.0V (OE, T/R) VID Input Leakage Test 4.75 V 0.0 I ID /c32 1.9 /c80 A (OE, T/R) All Other Pins Grounded IIH /c14 IOZH Output Leakage Current 10 /c80 A0 /c16 5.5V VOUT /c32 2.7V (An, Bn); OE /c32 2.0V IIL /c14 I OZL Output Leakage Current /c16 10 /c80 A0 /c16 5.5V VOUT /c32 0.5V (An, Bn); OE /c32 2.0V IOS Output Short-Circuit Current /c16 100 /c16 275 mA Max V OUT /c32 0.0V (An, Bn) ICEX Output HIGH Leakage Current 50 /c80 AM a x V OUT /c32 V CC (An, Bn) IZZ Bus Drainage Test 100 /c80 A0 . 0 V OUT /c32 5.5V (An, Bn); All Others GND ICCH Power Supply Current 50 /c80 A Max All Outputs HIGH ICCL Power Supply Current 30 mA Max All Outputs LOW ICCZ Power Supply Current 50 /c80 AM a x O E /c32 VCC , T/R /c32 GND or VCC ; All Other GND or VCC ICCT Additional Outputs Enabled 2.5 mA V I /c32 V CC /c16 2.1V I CC/Input Outputs 3-STATE 2.5 mA Max OE , T/R VI /c32 VCC /c16 2.1V Outputs 3-STATE 50 /c80 A Data Input V I /c32 VCC /c16 2.1V All Others at VCC or GND. ICCD Dynamic ICC No Load 0.1 mA/ Max Outputs Open MHz OE /c32 GND, T/R /c32 GND or VCC One Bit Toggling, 50% Duty Cycle

www.fairchildsemi.com 4 74ABT245 (SOIC package) Note 4: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 5: Max number of data inputs (n) switching. n-1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD). Guaranteed, but not tested. Note 6: Max number of outputs defined as (n). n /c16 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. (SOIC and SSOP package) Extended AC Electrical Characteristics (SOIC package) Note 7: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 8: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac- itors in the standard AC load. This specification pertains to single output switching only. Note 9: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 10: The 3-STATE delays are dominated by the RC network (500/c58 , 250 pF) on the output and have been excluded from the datasheet. Symbol Parameter Min Typ Max Units VCC Conditions CL /c32 50 pF, RL /c32 500/c58 VOLP Quiet Output Maximum Dynamic VOL 0.7 1.0 V 5.0 T A /c32 25/c113 C (Note 4) VOLV Quiet Output Minimum Dynamic VOL /c16 1.3 /c16 1.0 V 5.0 T A /c32 25/c113 C (Note 4) VOHV Minimum HIGH Level Dynamic Output Voltage 2.7 3.1 V 5.0 T A /c32 25/c113 C (Note 6) VIHD Minimum HIGH Level Dynamic Input Voltage 2.0 1.7 V 5.0 T A /c32 25/c113 C (Note 5) VILD Maximum LOW Level Dynamic Input Voltage 0.9 0.6 V 5.0 T A /c32 25/c113 C (Note 5) TA /c32 /c14 25/c113 CT A /c32 /c16 55/c113 C to /c14 125/c113 CT A /c32 /c16 40/c113 C to /c14 85/c113 C Symbol Parameter VCC /c32 /c14 5V V CC /c32 4.5V–5.5V V CC /c32 4.5V–5.5V Units CL /c32 50 pF C L /c32 50 pF C L /c32 50 pF Min Typ Max Min Max Min Max ns ns ns Symbol Parameter /c16 40/c113 C to /c14 85/c113 C TA /c32 /c16 40/c113 C to /c14 85/c113 C T A /c32 /c16 40/c113 C to /c14 85/c113 C Units CL /c32 50 pF C L /c32 250 pF C L /c32 250 pF

8 Outputs Switching 1 Output Switching 8 Outputs Switching

(Note 7) (Note 8) (Note 9) Min Typ Max Min Max Min Max fTOGGLE Max Toggle Frequency 100 MHz ns ns tPHZ Output Disable Time 1.0 6.5 (Note 10) (Note 10) ns tPLZ 1.0 5.6

5 www.fairchildsemi.com 74ABT245 Skew (SOIC package) Note 11: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL ), LOW-to-HIGH (tOSLH ), or any combination switching LOW-to-HIGH and/or HIGH-to-LOW (tOST ). The specification is guaranteed but not tested. Note 12: Propagation delay variation for a given set of conditions (i.e., temperature and VCC ) from device to device. This specification is guaranteed but not tested. Note 13: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) Note 14: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 15: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. Capacitance Note 16: C I/O is measured at frequency f /c32 1 MHz, per MIL-STD-883, Method 3012. Symbol Parameter TA /c32 /c16 40/c113 C to /c14 85/c113 CT A /c32 /c16 40/c113 C to /c14 85/c113 C Units VCC /c32 4.5V–5.5V V CC /c32 4.5V–5.5V CL /c32 50 pF C L /c32 250 pF

8 Outputs Switching 8 Outputs Switching

(Note 13) (Note 14) Max Max tOSHL Pin to Pin Skew 1.3 2.3 ns (Note 11) HL Transitions tOSLH Pin to Pin Skew 1.0 1.8 ns (Note 11) LH Transitions tPS Duty Cycle 2.0 3.5 ns (Note 15) LH –HL Skew tOST Pin to Pin Skew 2.0 3.5 ns (Note 11) LH/HL Transitions tPV Device to Device Skew 2.0 3.5 ns (Note 12) LH/HL Transitions Symbol Parameter Typ Units Conditions TA /c32 25/c113 C CIN Input Capacitance 5.0 pF V CC /c32 0V (OE, T/R) CI/O (Note 16) I/O Capacitance 11.0 pF V CC /c32 5.0V (An, Bn)

7 www.fairchildsemi.com 74ABT245 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B

www.fairchildsemi.com 8 74ABT245 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D

9 www.fairchildsemi.com 74ABT245 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

www.fairchildsemi.com 10 74ABT245 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

11 www.fairchildsemi.com 74ABT245 Octal Bi-Directional Transceiver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com