MSA-0700 HP | Alldatasheet
Document overview
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- PDF pages: 4
Technical content
Features
- Cascadable 50 Ω Gain Block
- Low Operating Voltage:
4.0 V Typical Vd
- 3 dB Bandwidth: DC to 2.5 GHz
- 13.0␣ dB Typical Gain at 1.0␣ GHz MSA-0700 Chip Outline[1]
Description
The MSA-0700 is a high perfor- mance silicon bipolar Monolithic Microwave Integrated Circuit (MMIC) chip. This MMIC is designed for use as a general purpose 50 Ω gain block. Typical applications include narrow and broad band IF and RF amplifiers in commercial, industrial and military applications. Typical Biasing Configuration C block C block R bias VCC > 5 V Vd = 4.0 V RFC (Optional) IN OUT MSA The MSA-series is fabricated using HP’s 10 GHz fT, 25␣ GHz fMAX, silicon bipolar MMIC process which uses nitride self-alignment, ion implantation, and gold metalli- zation to achieve excellent performance, uniformity and reliability. The use of an external bias resistor for temperature and current stability also allows bias flexibility. The recommended assembly procedure is gold-eutectic die attach at 400°C and either wedge or ball bonding using 0.7 mil gold wire. [1] See APPLICATIONS section, “Chip Use”. Note: 1. This chip contains additional biasing options. The performance specified applies only to the bias option whose bond pads are indicated on the chip outline. Refer to the APPLICATIONS section “Silicon MMIC Chip Use” for additional information. 5965-9589E
Parameter Absolute Maximum [1] Device Current 60 mA Power Dissipation[2,3] 275 mW RF Input Power +13 dBm Junction Temperature 200 °C Storage Temperature –65 to 200 °C Thermal Resistance[2,4]: θjc = 50°C/W Notes: 1. Permanent damage may occur if any of these limits are exceeded. 2. T Mounting␣ Surface = 25°C. 3. Derate at 20 mW/°C for TMounting␣ Surface␣ > 186°C. 4. The small spot size of this technique results in a higher, though more accurate determination of θjc than do alternate methods. See MEASURE- MENTS section “Thermal Resistance” for more information. GP Power Gain (|S21|2) f = 0.1 GHz dB 13.5 ΔGP Gain Flatness f = 0.1 to 1.5 GHz dB ± 0.6 f3 dB 3 dB Bandwidth GHz 2.5 Input VSWR f = 0.1 to 2.5 GHz 2.0:1 Output VSWR f = 0.1 to 2.5 GHz 1.6:1 NF 50 Ω Noise Figure f = 1.0 GHz dB 4.5 P1 dB Output Power at 1 dB Gain Compression f = 1.0 GHz dBm 5.5 IP3 Third Order Intercept Point f = 1.0 GHz dBm 19.0 tD Group Delay f = 1.0 GHz psec 130 Vd Device Voltage V 3.6 4.0 4.4 dV/dT Device Voltage Temperature Coefficient mV/ °C –7.0 Notes: 1. The recommended operating current range for this device is 15 to 40 mA. Typical performance as a function of current is on the following page. 2. RF performance of the chip is determined by packaging and testing 10 devices per wafer in a dual ground configuration. Electrical Specifications[1], TA = 25°C Symbol Parameters and Test Conditions [2]: Id = 22 mA, ZO = 50 Ω Units Min. Typ. Max. VSWR Part Number Ordering Information Part Number Devices Per Tray MSA-0700-GP4 up to 100
- S-parameters are de-embedded from 70 mil package measured data using the package model found in the DEVICE MODELS section.
Figure 1. Typical Power Gain vs. Figure 2. Power Gain vs. Current. Figure 3. Output Power at 1 dB Gain Compression, NF and Power Gain vs. Figure 4. Output Power at 1 dB Gain Figure 5. Noise Figure vs. Frequency.
0.1 GHz
0.5 GHz
1.0 GHz
2.0 GHz
OUTPUT [1] 419 µm 16.5 mil 419 µm 16.5 mil INPUT GROUND NOT APPLICABLE Unless otherwise specified, tolerances are –13 µm/ –0.5 mils. Chip thickness is 114µm/4.5 mil. Bond Pads are 41 µm/1.6 mil typical on each side. Note 1: Output contact is made by die attaching the backside of the die.