MSA-0600 HP | Alldatasheet
Document overview
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Technical content
Features
- Cascadable 50 Ω Gain Block
- Low Operating Voltage (3.5␣ V typical Vd)
- 3 dB Bandwidth: DC to 1.0 GHz
- High Gain: 19.5 dB Typical at 0.5␣ GHz
- Low Noise Figure: 2.8␣ dB Typical at 0.5␣ GHz MSA-0600 Chip Outline[1]
Description
The MSA-0600 is a high perfor- mance silicon bipolar Monolithic Microwave Integrated Circuit (MMIC) chip. This MMIC is designed for use as a general purpose 50 Ω gain block. Typical applications include narrow and Typical Biasing Configuration C block C block R bias VCC > 5 V Vd = 3.5 V RFC (Optional) IN OUT MSA Note: 1. This chip contains additional biasing options. The performance specified applies only to the bias option whose bond pads are indicated on the chip outline. Refer to the APPLICATIONS section “Silicon MMIC Chip Use” for additional information. broad band IF and RF amplifiers in commercial, industrial and military applications. The MSA-series is fabricated using HP’s 10 GHz f T, 25␣ GHz fMAX, silicon bipolar MMIC process which uses nitride self-alignment, ion implantation, and gold metalli- zation to achieve excellent performance, uniformity and reliability. The use of an external bias resistor for temperature and current stability also allows bias flexibility. The recommended assembly procedure is gold-eutectic die attach at 400°C and either wedge or ball bonding using 0.7 mil gold wire. [1] See APPLICATIONS section, “Chip Use”. 5965-9583E
Parameter Absolute Maximum [1] Device Current 50 mA Power Dissipation[2,3] 200 mW RF Input Power +13 dBm Junction Temperature 200 °C Storage Temperature –65 to 200 °C Thermal Resistance[2,4]: θjc = 50°C/W Part Number Ordering Information Part Number Devices Per Tray MSA-0600-GP4 100 GP Power Gain (|S21|2) f = 0.1 GHz dB 20.5 ΔGP Gain Flatness f = 0.1 to 0.6 GHz dB ± 0.7 f3 dB 3 dB Bandwidth GHz 1.0 Input VSWR f = 0.1 to 1.5 GHz 1.9:1 Output VSWR f = 0.1 to 1.5 GHz 1.8:1 NF 50 Ω Noise Figure f = 0.5 GHz dB 2.8 P1 dB Output Power at 1 dB Gain Compression f = 0.5 GHz dBm 2.0 IP3 Third Order Intercept Point f = 0.5 GHz dBm 14.5 tD Group Delay f = 0.5 GHz psec 200 Vd Device Voltage V 3.1 3.5 3.9 dV/dT Device Voltage Temperature Coefficient mV/ °C –8.0 Notes: 1. The recommended operating current range for this device is 12 to 30 mA. Typical performance as a function of current is on the following page. 2. RF performance of the chip is determined by packaging and testing 10 devices per wafer in a dual ground configuration. Electrical Specifications[1], TA = 25°C Symbol Parameters and Test Conditions [2]: Id = 16 mA, ZO = 50 Ω Units Min. Typ. Max. VSWR Notes: 1. Permanent damage may occur if any of these limits are exceeded. 2. T Mounting Surface (TMS) = 25°C. 3. Derate at 20 mW/°C for TMounting␣ Surface > 190°C. 4. The small spot size of this technique results in a higher, though more accurate determination of θjc than do alternate methods. See MEASURE- MENTS section “Thermal Resistance” for more information.
- S-parameters are de-embedded from 70 mil package measured data using the package model found in the DEVICE
Figure 1. Typical Power Gain vs. Frequency, TA = 25°C, Id = 16 mA. Figure 2. Power Gain vs. Current.
0.1 GHz
0.5 GHz
1.0 GHz
2.0 GHz
Figure 5. Noise Figure vs. Frequency. Figure 4. Output Power at 1 dB Gain Figure 3. Output Power at 1 dB Gain Compression, NF and Power Gain vs.
300 µm 12.8 mil 300 µm 12.8 mil