MSA-0500 HP | Alldatasheet

Document overview

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Technical content

Features

  • Cascadable 50 Ω Gain Block
  • High Output Power: +23 dBm Typical P1 dB at 1.0␣ GHz
  • Low Distortion: 33␣ dBm Typical IP3 at 1.0␣ GHz
  • 8.5 dB Typical Gain at 1.0␣ GHz MSA-0500 Chip Outline[1]

Description

The MSA-0500 is a high perfor- mance, medium power silicon bipolar Monolithic Microwave Integrated Circuit (MMIC) chip. This MMIC is designed for use as a general purpose 50 Ω gain block. Typical applications include narrow and broad band IF and RF amplifiers in industrial and military systems. 45␣ pF capacitor. Low frequency performance can be extended by using a larger valued capacitor. [1] Typical Biasing Configuration Note: 1. See Application Note, AN-S009: “Silicon MMIC Chip Use” for additional information. C block C block C Fbl R bias (Required) VCC > 15 V Vd = 12 V RFC (Optional) IN OUT MSA The MSA-series is fabricated using HP’s 10 GHz fT, 25␣ GHz fMAX, silicon bipolar MMIC process which uses nitride self-alignment, ion implantation, and gold metalli- zation to achieve excellent performance, uniformity and reliability. The use of an external bias resistor for temperature and current stability also allows bias flexibility. The recommended assembly procedure is gold-eutectic die attach at 400°C and either wedge or ball bonding using 0.7 mil gold wire. This chip is intended to be used with an external blocking capaci- tor completing the shunt feedback path (closed loop). Data sheet characterization is given for a AK 5965-9579E

Parameter Absolute Maximum [1] Device Current 225 mA Power Dissipation[2,3] 3.0 W RF Input Power +25 dBm Junction Temperature 200 °C Storage Temperature –65 to 200 °C Thermal Resistance[2,4]: θjc = 20°C/W Part Number Ordering Information Part Number Devices Per Tray MSA-0500-GP4 100 Electrical Specifications[1], TA = 25°C Unless otherwise noted, performance is for a MSA-0500 used with an external 45 pF capacitor. See bonding diagram. P1 dB Output Power at 1 dB Gain Compression f = 1.0 GHz dBm 23.0 GP Power Gain (|S21|2) f = 0.1 GHz dB 9.0 ΔGP Gain Flatness f = 0.1 to 2.0 GHz dB ± 0.75 f3 dB 3 dB Bandwidth3 GHz 2.8 Input VSWR f = 0.1 to 2.0 GHz 2.0:1 Output VSWR f = 0.1 to 2.0 GHz 2.5:1 IP3 Third Order Intercept Point f = 1.0 GHz dBm 33.0 NF 50 Ω Noise Figure f = 1.0 GHz dB 6.5 tD Group Delay f = 1.0 GHz psec 125 Vd Device Voltage V 10.5 12.0 13.5 dV/dT Device Voltage Temperature Coefficient mV/ °C –16.0 Notes: 1. The recommended operating current range for this device is 80 to 200 mA. Typical performance as a function of current is on the following page. 2. RF performance of the chip is determined by packaging and testing 10 devices per wafer in a dual ground configuration. 3. Referenced from 0.1 GHz gain (G p). Symbol Parameters and Test Conditions [2]: Id = 165 mA, ZO = 50 Ω Units Min. Typ. Max. VSWR Bonding Diagram MSA Die A05 Input Trace Numbers refer to pin contacts listed on the Chip Outline. Capacitor (45 pF typ) Ground Ground Output Trace (backside contact) Notes: 1. Permanent damage may occur if any of these limits are exceeded. 2. T Mounting Surface (TMS) = 25°C. 3. Derate at 50 mW/°C for TMS␣> ␣1 4 0°C. 4. The small spot size of this technique results in a higher, though more accurate determination of θjc than do alternate methods.

  1. S-parameters are de-embedded from 200 mil BeO package measured data using the package model found in the DEVICE MODELS
  2. S-parameter data assumes an external 45 pF capacitor. Low frequency performance can be extended using a larger valued capacitor.

Figure 1. Typical Gain vs. Power Out,

0.1 GHz

0.5 GHz

Figure 2. Output Power @ 1 dB Gain

2.0 GHz

1.0 GHz

Figure 3. Output Power @ 1 dB Gain Figure 4. Gain vs. Frequency.

MSA-0500 Chip Dimensions[1] AK 570 µm 22.4 mil 530 µm 20.8 mil Unless otherwise specified, tolerances are –13 µm/ –0.5 mils. Chip thickness is 114µm/4.5 mil. Bond Pads are 41 µm/1.6 mil typical on each side. Note 1: Output contact is made by die attaching the backside of the die.