MSA-0100 HP | Alldatasheet
Document overview
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- PDF pages: 4
Technical content
Features
- Cascadable 50 Ω Gain Block
- 3 dB Bandwidth: DC to 1.3 GHz
- High Gain: 18.5 dB Typical at 0.5 GHz
- Unconditionally Stable (k>1) MSA-0100 Chip Outline[1] Typical Biasing Configuration C block C block R bias VCC > 7 V Vd = 5 V RFC (Optional) IN OUT MSA Note: 1. This chip contains additional biasing options. The performance specified applies only to the bias option whose bond pads are indicated on the chip outline. Refer to the APPLICATIONS section “Silicon MMIC Chip Use” for additional information.
Description
The MSA-0100 is a high performance silicon bipolar Monolithic Microwave Integrated Circuit (MMIC) chip. This MMIC is designed for use as a general purpose 50 Ω gain block. Typical applications include narrow and broad band IF and RF amplifiers in commercial, industrial and military applications. The MSA-series is fabricated using HP’s 10 GHz fT, 25␣ GHz fMAX, silicon bipolar MMIC process which uses nitride self-alignment, ion implanta- tion, and gold metallization to achieve excellent performance, uniformity and reliability. The use of an external bias resistor for temperature and current stability also allows bias flexibility. The recommended assembly procedure is gold-eutectic die attach at 400°C and either wedge or ball bonding using 0.7 mil gold wire. [1] See APPLICATIONS section, “Chip Use”. 5965-9689E
Parameter Absolute Maximum [1] Device Current 40 mA Power Dissipation[2,3] 200 mW RF Input Power +20 dBm Junction Temperature 200 °C Storage Temperature –65 to 200 °C Thermal Resistance[2,4]: θjc = 45°C/W Part Number Ordering Information Part Number Devices Per Tray MSA-0100-GP4 100 GP Power Gain (|S21|2) f = 0.1 GHz dB 19.0 ΔGP Gain Flatness f = 0.1 to 0.7 GHz dB ± 0.6 f3 dB 3 dB Bandwidth GHz 1.3 Input VSWR f = 0.1 to 3.0 GHz 1.3:1 Output VSWR f = 0.1 to 3.0 GHz 1.3:1 NF 50 Ω Noise Figure f = 0.5 GHz dB 5.5 P1 dB Output Power at 1 dB Gain Compression f = 0.5 GHz dBm 1.5 IP3 Third Order Intercept Point f = 0.5 GHz dBm 14.0 tD Group Delay f = 0.5 GHz psec 150 Vd Device Voltage V 4.5 5.0 5.5 dV/dT Device Voltage Temperature Coefficient mV/ °C –9.0 Notes: 1. The recommended operating current range for this device is 13 to 25 mA. Typical performance as a function of current is on the following page. 2. RF performance of the chip is determined by packaging and testing 10 devices per wafer in a dual ground configuration. Electrical Specifications[1], TA = 25°C Symbol Parameters and Test Conditions [2]: Id = 17 mA, ZO = 50 Ω Units Min. Typ. Max. VSWR Notes: 1. Permanent damage may occur if any of these limits are exceeded. 2. T Mounting Surface (TMS) = 25°C. 3. Derate at 22.2 mW/°C for TMS␣> ␣1 9 1°C. 4. The small spot size of this technique results in a higher, though more accurate determination of θjc than do alternate methods. See MEASURE- MENTS section “Thermal Resistance” for more information.
Figure 1. Typical Power Gain vs. Frequency, TA = 25°C, Id = 17 mA. Figure 2. Power Gain vs. Current. Figure 3. Output Power at 1 dB Gain Compression, NF and Power Gain vs.
0.1 GHz
1.0 GHz
2.0 GHz
Figure 5. Noise Figure vs. Frequency. Figure 4. Output Power at 1 dB Gain
- S-parameters are de-embedded from 70 mil package measured data using the package model found in the DEVICE
OUTPUT [1] 394 µm 15.5 mil 394 µm 15.5 mil Chip thickness is 114 µm/4.5 mil. Bond Pads are 41 µm/1.6 mil typical on each side. Note 1: Output contact is made by die attaching the backside of the die.