MS7202AL

MS7200L MOSEL | Alldatasheet

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Features

I First-In/First-Out static RAM based dual port memory I Three densities in a x9 configuration I Low power versions I Includes empty, full, and half full status flags I Direct replacement for industry standard Mostek and IDT I Ultra high-speed 30 MHz FIFOs available with 33 ns cycle times. I Fully expandable in both depth and width I Simultaneous and asynchronous read and write I Auto retransmit capability I TTL compatible interface, single 5V ± 10% power supply I Available in 28 pin 300 mil and 600 mil plastic DIP, 32 Pin PLCC and 330 mil SOG Descriptions The MS7200L/7201AL/7202AL are dual-port static RAM based CMOS First-In/First-Out (FIFO) memories organized in nine-bit wide words. The devices are configured so that data is read out in the same sequential order that it was written in. Additional expansion logic is provided to allow for unlimited expansion of both word size and depth. The dual-port RAM array is internally sequenced by independent Read and Write pointers with no external addressing needed. Read and write operations are fully asynchronous and may occur simultaneously, even with the device operating at full speed. Status flags are provided for full, empty, and half-full conditions to eliminate data underflow and overflow. The x9 architecture provides an additional bit which may be used as a parity or control bit. In addition, the devices offer a retransmit capability which resets the Read pointer and allows for retransmission from the beginning of the data. The MS7200L/7201AL/7202AL are available in a range of frequencies from 10 to 30 MHz (33 - 100 ns cycle times). A low power version with a 500µA power down supply current is available. They are manufactured on Mosel-Vitelic’s high performance 1.2µ CMOS process and operate from a single 5V power supply. W WRITE CONTROL WRITE POINTER READ POINTER READ CONTROL RESET LOGIC FLAG LOGIC EXPANSION LOGIC THREE STATE BUFFERS DATA OUTPUTS (Q0-Q8) DATA INPUTS (Q0-Q8) R XI EF HF FF XO RS FL / RT RAM ARRAY 256x9 512x9 1Kx9 Block Diagram 28-PIN PDIP Pin Configurations 32-PIN PLCC V FL / RT EF XO / HF CC GND FF XI 300 mil 600 mil DIP 330 mil SOG W R RS D D XI FF Q Q Q NC FL / RT RS EF XO / HF W NC VCC NC VSS NC R

32 Pin PLCC

MS7200L/01AL/02AL Rev. 1.0 January 1995 Signal Descriptions INPUTS: Data In (D0 - D8) These data inputs accept 9-bit data words for sequential storage in the FIFO during write operations. CONTROLS: Reset (RS) The reset input is active LOW. When asserted, the device is asynchronously reset, and both the read and write internal pointers are set to the first location in the FIFO. A Reset is required after power-up before a write operation can occur. Both Read Enable (R) and Write Enable (W) must be HIGH during Reset. Read Enable (R) The read enable input is active LOW. As long as the Empty Flag (EF) is not set, the read cycle is started on the falling edge of this signal. The data is accessed on a First-In/First-Out basis, independent of any write activity, and is presented on the Data Output pins (Q0 - Q8). When R goes HIGH the Data Output pins return to the high impedance state, and the read pointer is incremented. When the FIFO is empty or all of the data has been read, the Empty Flag will be set and further read operations are inhibited until a valid write operation has been performed. Write Enable (W) The write enable input is active LOW. As long as the Full Flag (FF) is not set, the write cycle is started on the falling edge of this signal. The data present on the Data Input pins (D0 - D8) is stored sequentially, independent of any read activity. When W goes HIGH the write cycle is terminated and the write pointer is incremented. When the maximum capacity of the FIFO has been reached the Full Flag will be set, and further write operations are inhibited until a valid read operation has been performed. Expansion In (XI) This input pin serves two purposes. When grounded, it indicates that the device is being operated in the single device mode. In Depth Expansion mode, this pin is connected to the Expansion Out Output (XO) of the previous device. First Load/Retransmit (FL/RT) This is a dual-purpose input. In single device mode (when Expansion In (XI) is grounded) this pin acts as the retransmit input. A LOW pulse on this will reset the read pointer to the first memory location of the FIFO. The write pointer is unaffected. Both the read enable (R) and write enable (W) inputs must remain HIGH during the retransmit cycle. In Depth Expansion mode this pin acts as a first load indicator. It must be grounded on the first device in the chain to indicate which device is the first to receive data. OUTPUTS: Data Output (Q0 - Q8) A 9 bit data word from the FIFO is output on these pins during read operations. They are in the high impedance state whenever R is HIGH. Empty Flag (EF) This output is active LOW. When all of the data has been read from the FIFO (defined as when the Read pointer is one location behind the Write pointer) this flag will be set. The Data Output pins will be forced into the high impedance state, and all further read operations will be inhibited until a valid write operation has been performed (which will reset this flag). Full Flag (FF) This output is active LOW. To prevent data overflow, when the maximum capacity of the FIFO has been reached (defined as when the Write pointer is one location behind the Read pointer) this flag will be set. All further write operations will be inhibited until a valid read operation has been performed (which will reset this flag). Expansion Out/Half Full Flag (XO/HF) This dual-purpose output is active LOW. In single device mode (when Expansion In (XI) is grounded) this flag will be set at the falling edge of the next write operation after the FIFO has reached one-half of its maximum capacity. This flag will remain set as long as the difference between the read pointer and the write pointer is greater than one-half of the maximum capacity of the FIFO. In Depth Expansion mode, this output is connected to the Expansion In Input of the next device in the chain. The Expansion Out pin provides a pulse to the next device in the chain when the last memory location has been reached.

MS7200L/01AL/02AL Rev. 1.0 January 1995 Operating Range Capacitance(1) TA = 25°C, f = 1.0MHz Range Ambient Temperature Vcc Commercial 0°C to + 70°C 5V ± 10% Symbol Parameter Condition Unit VTERM Terminal Voltage with Repect to GND -0.5 to +7.0 V TBIAS Temperature Under Bias -10 to +125 TSTG Storage Temperature -60 to +150 PT Power Dissipation 1.0 W IOUT DC Output Current mA Absolute Maximum Ratings(1) Symbol Parameter Condition Max. Unit C IN Input Capacitance VIN = 0V pF CQ Output Capacitance VDQ = 0V pF Depth Expansion/Compound Expansion Mode NOTE: Output. FF Full Flag Output. XI = Expansion Input. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth Tables Single Device Configuration/Width Expansion Mode NOTE: 1. Pointer will increment if flag is high. Mode Inputs Internal Status Outputs RS RT XI Read Pointer Write Pointer EF FF HF Reset X Location Zero Location Zero Retransmit Location Zero Unchanged X X X Read/Write Increment (1) Increment (1) X X X Mode Inputs Internal Status Outputs RS FL XI Read Pointer Write Pointer EF FF Reset-First Device (1) Location Zero Location Zero Reset all Other Devices (1) Location Zero Unchanged Read/Write X (1) X X X X Test MS7200L/7201AL 7202AL (-25, -35) MS7200L/7201AL 7202AL (-50, -80) Parameter Parameter Test Conditions Min. Typ. Max. Min. Typ. Max. Units VIL Input Low Voltage 0.8 0.8 V VIH Input High Voltage 2.0 2.0 V I IL Input Leakage Current VCC = Max, V IN = 0Vto V CC µA IOL Output Leakage Current VCC = Max, R= VIH, VIN = 0V toVCC -10 -10 µA VOL Output Low Voltage VCC = Min, IOL = 8mA 0.4 0.4 V VOH Output High Voltage VCC = Min, IOH = -2mA 2.4 2.4 V ICC1 Operating Power Supply Current VCC = Max, II/O = 0mA, F = Fm ax 125 mA ICC2 Average Standby Current VCC = Max, R = W = RS = FL / RT = VIH, I I/O = 0mA mA ICCSB(S) Power Down Power Supply Current (Standard Power) VCC = Max, R = W = RS = FL / RT > VCC-0.2V, V IN > V CC-0.2V or V IN < 0.2V mA ICCSB(L) Power Down Power Supply Current (Low Power) VCC = Max, R = W = RS = FL / RT > VCC-0.2V, V IN > V CC-0.2V or V IN < 0.2V 500 500 µA

MS7200L/01AL/02AL Rev. 1.0 January 1995 Parameter MS7200L-25 MS7201AL-25 MS7202AL-25 MS7200L-35 MS7201AL-35 MS7202AL-35 MS7200L-50 MS7201AL-50 MS7202AL-50 MS7200L-80 MS7201AL-80 MS7202AL-80 Name Parameter Min. Max. Min. Max. Min. Max. Min. Max. Units ƒS Shift Frequency 22.2 MHz Read Cycle tRC Read Cycle Time 100 ns tA Access Time ns tRPW Read Pulse Width ns tRR Read Recovery Time ns tRLZ (2) Read Pulse Low to Data Bus at Low Z ns tRHZ (2,3) Read Pulse High to Data Bus at High Z ns tDV Data Valid from Read Pulse High ns Write Cycle tWC Write Cycle Time 100 ns tWPW (1) Write Pulse Width ns tWR Write Recovery Time ns tDS Data Setup Time ns tDH Data Hold Time ns tWLZ (2,3) Write Pulse High to Data Bus at Low Z ns Flag Timing tREF Read Low to Empty Flag Low ns tRHF Read High to Half Full Flag High 100 ns tRFF Read High to Full Flag High ns tWEF Write High to Empty Flag High ns tWFF Write Low to Full Flag Low ns tWHF Write Low to Half Full Flag Low 100 ns tRPE Read Pulse Width After EF High ns tWPF Write Pulse Width After FF High ns Reset Timing tRSC Reset Cycle Time 100 ns tRS (1) Reset Pulse Width ns tRSS Reset Set Up Time ns tRSR Reset Recovery Time ns tEFL Reset to Empty Flag Low 100 ns tHFH Reset to Half Full Flag High 100 ns tFFH Reset to Full Flag High 100 ns Retransmit Timing tRTC Retransmit Cycle Time 100 ns tRT (1) Retransmit Pulse Width ns tRTS Retransmit Set up Time ns tRTR Retransmit Recovery Time ns Expansion Timing tXOL Read/Write to XO Low ns tXOH Read/Write to XO High ns tXI XI Pulse Width ns tXIS XI Set up Time ns tXIR XI Recovery Time ns NOTES: Pulse widths less than minimum value are not allowed. Values guaranteed by design, not currently tested. Only applies to read data flow-through mode.

MS7200L/01AL/02AL Rev. 1.0 January 1995 W EF R tWEF tRPE t : EFFECTIVE READ PULSE WIDTH AFTER EMPTY FLAG HIGH RPE tRTC tRT tRTS tRTR FL / RT R, W D0-D8 WRITE DATA VALID W WRITE DATA VALID tWC tWPW tWR tDH tDS Timing Waveforms ASYNCHRONOUS WRITE OPERATION RETRANSMIT EMPTY FLAG TIMING

MS7200L/01AL/02AL Rev. 1.0 January 1995 W FF R tRFF tWPF t : EFFECTIVE WRITE PULSE WIDTH AFTER FULL FLAG HIGH WPF W R HF tWHF tRHF HALF-FULL OR LESS MORE THAN HALF-FULL HALF-FULL OR LESS R FIRST READ W FF LAST WRITE ADDITIONAL READS FIRST WRITE tWFF tRFF Timing Waveforms FULL FLAG TIMING HALF-FULL FLAG TIMING FULL FLAG FROM LAST WRITE TO FIRST READ

MS7200L/01AL/02AL Rev. 1.0 January 1995 FIRST WRITE LAST READ ADDITIONAL WRITES FIRST READ VALID R W EF tREF tWEF VALID tA DATA OUT DATA W tRPE DATA VALID EF tWEF tWLZ tA OUT OUT R DATA IN tREF Timing Waveforms EMPTY FLAG FROM LAST READ TO FIRST WRITE READ DATA FLOW-THROUGH MODE WRITE DATA FLOW-THROUGH MODE DATA W tWPF DATA VALID FF tRFF tDS tA IN IN R tWFF DATA DATA VALID OUT OUT tDH

input pin must be grounded. See Figure 3. Figure 3. Single Device Mode

MS7200L/01AL/02AL Rev. 1.0 January 1995 RA EFA WB FFB WA FFA RB EFB SYSTEM A SYSTEM B MS7201 MS7201 DB QA0-8 QB0-8 DA0-8 HFB HFA Figure 6. BiDirectional FIFO Mode Figure 6. This allows each system to READ and

Ordering Information

Speed (ns) Ordering Part Number Package Temperature Range MS7201AL-25PC MS7202AL-25PC

28 Pin Plastic DIP - 600 mil

0°C to +70°C MS7200-25NC MS7201AL-25NC MS7202AL-25NC

28 Pin Plastic DIP - 300 mil

0°C to +70°C MS7200-25JC MS7201AL-25JC MS7202AL-25JC

32 Pin Plastic PLCC

0°C to +70°C MS7200-25FC MS7201AL-25FC MS7202AL-25FC

28 Pin Small Outline - 330 mil

0°C to +70°C MS7201AL-35PC MS7202AL-35PC 0°C to +70°C MS7200-35NC MS7201AL-35NC MS7202AL-35NC 0°C to +70°C MS7200-35JC MS7201AL-35JC MS7202AL-35JC 0°C to +70°C MS7200-35FC MS7201AL-35FC MS7202AL-35FC 0°C to +70°C MS7201AL-50PC MS7202AL-50PC 0°C to +70°C MS7200-50NC MS7201AL-50NC MS7202AL-50NC 0°C to +70°C MS7200-50JC MS7201AL-50JC MS7202AL-50JC 0°C to +70°C MS7200-50FC MS7201AL-50FC MS7202AL-50FC 0°C to +70°C MS7201AL-80PC MS7202AL-80PC 0°C to +70°C MS7200-80NC MS7201AL-80NC MS7202AL-80NC 0°C to +70°C MS7200-80JC MS7201AL-80JC MS7202AL-80JC 0°C to +70°C MS7200-80FC MS7201AL-80FC MS7202AL-80FC 0°C to +70°C