MS62256L-85PC | DigiCamel IC Datasheet

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SHE D MM 6353391 0001399 311 MNOVI ery ns 32K x 8 CMOS Static RAM MOSEL-VITELIC oe a T 4b 23ND FEATURES DESCRIPTION * High-speed — 70/85/100/120 ns The MOSEL MS62256 is a 262,144-bit static random . lash : access memory organized as 32,768 words by 8 bits and Low Power dissipation: operates from a single & volt supply. Itis bullt with Ms62256L. MOSEL’s high performance twin tub CMOS process. — 385mW (Max.) Operating Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus ~ 650 (Typ.) Power Down structures. The MS62256 Is available in a standard 28-pin * Fully static operation 600 mil plastic DIP package and 330 mil SOP. * All inputs and outputs directly TTL compatible * Three state outputs * Ultra low data retention supply current at Veg = 2V PIN CONFIGURATIONS FUNCTIONAL BLOCK DIAGRAM Aus 201 veo mo—fSo-] , ane Ww . —oan ats aE ais : one Nomar aty ae af Ay . = ne = suo—fSo] Aa Yo moses, Fay as? abs [oseeeee] ale 21 Awe a004—> wat Bt Ty]. EL ed va] 10-1 006 : Crest F: FE: a; C} 17/1 bas, pa70t+ef> Z\\ A VV cae] 1871 004 i. b i ono] « 15[71 005 Wo MOSEL Corporation 914 West Maude Avenue, Sunnyvale, CA 94086 U.S.A 408-733-4556 PIDO19A 3-32

S4YE D MM 6353391 O0O1L400 963 MENOVI NOSEL=VITELIC ~ MS62256 T-46-23-13 PIN DESCRIPTIONS 46 A,-A, Address Inputs W Write Enable Input These 15 address inputs select one of the 32768 8-bit The write enable input is active LOW and controls read and words in the RAM. write operations. With the chip enabled, when W is HIGH _ and G is LOW, output data will be present at the DQ pins; E Chip Enable input when W is LOW, the data present on the DQ pins will be Eis active LOW. The chip enable must be active to read written into the selected memory location. from or write to the device. If itis not active, the device is deselected and is in a standby power mode. The DQ pins DQ,-DQ, Data Input/Output Ports will be in the high-impedance state when deselected. These 8 bidirectional ports are used to read data from or _ write data into the RAM. G Output Enable Input The output enable input is active LOW. If the output enable Veo Power Supply is active whilo the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will GND Ground be enabled. The DQ pins will be in the high Impedance state when G is inactive. TRUTH TABLE [one T= | & | W_|vooperation [-stancoy a [x [x | tinz | a [Read fe fe Te | nz | a ABSOLUTE MAXIMUM RATINGS “ OPERATING RANGE a ee Supply Voltage TENPERATUE ve v InpuYOulput Voltage Applied a ll Bias P= Tian PI Temperature [Fo [Power Dissipation | 1.0 | w | [esr [oc oupucuren | 20 | ma | 1, Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is ‘a stress rating only and functional operation of the device at these or any other conditions above those Indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3-33 PIDO19A,

S4E-D MM 6353391 0001401 aTT mnovi. MS62256 NOSEL-VITELIC ~~ T=46-23-13 DC ELECTRICAL CHARACTERISTICS (over the commercial operating range) PARAMETER +70, -85 210, -12 Vi [Guaranteed Input Low 03 - 408/03 - 408 foltago!2i9) Vin [Guaranteed Input High y Wottagot®) | [input Leakage Current [Voo=MaxVn= WioVes Ss 2 | -- 2 | ga | I a ac tov Ouput Low Voltage [Voo= Min. =4mA oa | on | | | | Vou fouiputtignvotage [Voc Min y=-mA dea 38 - (fads - |v _| leo |Operating Power Supply | Voo= Max, E = Vi, lyo = OMA, Frm ax : - 70 [Current loose /Standby Powor Supply | Voc = Max, E = Vij, yo = OMA | Current ‘cogs: Power Down Power | Voc=MaKE®Vco-0.2V [msezase.] = or | =~ oa | ma | | [Supply Current Min® Voo-0:2V orVns0.2v | mseaase [- = a | = = 1 | ma | 1. Typical characteristics are at V, = 5V, T, = 25°C. 2. These are absolute values with respect to device ground and all overshoots due to ‘system or tester noise are included. 3. V, (Min.) =-3.0V for pulse width < 20ns 3. Fae he | CAPACITANCE" (T, = 25°C, f = 1.0MHz) [ svmeot [PARAMETER conorrions | wax. [ unr] Input Capacitance | Vw=0V | @_| pF | Input/Output . [cw [emeaaes | vos [ w | or | 1. This parameter is guaranteed and not tested, DATA RETENTION CHARACTERISTICS" (over the commercial operating range) sywpol_[ "_panaweren [TEST CONDITIONS ‘| MIN._TYPH_MAK@)] UNITS | Vor Vco for Data Ratention E = Voo-0.2V, G2 Veg -O.2V, Vin 2 Voo-0.2V Vv jor Vy $0.2V |Data Retention Current IE; 2 Vog-0.2V, G 2 Voc -0.2V, Vin 2 Voo-0.2V - 2 50 pA jor Vy S$ 0.2V [Chip Deselect to Data Retention [= | ime See Retention Waveform [5 oven Reson Tio [ee 1. Applies to L verion only 2. Veg = 2V, T= 425°C. 8. Veg = 8V 4, tag = Read Cycle Timo TIMING WAVEFORM LOW V,,, DATA RETENTION WAVEFORM Veo Data Retention Mode 45v) Vpn 2 2V 4.5V topa’ tr = Ve = Vin <= Vn eS PIDO19A 3-34

S4E D MM 635339) 0002402 73b MMMOVI “MOSEL-VITELIC) => FF T=46-23-13 \\ MS62256 eee OO AC TEST CONDITIONS KEY TO SWITCHING WAVEFORMS Input Pulse Levels OV to 3.0V WAVEFORM INPUTS oureure Input Rise and Fall Times ‘ns a Timing Reference Level 1.8V Meby | Seaby Wee MORNE BiB LY "itt MOCO MELEE, XXX See gues BRAS El coven ES AC TEST LOADS AND WAVEFORMS soon (t) e900 ouput ourur 009° econ) 5p 6600. wae ea Equivalent te: THEVENIN EQUIVALENT py oureut o_o. auinpur uses rc a a ne ‘Figure 2 sor tgone ven, sn00 ER igesreake ae ‘3. For 100 ns version, 100pF AC ELECTRICAL CHARACTERISTICS (over the commercial operating range) READ CYCLE JEDEC |MS62256L-70|MS62256L-85|MS62256L-10| MS62256L-12| |PARAMETER |PARAMETER [“iwe| tne [ReadGycotime «dt = “fas - [to ao [ne | [wav | wa | Address Accesstime | 70 [es | too | = 120 | ns _ [eta [os] Chip enable Aoness Tima [0 | - 08 | too] 20 [ me | [tevox | ‘or Ouipotenableto Ouiputvaid fos | - 40 | = so | 60 [ns | | “ies [ez | hin EnatiotoOuittowz [= fs | 8 oe | [Pex —| tox [Oupteratioto Ouputintow2 [8 [6 - | o -|s -| | [wie [tae [Chip Disabinto Ouputinrighz | 0 wo | oe [os | 0 a0 | re | [ore | fore Output Disstioo OuputinignZ [ooo | 005 [0 a5 | 00 | re | [ince [tor] Output Hotarom Adress Chango [to _- [0 - | - | - | = | 3-35 PIDO19A

S4E D MM 6353393 0001403 b?2 mNOVI. Sr WT cic an MS62256 _MOSEL-VITELI (ngr23a-13 SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE 1 tre’ tan a Ww LLLLLL LL. tow: tou z\\\\S tos Lan tacos: 19) tonz©'—s} ee Dour OK KX) READ CYCLE 20:2. ‘tro’ ADDRESS oat ton Dour READ CYCLE 34.3.4 7 =o teva Dour’ NOTES: 1. Wis High for READ Cycle, 2, Device is continuously selected E = V,._ 3, Address valid prior to or colncident with E transition low. 4. G=V,. 5. Transition fs measured 500m from steady stato with O, = 6pF as shown in Figuro tb on page 4. This parameter fs guaranteed and not 100% tested. PIDOI9A. 3-36

SUE D MM 6353391 O001404 509 MENOVI SE 7 635335 00 MOSEL-VITELIC MS62256 __maset-virevic 862256 SO AC ELECTRICAL CHARACTERISTICS (over the commercial operating range) T-46-23~ 13 _ WRITE CYCLE JEDEC [MS62256L-70| MS62256L-85| MS62256L-10| MS62256L-12| PARAMETER |PARAMETER pets | arn Yam md ane mer PC [tame [tow | Chiptnabiotoendorwae | - | eo - | - | - [ns | [the ns] Across Sot uptime | o- | 0 - | o- | o- |» | [it] te adess vatato ena ofits [6s [es - | 7 - | 5 - | vs | [Tain [ wr | WetePusewiah dO dP PO dP |e | [hax [we [WiteRecoveytine [6 -|s -,o -[o -| =| [ace | Wiz | WiltotoOutputinignz =| O25 | 030 | oa | 0 40 | ns | [Town ow [oatavatdtoensorwite [so - | - |e - |e - | m= | [wo [ton | Datatot irom witeting [6 - | s_- | 0 - [| o - [ms | [“eiza [Tore] Output Disab fo Ouputinighz@ [05 | 0 | 0 [0 | me | [Fimo [ ow Loupuracivetromenaofwrie [6 - [s -]s -[s -| | SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE 1 two z WAM WLLTLLLL a | WwW YAAK 4, 10) tonz——| ‘twe Dor SSS our "PZ ZZZZ ZZ LTP. a 3-37 PIDO19A

SHE D MM 6353391 0002405 44S MEMOVI - oo MOSEL-VITELIC : —_—— SWITCHING WAVEFORMS (WRITE CYCLE) area T-46-23-13 WRITE CYCLE 2!) two wy 7 = y zs (YA LLVLLTLLLL w YAY ton — = =e a ES Dour D999 AN AVAN Se YAP AP AT AY A A AF AT A AAT AT AT WAV VAY 4 tow ton —>| @ NOTES: 1, W must be high during address transitions. 2, Tho internal write time of the memory is defined by the overlap E active and W low. Both signals must be active to initiate and any one signal can terminato a write by going inactive, Tho data input setup and hold timing should be referenced to the second transition edgo of the signal that terminates the write. 8, Tyas measured from the earlier of E or W going high at the end of write cycle. 4, During this period, DO pins are in the output state s0 that the input signals of opposite phase to the outputs must not bo applied, 5. Ifthe E low transition occurs simuttaneously with the W low transitions or after the W low transition, outputs remain in a high impedance state, 6. Gis continuously low (@ = V,). 7. Doyris the same phase of write data ofthis write cycle, 8, Dar is the road data of next address. 9. IfE Is low during this period, DQ pins are In the output state. Then the data input signals of opposite phaso to the outputs must not be applied to them, 10. Transition is measured :!600mV from steady state with C, = SpF as shown in Figuro 1b, This parameter Is guaranteed and not 100% tested, 11. toy [Ss measured from E going low to the end of write.

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Product Information

MS62256L-85PC specifications and overview.

Summary

32K x 8 CMOS Static RAM

Description

32K x 8 CMOS Static RAM

Source title MS62256L-85PC Datasheet(PDF) - Mosel Vitelic, Corp

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