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Technical content

© 2021 NXP B.V. Rev. 0.1 of the i.MX RT500 Low-Power Crossover Processor Data Sheet with Addendum has two parts:

• Revision 0 of the data sheet, immediately following this cover page. The changes described in the addendum have not been implemented in the specified pages.
• The addendum to revision 0 of the data sheet. i.MX RT500 Low-Power Crossover Processor Data Sheet with Addendum Document Number: IMXRT500 EC Rev. 0.1, 04/2021

i.MX RT500 Low-Power Crossover Processor The i.MX RT500 is a family of dual-core microcontrollers for embedded applications featuring an Arm Cortex-M33 CPU combined with a Cadence® Xtensa® Fusion F1 Audio Digital Signal Processor CPU. The Cortex-M33 includes two hardware coprocessors providing enhanced performance for an array of complex algorithms along with a 2D Vector GPU with LCD Interface and MIPI DSI PHY. The family offers a rich set of peripherals and very low power consumption. The device has up to 5 MB SRAM, two FlexSPIs (Octal/Quad SPI Interfaces) each with 32 KB cache, one with dynamic decryption, high-speed USB device/host + PHY, 12-bit 1 MS/s ADC, Analog Comparator, Audio subsystems supporting up to 8 DMIC channels, 2D GPU and LCD Controller with MIPI DSI PHY, SDIO/eMMC; FlexIO; AES/SHA/Crypto M33 coprocessor and PUF key generation Control processor core

• Arm Cortex-M33 processor, running at frequencies of up to 200 MHz
• Arm TrustZone
• Arm Cortex-M33 built-in Memory Protection Unit (MPU) supporting eight regions
• Single-precision Hardware Floating Point Unit (FPU).
• Arm Cortex-M33 built-in Nested Vectored Interrupt Controller (NVIC).
• Non-maskable Interrupt (NMI) input.
• Two coprocessors for the Cortex-M33: a hardware accelerator for fixed and floating point DSP functions (PowerQuad) and a Crypto/FFT engine (Casper). The DSP coprocessor uses a bank of four dedicated 2 KB SRAMs. The Crypto/FFT engine uses a bank of two 2 KB SRAMs that are also AHB accessible by the CPU and the DMA engine.
• Serial Wire Debug with eight break points, four watch points, and a debug timestamp counter. It includes Serial Wire Output (SWO) trace and ETM trace.
• Cortex-M33 System tick timer DSP processor core
• Cadence Tensilica Fusion F1 DSP processor, running at frequencies of up to 200 MHz.
• Hardware Floating Point Unit.
• Serial Wire Debug (shared with Cortex-M33 Control Domain CPU). Communication interface
• 9 configurable universal serial interface modules (Flexcomm Interfaces). Each module contains an integrated FIFO and DMA support. Each of the nine modules can be configured as:
• A USART with dedicated fractional baud rate generation and flow-control handshaking signals. The USART can optionally be clocked at 32 kHz and operated when the chip is in reduced power mode, using either the 32 kHz clock or an externally supplied clock. The USART also provides partial support for LIN2.2.
• An I2C-bus interface with multiple address recognition, and a monitor mode. It supports

400 Kb/sec Fast-mode and 1 Mb/sec Fast-

mode Plus. It also supports 3.4 Mb/sec high- speed when operating in slave mode.

• An SPI interface.
• An I2S (Inter-IC Sound) interface for digital audio input or output. Each I2S supports up to four channel-pairs.
• Two additional high-speed SPI interfaces supporting

50 MHz operation

• One additional I2C interface with open-drain pads
• Two I3C bus interfaces
• A digital microphone interface supporting up to 8 channels with associated decimators and Voice MIMXRT5XXSFFOC MIMXRT5XXSFFOCR MIMXRT5XXSFAWCR 249 FOWLP 7.0mm x 7.0mm x 0.725mm, 0.4mm pitch 141 WLCSP 4.525mm x 4.525mm x 0.49mm, 0.35mm pitch NXP Semiconductors IMXRT500EC Data Sheet: Technical Data Rev. 0, 02/2021 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.

• Five independent supplies powering different clusters of pins to permit interfacing directly to off-chip peripherals operating at different supply levels. On-chip memory
• Up to 5 MB of system SRAM accessible by both CPUs, both DMA engines, the Graphics Subsystem and all other AHB masters.
• Additional SRAMs for USB traffic (16 KB), Cortex-M33 co-processors (4 x 2 KB), SDIO FIFOs (2 x 512 B dual- port), PUF secure key generation (2 KB), FlexSPI caches (32 KB each), SmartDMA commands (32 KB), and a variety of dual and single port RAMs for graphics.
• 16 kbits OTP fuses
• Up to 192 KB ROM memory for factory-programmed drivers and APIs
• System boot from High-speed SPI, FlexSPI Flash, HS USB, I2C, UART or eMMC via on-chip bootloader software included in ROM. FlexSPI boot mode will include an option for Execute-in-place start-up for non- secure boot. Digital peripherals
• Two general purpose DMA engines, each with 37 channels and up to 27 programmable request/trigger sources.
• Can be configured such that one DMA is secure and the other non-secure and/or one can be designated for use by the M33 CPU and the other by the DSP
• Smart DMA Controller with dedicated 32KB code RAM
• USB high-speed host/device controller with on-chip PHY and dedicated DMA controller.
• Two FlexSPI (Octal/Quad) Interfaces up to 200 MHz DDR/SDR (target). 32 KB caches with selectable cache policies based on programmable address regions. One of the FlexSPI interface will include on- the-fly decryption for execute-in-place and address- remapping to support dual-image boot. DMA supported (both modules).
• Two SD/eMMC memory card interfaces with dedicated DMA controllers. One supports eMMC 5.0 with HS400/DDR operation. Analog peripherals
• One 12-bit ADC with sampling rates of 1 Msamples/sec and an enhanced ADC controller. It supports up to 10 single-ended channels or 5 differential channels. The ADC supports DMA.
• Temperature sensor.
• Analog comparator Activation Detect. One pair of channels can be streamed directly to I2S. The DMIC supports DMA. Timers
• One 32-bit SCTimer/PWM module (SCT). Multi- purpose timer with extensive event-generation, match/compare, and complex PWM and output control features.
• 10 general-purpose/PWM outputs, 8 general- purpose inputs
• It supports DMA and can trigger external DMA events
• It supports fractional match values for high resolution
• Five general purpose, 32-bit timer/counter modules with PWM capability
• 24-bit multi-rate timer module with 4 channels each capable of generating repetitive interrupts at different, programmable frequencies.
• Two Windowed Watchdog Timers (WDT) with dedicated watchdog oscillator (1 MHz LPOSC)
• Frequency measurement module to determine the frequency of a selection of on-chip or off-chip clock sources.
• Real-Time Clock (RTC) with independent power supply and dedicated oscillator. Integrated wake-up timer can be used to wake the device up from low- power modes. The RTC resides in the “always-on” voltage domain. RTC includes eight 32-bit general- purpose registers which can retain contents when power is removed from the rest of the chip.
• Ultra-low power micro-tick Timer running from the Watchdog oscillator with capture capability for timestamping. Can be used to wake up the device from low-power modes.
• 64-bit OS/Event Timer common to both processors with individual match/capture and interrupt generation logic. Enabled on POR Clocks
• Crystal oscillator with an operating range of 4 MHz to 26 MHz.
• Dual trim option: Internal 192/96 MHz FRO oscillator. Trimmed to 1% accuracy.
• FRO capable of being tuned using an accurate reference clock (eg. XTAL Osc) to 0.1% accuracy with 46% duty cycle to support MIPI PHY and FlexSPI.
• Internal 1 MHz low-power oscillator with 5% accuracy. Serves as the watchdog oscillator and clock for the OS/Event Timer and the Systick among others. Also available as the system clock to both domains.
• 32 kHz real-time clock (RTC) oscillator that can optionally be used as a system clock.
• Main System PLL:
• allows CPU operation up to the maximum rate without the need for a high-frequency crystal. 2 i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 NXP Semiconductors

• 2D Vector Graphics Processing Unit, running at frequencies of up to 200 MHz.
• LCD Display Interface supporting smart LCD displays and video mode.
• MIPI DSI Interface with on-chip PHY supporting transfer rates up to 895.1 Mbps.
• FlexIO can be configured to provide a parallel interface to an LCD I/O Peripherals
• Up to 136 general purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors. Ports can be written as words, half-words, bytes, or bits.
• Mirrored, secure GPIO0.
• Individual GPIO pins can be used as edge and level sensitive interrupt sources, each with its own interrupt vector.
• All GPIO pins can contribute to one of two ganged (OR’d) interrupts from the GPIO_HS module.
• A group of up to 7 GPIO pins (from Port0/1) can be selected for Boolean pattern matching which can generate interrupts and/or drive a “pattern-match” output.
• Adjustable output driver slew rates.
• JTAG boundary scan Security
• Secure Isolation: Protection from software and remote attacks using Trustzone for armV8M. Hardware isolation of AES keys
• Secure Boot: firmware in ROM providing immutable root of trust
• Secure Storage: Physically Unclonable Function (PUF) based key store, On-the-fly-AES decryption (OTFAD) of off-chip flash for code storage
• Secure Debug: Certificate based debug authentication mechanism
• Secure Loader: Supports firmware update mechanism with authenticity (RSA signed) and confidentiality (AES-CTR encrypted) protection
• Secure Identity: 128-bit Universal Unique Identifier (UUID), 256-bit Compound Device Identifier (CDI) per TCG DICE specification
• Cryptographic Accelerators
• Symmetric cryptography (AES) with 128/192/256-bit key strength and protection against Side-channel analysis (Differential Power Analysis and Template attacks)
• Asymmetric cryptography acceleration using CASPER co-processor
• NIST SP 800-90b compliant TRNG design with 512-bit output per call
• Hash engine with SHA-256 and SHA1 May be run from the FRO, the crystal oscillator or the CLKIN pin.
• a second, independent PLL output provides alternate high-frequency clock source for the DSP CPU if the required frequency is different from the main system clock. (Note: 2nd PFD output from Main System PLL)
• two additional PLL outputs provide potential clock sources to various peripherals.
• Audio PLL for the audio subsystem. Power Control
• Main external power supply: 1.8V ± 5%
• Vddcore supply (from PMIC or internal PMU): adjustable from 0.6 V to 1.1 V (including retention mode)
• Analog supply: 1.71-3.6 V
• Five VDDIO supplies (can be shared or independent): 1.71 - 3.6 V
• USB Supply: 3.0-3.6 V
• Reduced power modes:
• Sleep mode: CPU clock shut down (each CPU independently)
• Deep_sleep mode: User-selectable configuration via PDSLEEPCFG
• Deep_powerdown mode: Internal power removed from entire chip except “always-on” domain
• Each individual SRAM partition can be independently powered-off or put into a low- power retain mode
• DSP Domain can be powered-off independently from the rest of the system.
• Ability to operate the synchronous serial interfaces in sleep or deep-sleep as a slave or USART clocked by the 32 kHz RTC oscillator
• Wake-up from low-power modes via interrupts from various peripherals including the RTC and the OS/Event timer
• RBB/FBB to provide additional control over power/ performance trade-offs
• Power-On Reset (POR). Operating characteristics
• Temperature range (ambient): -20 °C to +70 °C
• VDDCORE: 0.7 V - 1.155 V
• VDDIO_3: 1.71 V - 3.6 V i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 3 NXP Semiconductors

192 KB ROM

16 KB USB RAM

Figure 1. i.MX RT500 Block Diagram The following table provides examples of orderable sample part numbers covered by this data sheet.

Orderable part number table Orderable part number Part number1 SRAM (MB) DSP Graphics Security USB I2S Package MIMXRT595SFFOC MRT595SFFOC 5 Yes Yes SRAM PUF, AES256, HASH HS 9 FOWLP2492 MIMXRT555SFFOC MRT555SFFOC 5 No Yes SRAM PUF, AES256, HASH HS 9 FOWLP249 MIMXRT533SFFOC MRT533SFFOC 3 No No SRAM PUF, AES256, HASH HS 9 FOWLP249 MIMXRT595SFFOCR MRT595SFFOC 5 Yes Yes SRAM PUF, AES256, HASH HS 9 FOWLP2492 MIMXRT555SFFOCR MRT555SFFOC 5 No Yes SRAM PUF, AES256, HASH HS 9 FOWLP249 MIMXRT533SFFOCR MRT533SFFOC 3 No No SRAM PUF, AES256, HASH HS 9 FOWLP249 MIMXRT533SFAWCR MRT533SFAWC 3 No No SRAM PUF, AES256, HASH HS 6 WLCSP141 MIMXRT555SFAWCR MRT555SFAWC 5 No Yes SRAM PUF, AES256, HASH HS 6 WLCSP141 MIMXRT595SFAWCR MRT595SFAWC 5 Yes Yes SRAM PUF, AES256, HASH HS 6 WLCSP141 1. As marked on package 2. 249-pin Fan-out wafer-level package Device revision number Device Mask Set Number SILICONREV_ID JTAG_ID[CHIPREV] 2P43B 0x000B0002 0x2 Package markings for i.MX RT devices consist of 4 sets of identifiers as shown below. i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 5 NXP Semiconductors

Figure 2. Package markings

• The 1st identifier defines the Part Number and is composed of 11 characters.
• The 2nd and 4th identifiers define the Traceability markings.
• The 3rd identifier defines the Date Code for the week of manufacture is a subset of the standard 5 character format. The standard date code format is “xYYWW”:
• The leading digit represented by “x” can be ignored and “YYWW” indicate the Date Code.
• “YY" represents an encoding of the calendar year (for example, 19 corresponds to year 2019).
• “WW” represents an encoding of the work week within the calendar year (for example, 07 corresponds to work week 7). Please provide this information to your local NXP representative for further details. The following figure explains the part number for this device. 6 i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 NXP Semiconductors

5 R T500 series

Figure 3. Part number diagram device for design suitability. description of the structure and function (operation) of a device. Data Sheet Refers to this document which includes electrical characteristics and signal connections.

8 i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 NXP Semiconductors

1.1.4 Absolute maximum voltage and current

1.2.2 Free-running oscillator FRO-192/96M

1.3.2 Serial Wire Debug (SWD) timing

1.7.5 High-Speed SPI interface (Flexcomm

1.7.10 USB High Speed Transceiver and PHY

1.7.11 Improved Inter-Integrated Circuit Interface

3.4.1 RTC Printed Circuit Board (PCB) design

3.5.1 XTAL Printed Circuit Board (PCB) design

3.5.2 Thermally compensated crystal oscillator

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 9 NXP Semiconductors

Electrical characteristics

1.1 Chip-level conditions

This section provides the device-level electrical characteristics for the IC. See the following table for a quick reference to the individual tables and sections. Table 1. i.MX RT500 chip-level conditions

1.1.1 Thermal handling ratings

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.1.2 Moisture handling ratings

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices. 10 i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 NXP Semiconductors

1.1.3 ESD handling ratings

Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 500 V 2 ILAT Latch-up current at ambient temperature of 70 °C -100 100 mA 3 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

1.1.4 Absolute maximum voltage and current ratings

Stress beyond those listed under the following table may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Table 2. Absolute maximum ratings 1

features

• 2 -0.3 1.98 V VDD1V8 1.8 V supply voltage for on- chip analog functions other than the ADC and comparator. - 2 -0.3 1.98 V VDD1V8_1 1.8 V supply voltage for on- chip digital logic - 2 -0.3 1.98 V Table continues on the next page...

i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 11 NXP Semiconductors

Table 2. Absolute maximum ratings 1 (continued)

3.3 V supply

1.71 V ≤ VDD <

Table continues on the next page... 12 i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 NXP Semiconductors

1. In accordance with the Absolute Maximum Rating System (IEC 60134). The following applies to the limiting values:

• This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.
• Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
• The limiting values are stress ratings only and operating the part at these values is not recommended and proper operation is not guaranteed. The conditions for functional operation are specified in Table 1. 2. Maximum/minimum voltage above the maximum operating voltage (see Table 1) and below ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device. 3. The peak current should not exceed the total supply current. 4. Determined in accordance to JEDEC JESD51-2A natural convection environment (still air). Thermal specifications

1.1.5.1 Thermal operating requirements

Table 3. Thermal operating requirements

1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to

determine TJ is: TJ = TA + RΘJA × chip power dissipation.

1.1.5.2 Thermal characteristics

• T amb = ambient temperature (°C),
• R th(j-a) = the package junction-to-ambient thermal resistance (°C/W)
• P D = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of the I/O pins is often small and many times can be negligible. However it can be significant in some applications.

Table 4. Thermal resistance 1

1. Determined in accordance to JEDEC JESD51-2A natural convection environment (still air). Thermal resistance data in

1.1.6 General operating conditions

Tamb = -20 °C to +70 °C, unless otherwise specified. Table 5. General operating conditions Table continues on the next page...

Table 5. General operating conditions (continued) Table continues on the next page...

1. Typical ratings are not guaranteed. The values listed are for room temperature (25 °C), nominal supply voltages.
2. 1.8 V supply voltage for on-chip digital logic during active mode. In deep-sleep mode, this pin can be powered off to

conserve additional current (~20 uA).

1. The maximum frequency for the specified VDDCORE voltage is the frequency of the main clock. This is before the CPU

CLOCK Divider. The VDDCORE voltage has to be set according to the chosen main clock frequency.

1. When LDO_ENABLE is externally tied low, the user must boot at VDDCORE = 1.0 V or higher (Low power/Normal clock

BOOT_CLK_SPEED). Thereafter, the VDDCORE can be adjusted to the desired level.

1. When LDO_ENABLE is externally tied high, the on-chip regulator to the VDDCORE Core voltage in PMC is set to the

internally configure the on-chip regulator voltage to the VDDCORE.

1. When performing any OTP read/write function, the VDDCORE voltage must be set to 1.0 V or higher when

LDO_ENABLE is externally tied high or low.

1. GPU, SPI, and CTIMER are disabled.
2. Although i.MX RT500 is targeted to operate up to 200 MHz for low power operation, it can operate up to 275 MHz;

however, there will be an increase in current consumption.

1. VDD_BIAS must be equal to maximum ADC input voltage or maximum comparator input voltage.
2. The USB PHY provides two options for reporting VBUS valid back to the USB controller:

• A programmable internal VBUS_VALID comparator (the default option), or
• An alternate VBUS_VALID_3V detector that will report VBUS valid for voltages above 3 V Thermal specifications 16 i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 NXP Semiconductors

used, USBPHY_USB1_VBUS_DETECTn[VBUSVALID_THRESH] determines the threshold voltage for a valid VBUS. The programmable range is 4.0V to 4.4V (default).

1. The USB PHY provides two options for reporting VBUS valid back to the USB controller:

• A programmable internal VBUS_VALID comparator (the default option), or
• An alternate VBUS_VALID_3V detector that will report VBUS valid for voltages above 3 V USBPHY_USB1_VBUS_DETECTn[VBUSVALID_SEL] selects which option is used. If the VBUS_VALID_3V detector is used, the detector voltage is not programmable.

1.1.7 I/O parameters

1.1.7.1 I/O DC parameters

Tamb = -20 °C to +70 °C, unless otherwise specified. Values tested in production unless otherwise specified. Table 6. I/O DC characteristics

1.71 V ≤ VDD_AO1V8

Table continues on the next page...

Table 6. I/O DC characteristics (continued)

1. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltage.
2. Guaranteed by design, not tested in production.

1. All GPIO pins are fail safe up to 3.6 V when VDDIO supply = 0 V except following pins: PIO1_18 to PIO1_29, PIO1_30
2. Based on characterization. Not tested in production.

1.1.8 Power consumption operating behavior

Tamb = -20 °C to +70 °C, unless otherwise specified. Table 7. Power consumption in active mode

1. Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C). VDD_AO1V8 = VDD1V8 =
2. Characterized through bench measurements using typical samples.
3. Based on the power API library from the SDK software package available on nxp.com
4. SRAM partition 30 represents the worst case partition.
5. FRO clock source, FBB enabled

Tamb = -20 °C to +70 °C, unless otherwise specified. Table 8. Power consumption in active mode

1. Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C). VDD_AO1V8 = VDD1V8 =
2. Characterized through bench measurements using typical samples.
3. Compiler settings: IAR C/C++ Compiler for Arm ver 8.40. High Speed, No Size constraints. The optimization level is
4. Based on the power API library from the SDK software package available on nxp.com
5. SRAM partition 30 represents the worst case partition.

Tamb = -20 °C to +70 °C, unless otherwise specified. Table 9. Power consumption in active mode Table continues on the next page...

Table 9. Power consumption in active mode (continued)

1. Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C). VDD_AO1V8 = VDD1V8 =
2. Characterized through bench measurements using typical samples.
3. Compiler settings: IAR C/C++ Compiler for Arm ver 8.40. High Speed, No Size constraints. The optimization level is
4. SRAM partitions 30 and 31 represent the worst case partitions. The Fusion F1 DSP requires DRAM and IRAM in

different partitions. DSP_DRAM is in partition 30, DSP_IRAM is in partition 31.

1. Based on the power API library from the SDK software package available on nxp.com
2. PLL clock source, FBB enabled

Table 10. Power consumption in sleep mode

1. 256 KB SRAM, internal LDO enabled
2. All peripheral clocks gated

Tamb = -20 °C to +70 °C, unless otherwise specified.

Table 11. Power consumption in deep sleep mode

1. Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C). All power supplies = 1.8 V,
2. Characterized through bench measurements using typical samples.
3. Guaranteed by characterization, not tested in production.
4. VDDCORE = 0.6 V, RBB Enabled

Tamb = -20 °C to +70 °C, unless otherwise specified. Table 12. Power consumption in deep sleep mode Table continues on the next page...

Table 12. Power consumption in deep sleep mode (continued)

1. Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C). All power supplies = 1.8 V,
2. Characterized through bench measurements using typical samples.
3. Guaranteed by characterization, not tested in production.

Tamb = -20 °C to +70 °C, unless otherwise specified. Table 13. Power consumption in deep power-down mode and full deep power-down modes supply current Full Deep power-down mode; Internal LDO disabled. Full Deep power-down mode; Internal LDO disabled.

1. Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C). All power supplies = 1.8 V,
2. Characterized through bench measurements using typical samples.
3. Guaranteed by characterization, not tested in production.

1.1.9 CoreMark data

Table 14. Coremark data

1. Characterized through bench measurements using typical samples.
2. Compiler settings: IAR C/C++ Compiler for Arm ver 8.22.2, optimization level 3, optimized for time on.
3. Clock source FRO. PLL disabled
4. Clock source external clock to XTALIN (bypass mode). PLL enabled.

1.2 System power and clocks

1.2.1 Power sequence

1. VDD_AO1V8, VDD1V8, and VDD1V8_1 pins should be powered first. There is
2. VDDA_ADC1V8 and VREFP can be powered concurrently with VDD_AO1V8
3. VDDIO_x and VDDA_BIAS pins can be powered concurrently with

delta voltage between VDDIO_x and VDD1V8 must be 1.89 V or less.

1. VDD_AO1V8, VDD1V8, and VDD1V8_1 pins should be powered first. There is
2. VDDA_ADC1V8 and VREFP can be powered concurrently with VDD_AO1V8
3. VDDIO_x and VDDA_BIAS pins can be powered concurrently with VDD1V8 if

VDDIO_x and VDD1V8 must be 1.89 V or less.

1. Power up the VDDCORE. The external RESETN should be held low until

until after all the other supplies have completed ramp up. USB1_VDD3V3 can be powered at any time, independent of the other supplies. the rise time, except for the sequencing defined above. Table 15. Power-on characteristics

Figure 4. Power-up ramp

1.2.2 Free-running oscillator FRO-192/96M specifications

Table 16. FRO-192M specifications

• 1T trim (Open loop) — — ±1 % Table continues on the next page... Thermal specifications i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 27 NXP Semiconductors

Table 16. FRO-192M specifications (continued)

1. Vmin =0.8 V is derived from FRO192 MHz divided by 2/4/8.

anywhere should be turned off to save power. Table 17. FRO-96M specifications

• 1T trim (Open loop) — — ±1 % tstartup Start-up time — 120 — μs jitcyc Cycle to cycle jitter — 180 — ps Ifro96m Current consumption — 23 63 μA Vmin Minimum voltage 0.71 — — V 1. Vmin =0.7 V is derived from FRO96 MHz divided by 2/4/8.

1.2.3 Crystal oscillator

Table 18. Crystal oscillator characteristics

1. Parameters are valid over operating temperature range unless otherwise specified.
2. Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.

1. CLKCTL0_SYSOSCCTL0[LP_ENABLE] = 1 sets High Gain Mode, which requires a 1 MΩ feedback resistor.

1.2.4 RTC oscillator

See RTC oscillator for connecting the RTC oscillator to an external clock source. Table 19. RTC oscillator characteristics

1. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
2. Proper PCB layout procedures must be followed to achieve specifications.
3. In bypass mode, using an input square wave only on RTCXIN with RTXOUT floating.

1.2.5 External Clock Input (CLKIN) pin

Table 20. Dynamic characteristic: CLKIN

1. Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages

1.2.6 Internal low-power oscillator (1 MHz)

The IRC is trimmed to 10% accuracy over the entire voltage and temperature range.

Table 21. LPOSC characteristics

1. Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.

1.3 System modules

1.3.1 Reset timing parameters

The following figure shows the reset timing and Table 22 lists the timing parameters. Figure 5. Reset timing diagram Table 22. Reset timing parameters

1.3.2 Serial Wire Debug (SWD) timing specifications

Table 23. SWD timing specifications

• Serial wire debug 20 — 20 — ns J4 SWD_CLK rise and fall times — 3 — 3 ns Table continues on the next page... Thermal specifications 30 i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 NXP Semiconductors

1.3.3 JTAG timing specifications

Table 24. JTAG timing specifications

• Boundary Scan 0 10 0 10 MHz
• JTAG 0 25 0 10 MHz J2 TCLK cycle period 1000/J1 — 1000/J1 — ns J3 TCLK clock pulse width
• Boundary Scan 50 — 50 — ns
• JTAG 20 — 20 — ns J4 TCLK rise and fall times — 3 — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — 20 — ns J6 Boundary scan input data hold time after TCLK rise 5 — 5 — ns J7 TCLK low to boundary scan output data valid — 28 — 28 ns J8 TCLK low to boundary scan output high-Z — 25 — 25 ns J9 TMS, TDI input data setup time to TCLK rise 10.5 — 19 — ns J10 TMS, TDI input data hold time after TCLK rise 2.5 — 2 — ns J11 TCLK low to TDO data valid — 19 — 19 ns J12 TCLK low to TDO high-Z 2 — 2 — ns J13 TRST assert time 100 — 100 — ns J14 TRST setup time (negation) to TCLK high 8 — 8 — ns J3 J3 J4 J4 TCLK (input)

Figure 8. Test clock input timing

Figure 11. TRST timing

1.3.4 Wake-up process

VDD = 3.3 V;Tamb = 25 °C; using FRO as the system clock. Table 25. Typical wake-up times from low power modes

1. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
2. The wake-up time measured is the time between when a GPIO input pin is triggered to wake the device up from the low

power modes and from when a GPIO output pin is set in the interrupt service routine (ISR) wake-up handler.

1. FRO disbled, all peripherals off. PLL disabled.
2. Wake up from deep power-down causes the part to go through entire reset process. The wake-up time measured is the

1.4.1 FlexSPI Flash interface

Table 26. Dynamic characteristics: FlexSPI flash interface 1 Table continues on the next page...

Table 26. Dynamic characteristics: FlexSPI flash interface 1 (continued)

1. Based on simulation; not tested in production.

Figure 12. SDR mode (input timing, mode 0 and 1)

Figure 18. DDR mode (output timing, mode 0 and 1) Figure 19. DDR mode (output timing, mode 3)

1.5 Display and graphics

1.5.1 LCDIF

Tamb = -20 °C to 70 °C; VDD = 2.7 V to 3.6 V; CL = 30 pF. Simulated values. Table 27. LCDIF characteristics

1.5.2 MIPI DSI timing

2.0, DSC version 1.0a at protocol layer) for MIPI display port x2 lanes.

1.5.3 Flexible IO controller (FlexIO)

Table 28. FlexIO timing specifications

1. Assumes pins muxed on same VDD_IO domain with same load

1.6 Analog characteristics

Tamb = -20 °C to +70 °C; 1.71 V ≤ VDD≤ 3.6 V; VSSA = VREFN = GND. ADC calibrated at Tamb = 25 °C. Table 29. 12-bit ADC static characteristics Table continues on the next page...

Table 29. 12-bit ADC static characteristics (continued)

1. Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.
2. CADIN represents the external capacitance on the analog input channel for sampling speeds of 1.0 Msamples/s. No

parasitic capacitances included.

1. This resistance is external to the MCU. To achieve the best results, the analog source resistance must be kept as low

possible. The results in this data sheet were derived from a system that had less than 15 Ω analog source resistance.

1. Based on characterization; not tested in production.
2. The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 1.
3. The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal

transfer curve after appropriate adjustment of gain and offset errors. See Figure 1.

1. The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line

which fits the ideal curve. See Figure 1.

1. The full-scale error voltage or gain error (EG) is the difference between the straight-line fitting the actual transfer curve

after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 1.

(1) Example of an actual transfer curve. (2) The ideal transfer curve. (5) Center of a step of the actual transfer curve.

1 LSB

1 LSB =

Figure 20. 12-bit ADC characteristics

1.6.1.1 ADC input impedance

The following figure shows the ADC input impedance for this device.

Figure 21. ADC input impedance

1.6.2 Temperature sensor

Table 30. Temperature sensor static and dynamic characteristics

1. Absolute temperature accuracy. Based on characterization. Not tested in production

Table 31. Temperature sensor Linear-Least-Square (LLS) fit parameters

1. Based on characterization, Not tested in production.
2. Equation: Temp = 25 - ((Vtemp -Vtemp25)/m) Where: VTEMP is the voltage of the temperature sensor channel at the

versus temperature slope in V/°C.

Figure 22. Average Vo @ 1.8V supply

1.6.3 Comparator characteristics

Table 32. Comparator characteristics Table continues on the next page...

Table 32. Comparator characteristics (continued) Table continues on the next page...

1. Characterized on typical samples, not tested in production
2. 100 mV overdrive corresponds to a square wave from 50 mV below the reference (VIC) to 50 mV above the reference.
3. Input hysteresis is relative to the reference input channel and is software programmable.

1.7 Communication interfaces

1.7.1 USART interface

bit rate for USART slave synchronous mode is 20.0 Mbit/s. external device, system clock (HCLK), and capacitive loading. = standard mode for all pins; Parameters sampled at the 50 % level of the rising or falling edge. Table 33. USART interface characteristics 1 Table continues on the next page...

Table 33. USART interface characteristics 1 (continued)

1. Based on simulation; not tested in production

Figure 23. USART timing

1.7.2 I2C-bus

Table 34. I 2C-bus pins1

6 Standard-mode 4 - μs

Table continues on the next page...

1. Parameters are valid over operating temperature range unless otherwise specified. See the I2C-bus specification

Table 34. I 2C-bus pins1 (continued)

1. Guaranteed by design. Not tested in production.
2. A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the

SCL signal) to bridge the undefined region of the falling edge of SCL.

1. Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed.
2. The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output

SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.

1. In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used,

designers should allow for this when considering bus timing.

1. The MSTTIME register allows programming of certain times for the clock (SCL) high and low times. Please see i.MX

RT500 Low-Power Crossover MCU Reference Manual for further details.

1. tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the
2. The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the
3. tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission
4. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns

must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. is released. Also the acknowledge timing must meet this set-up time. Figure 24. I2C bus pins clock timing

1.7.3 I2S-bus interface

standard mode for all pins; Parameters sampled at the 50 % level of the rising or falling edge. Table 35. I 2S-bus interface pins1, 2

1. Based on simulation; not tested in production.
2. The Flexcomm Interface function clock frequency should not be above 48 MHz. See the data rates section in the I2S
3. Typical ratings are not guaranteed.
4. Based on simulation. Not tested in production.
5. Clock Divider register (DIV) = 0x0.

Figure 25. I2S-bus timing (master) Figure 26. I2S-bus timing (slave)

1.7.4 SPI interfaces (Flexcomm interfaces 0-8)

external device, system clock (HCLK), and capacitive loading.

bit rate for SPI slave mode (transmit/receive) is 25 Mbit/s. standard mode for all pins;. Parameters sampled at the 50 % level of the rising or falling edge. Table 36. SPI interfaces 1

1. Based on simulation; not tested in production

Figure 27. SPI master timing

Figure 28. SPI slave timing

1.7.5 High-Speed SPI interface (Flexcomm interface 14)

external device, system clock (HCLK), and capacitive loading. rate for SPI master mode (transmit/receive) is 50 Mbit/s. standard mode for all pins;. Parameters sampled at the 50 % level of the rising or falling edge.

Table 37. High-Speed SPI interfaces 1

1. Based on simulation; not tested in production

Figure 29. SPI master timing

Figure 30. SPI slave timing

1.7.6 SD/MMC and SDIO

rising or falling edge. Based on simulation, not tested in production. Table 38. SD/MMC and SDIO characteristics (Default Speed (DS), High Speed (HS) SDR-12 Table continues on the next page...

falling edge. Based on simulation, not tested in production. Table 39. SD/MMC and SDIO characteristics ((SDR-50, SDR-104, HS-200 (MMC)) Table continues on the next page...

Table 39. SD/MMC and SDIO characteristics ((SDR-50, SDR-104, HS-200 (MMC)) (continued) rising or falling edge. Based on simulation, not tested in production. HS-400 supported on SD port 0 only. Table 40. SD/MMC and SDIO characteristics ((DDR-50, HS DDR (MMC))

52 MHz

falling edge. Based on simulation, not tested in production. HS-400 supported on SD port 0 only. Table 41. SD/MMC and SDIO characteristics (HS-400(MMC)) Figure 31. SD/MMC and SDIO timing

1.7.7 DMIC subsystem

standard mode for all pins; Bypass bit = 0; Parameters sampled at the 50% level of the rising or falling edge. Table 42. Dynamic characteristics 1

1. Based on simulated values.

Figure 32. DMIC timing diagram

1.7.8 USB interface characteristics

Serial Bus Revision 2.0 Specification.

1.7.9 USB DCD electrical specifications

Table 43. USB DCD electrical specifications

1.7.10 USB High Speed Transceiver and PHY specifications

capable of full speed signaling as well. Serial Bus Revision 2.0 Specification with the amendments below.

• USB ENGINEERING CHANGE NOTICE
• Title: 5V Short Circuit Withstand Requirement Change
• Applies to: Universal Serial Bus Specification, Revision 2.0
• Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
• USB ENGINEERING CHANGE NOTICE
• Title: Pull-up/Pull-down resistors
• Applies to: Universal Serial Bus Specification, Revision 2.0
• USB ENGINEERING CHANGE NOTICE
• Title: Suspend Current Limit Changes
• Applies to: Universal Serial Bus Specification, Revision 2.0
• On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification
• Revision 2.0 plus errata and ecn June 4, 2010
• Battery Charging Specification (available from USB-IF)
• Revision 1.2, December 7, 2010 USB0_VBUS pin is a detector function which is 5v tolerant and complies with the above specifications without needing any external voltage division components.

1.7.11 Improved Inter-Integrated Circuit Interface (MIPI-I3C)

Table 44. MIPI-I3C specifications when communicating with legacy I 2C devices Table continues on the next page...

Table 44. MIPI-I3C specifications when communicating with legacy I 2C devices (continued) Table 45. MIPI-I3C open drain mode specifications

• ENTAS0
• ENTAS1
• ENTAS2
• ENTAS3 38.4 n 1 μ 100 μ 2 m 50 m s s s s tCBP Clock before STOP (P) condition tCAS(min)/2 — ns tMMOverlap Current master to secondary master overlap time during handoff tDIG_OD_L — ns tAVAL Bus available condition 1 — μs tIDLE Bus idle condition 1 — ms tMMLock Time internal where new master not driving SDA low tAVAL — μs 1. Cb = total capacitance of the one bus line in pF. External memory interface i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 59 NXP Semiconductors

Table 46. MIPI-I3C push-pull specifications for SDR and HDR-DDR modes

• Master mode
• Slave mode tCR+3 and tCF+3 ns tSU_PP SDA signal setup 3 — — ns tCASr Clock after repeated START (Sr) tCAS (min) — — ns tCBSr Clock before repeated START (Sr) tCAS (min)/2 — — ns Cb Capacitive load per bus line — — 50 pF 1. When communicating with an I3C Device on a mixed Bus, the tDIG_H_MIXED period must be constrained in order to make sure that I2C devices do not interpret I3C signaling as valid I2C signaling. SDA HD; STA tHD; DAT tLOW tSU; DAT tHIGH tSU; STA SR P SS tHD; STA tSP tSU; STO tBUFtf tr tf tr SCL

Figure 33. Timing definition for devices on the I2C bus

1.8 Timer modules

1.8.1 SCTimer/PWM output timing

any two SCT fixed-pin output signals; sampled at the 50% level of the rising or falling edge; values guaranteed by design. Table 47. SCTimer/PWM output dynamic characteristics

2 Architectural overview

The Arm Cortex-M33 includes two AHB-Lite buses: the code bus and the system bus. be accessed simultaneously by different bus masters.

2.1 Detailed block diagram

• Y ellow shaded blocks include dedicated DMA Ctrl.
• Orange shaded blocks support General Purpose DMA.

Figure 34. i.MX RT500 detailed block diagram

2.2 Shared system SRAM

the graphics AHB bus and the Fusion Tightly-Coupled-Memory buses.

2.3 RT500 modules list

table describes briefly about these modules. Table 48. i.MX RT500 modules list Table continues on the next page...

Table 48. i.MX RT500 modules list (continued) instruction is being fetched from memory. Table continues on the next page...

power control for low-power operation.

• In-Application Programming (IAP) and In-System Programming (ISP).
• ROM-based USB drivers (HID, CDC, MSC). Supports flash updates via USB.
• Supports booting from valid Octal/ Quad SPI, eMMC, USB, USART, SPI, and I2C. • Legacy, Single, and Dual image boot.
• OTP API for programming OTP memory.
• Random Number Generator (RNG) API. One-Time Programmable memory OTP Memories The i.MX RT500 contains up to 16 kbits one-time-programmable memory used for part configuration, key storage (as an alternative to PUF) and other uses. Clock sources

192 MHz Free Running

1 MHz Low Power Oscillator LPO System Control The 1 MHz oscillator provides an ultra

accurate to ±5% over temperature. Table continues on the next page...

PLL to achieve higher clock rates.

32 KHz Crystal Oscillator - System Control The 32KHz oscillator resides in the

four independent outputs (PFD0-3). be enabled or disabled by software. ports with a total of up to 136 GPIO pins. polarity, level or edge detection. Table continues on the next page...

I/O+ bus for fast single-cycle access. devices through a token-based protocol.

200 MHz DDR/SDR The FlexSPI

with an CACHE64 AHB-cache controller.

• Write-back
• Write-through
• Non-cached Table continues on the next page... Architectural overview i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 67 NXP Semiconductors

• USART with asynchronous operation or synchronous master or slave operation.
• SPI master or slave, with up to 4 slave selects.
• I2C, including separate master, slave, and monitor functions.
• Two I2S functions using Flexcomm Interface 6 and Flexcomm Interface
• Data for USART, SPI, and I2S traffic uses the Flexcomm Interface FIFO. The I2C function does not use the FIFO. I3C interface I3C Communication interface Two I3C master/slave interfaces are provided, both of which support DDR. Counter/Timer modules General-purpose 32-bit timers/external event counter - Counter/Timers The i.MX RT500 includes five general- purpose 32-bit timer/counters. The timer/ counter is designed to count cycles of the system derived clock or an externally- supplied clock. It can optionally generate interrupts, generate timed DMA requests, or perform other actions at specified timer values, based on four match registers. Each timer/counter also includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. SCTimer/PWM SCT/PWM Counters/Timers The SCTimer/PWM allows a wide variety of timing, counting, output modulation, and input capture operations. The inputs and outputs of the SCTimer/PWM are shared with the capture and match inputs/outputs of the 32-bit general- purpose counter/timers. The SCTimer/PWM can be configured as two 16-bit counters or a unified 32-bit counter. In the two-counter case, in addition to the counter value the following operational elements are independent for each half: Table continues on the next page... Architectural overview 68 i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 NXP Semiconductors

• State variable
• Limit, halt, stop, and start conditions.
• Values of Match/Capture registers, plus reload or capture control values. In the two-counter case, the following operational elements are global to the SCTimer/PWM, but the last three can use match conditions from either counter:
• Clock selection
• Inputs
• Events
• Outputs
• Interrupts Windowed Watchdog Timer (WWDT) WWDT Timers The purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window. A separate Watchdog Timer is provided for each of the two CPUs. Real Time Clock Timer RTC Timer Timers The RTC timer is a 32-bit timer which counts down from a preset value to zero. At zero, the preset value is reloaded and the counter continues. The RTC timer uses the 32.768 kHz clock input to create a 1 Hz or 1 kHz clock. Multi-Rate Timer MRT Timers The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each channel can be programmed with an independent time interval, and each channel operates independently from the other channels. OS/Event Timer - Timers An OS/EVENT Timer module provides a common timebase between the two CPUs for event synchronization and timestamping. The OS/EVENT Timer is comprised of a shared, free-running counter readable by each CPU and individual match and capture registers for each CPU. The shared and local counters in this module are implemented using Gray code. This will enable them to be read asynchronously by the processing domains. The main counter in the OS/EVENT Timer module begins counting immediately following power-up and continues counting through any subsequent system resets (except those caused by a new POR). Table continues on the next page... Architectural overview i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 69 NXP Semiconductors

with extremely low power consumption. for display by the LCD Display Controller.

895.1 Mbps to support 1024x480

LCD with a parallel interface. controllers are provided on i.MX RT500.

• Pulse-Density Modulation (PDM) data input for left and/or right channels on 1 or 2 buses.
• Flexible decimation.
• 16 entry FIFO for each channel.
• DC blocking or unaltered DC bias can be selected.
• Data can be transferred using DMA from deep-sleep mode without waking up the CPU, then Table continues on the next page... Architectural overview 70 i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 NXP Semiconductors

• Data can be streamed directly to I2S on Flexcomm Interface 7. Smart DMA Engine Smart DMA Controller Other Smart DMA Controller with dedicated 32 KB code RAM Flexible Input/Output FlexIO Others The Flexible Input/Output (FlexIO) module is capable of supporting a wide range of protocols including, but not limited to: UART, I2C, SPI, I2S, camera interface, display interface, PWM waveform generation, and so on Cyclic Redundancy Check(CRC) engine CRC Other The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings supports several CRC standards commonly used. To save system power and bus bandwidth, the CRC engine supports DMA transfers. Analog Peripherals 12-bit Analog to Digital Converter ADC Analog The ADC supports a resolution of 12-bit and fast conversion rates of up to 1 Msamples/s. Sequences of analog-to- digital conversions can be triggered by multiple sources. Possible trigger sources are the SCTimer/PWM, external pins, and the Arm TXEV interrupt. Temperature Sensor - Analog The temperature sensor transducer uses an intrinsic pn-junction diode reference and outputs a CTAT voltage (Complement To Absolute Temperature). The output voltage varies inversely with device temperature with an absolute accuracy of better than ±5 °C over the full temperature range (-20 °C to +70 °C). The temperature sensor is only approximately linear with a slight curvature. The output voltage is measured over different ranges of temperatures and fit with linear-least- square lines. After power-up, the temperature sensor output must be allowed to settle to its stable value before it can be used as an accurate ADC input. For an accurate measurement of the temperature sensor by the ADC, the ADC must be configured in single-channel burst mode. The last value of a nine- conversion (or more) burst provides an accurate result. Table continues on the next page... Architectural overview i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 71 NXP Semiconductors

• Trust Zone M
• AES256 Decryption Engine.
• SHA-1, SHA-2 HASH Engine.
• Physical Unclonable Function (PUF) Key Generation
• CASPAR security Cortex-M33 co- processor
• OTP memory
• Random number generator (RNG)
• On-the-Fly Decryption on FlexSPI interface On-The-Fly AES Decryption OTFAD Security The On-The-Fly AES Decryption (OTFAD) module provides an advanced hardware implementation that minimizes any incremental cycles of latency introduced by the decryption in the overall external memory access time. The OTFAD engine also includes complete hardware support for a standard AES key unwrap mechanism to decrypt a key BLOB data instruction containing the parameters needed for up to 4 unique AES contexts. True Random Number Generator TRNG Security The True Random Number Generator (TRNG) module is used to generate high quality, cryptographically secure, random data. The TRNG module is capable of generating its own entropy using an integrated ring oscillator.

3 Application information

Application information

72 i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 NXP Semiconductors

M33 active, running enhanced-while(1) code in different partitions. Typical silicon, VDDCore=1.1V, Temperature=25℃, FBB, HCLK=192MHz (FRO). All memories array/periphery ON (PDRUNCFG2/3) and only one partition clocked (AHB_SRAM_ACCESS_DISABLE register). Figure 35. Current consumption vs. memory partitions

3.2 Standard I/O pin configuration

provide a drive capability equivalent to pull-up and pull-down resistors. i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 73 NXP Semiconductors

Figure 36. Pin configuration

3.3 I/O power consumption

voltage level at the pin and the setting of the internal pull-up and pull-down resistors. need to consider any external loads connected to the pin. external capacitive loads connected to the pin in addition to powering the I/O circuitry. 74 i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 NXP Semiconductors

3.4 RTC oscillator

In the RTC oscillator circuit, only the crystal (XTAL) and the capacitances CX1 and CX2 need to be connected externally on RTCXIN and RTCXOUT. See the following figure. RTxxx RTCXIN RTCXOUT C X2 C X1 XTAL = C L C P R S L Figure 37. RTC oscillator components For best results, it is very critical to select a matching crystal for the on-chip oscillator. CPad - Pad capacitance of the RTCXIN and RTCXOUT pins (~3 pF, for each pad). CSTRAY – stray capacitance between RTCXIN and RTCXOUT pins. external components influences the optimal values of external load capacitors. i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 75 NXP Semiconductors

actual hardware board to get the accurate clock frequency. For fine tuning, output the RTC Clock to the CLOCKOUT pin and optimize the values of external load capacitors for minimum frequency deviation. To use bypass mode on RTC, remove the crystal, drive an external clock to RTCIN pin, and float the RTCOUT pin.

3.4.1 RTC Printed Circuit Board (PCB) design guidelines

• Connect the crystal and external load capacitors on the PCB as close as possible to the oscillator input and output pins of the chip.
• The length of traces in the oscillation circuit should be as short as possible and must not cross other signal lines.
• Ensure that the load capacitors CX1, CX2, and CX3, in case of third overtone crystal usage, have a common ground plane.
• Loops must be made as small as possible to minimize the noise coupled in through the PCB and to keep the parasitics as small as possible.
• Lay out the ground (GND) pattern under crystal unit.
• Do not lay out other signal lines under crystal unit for multi-layered PCB.

3.5 XTAL oscillator

In the XTAL oscillator circuit, only the crystal (XTAL) and the capacitances CX and CY need to be connected externally on XTALIN and XTALOUT. See the figure below. 76 i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 NXP Semiconductors

CL = 9 pF Cx = Cy = 2CL - CPad - 2CSTRAY Cx = Cy = 2*9 - 3 - 0 = 15 pF Although CSTRAY can be ignored in general, the actual board layout and placement of external components influences the optimal values of external load capacitors. Therefore, it is recommended to fine tune the values of external load capacitors on actual hardware board to get the accurate clock frequency. For fine tuning, measure the clock on the XTALOUT pin and optimize the values of external load capacitors for minimum frequency deviation. To use bypass mode on system oscillator, set bit 1 to "1" in the system oscillator control 0 (CLKCTL0_SYSOSCCTL0), float the XTALIN pin, and drive XTALOUT with < 0.7 V to 1.8 V. For oscillator high gain mode, a larger voltage swing is used at the crystal pin. This gives a higher noise immunity within the oscillator and less edge to edge jitter of the internal clock. When high gain mode is not required, power used by the crystal oscillator can be reduced by using low power mode. NOTE High gain mode requires a 1 megaohm resistor (RF) to be inserted.

3.5.1 XTAL Printed Circuit Board (PCB) design guidelines

• Connect the crystal and external load capacitors on the PCB as close as possible to the oscillator input and output pins of the chip.
• The length of traces in the oscillation circuit should be as short as possible and must not cross other signal lines.
• Ensure that the load capacitors C X, CY, and CX3, in case of third overtone crystal usage, have a common ground plane.
• Loops must be made as small as possible to minimize the noise coupled in through the PCB and to keep the parasitics as small as possible.
• Lay out the ground (GND) pattern under crystal unit.
• Do not lay out other signal lines under crystal unit for multi-layered PCB.

78 i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 NXP Semiconductors

3.5.2 Thermally compensated crystal oscillator (TCXO)

In the TXCO circuit, only the oscillator should be connected to the XTALIN pin while the XTALOUT pin remains floating when driving the device with a TXCO. See the following figure. XTALIN XTALOUT crystal oscillator osc_clk i.MX RT500 TCXO Figure 40. Thermally compensated crystal oscillator

3.6 Suggested USB interface solutions

or bus-powered device (see Figure 42). USB1_VDD3V3 or VDD pins are present or not. i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 79 NXP Semiconductors

4 Abbreviations

Table 49. Abbreviations

5 Pinouts

5.1 Signal multiplexing and pinouts

The table below shows the pin functions available on each pin, and for each package. These functions are selectable using IOCON control registers. pins. This allows debug to operate through reset.

use the ISP Select pins at boot, then these pins PIO1_15, PIO3_28, and PIO3_29 have pull-ups enabled by ROM; otherwise these pull-ups are not enabled at boot. The SWD pins PIO2_25 and PIO2_26 have the input buffers enabled at reset. The state of pins PIO1_15, PIO3_28, and PIO3_29 at Reset determine the boot source for the part (if configured in the Boot ROM OTP) or if the ISP handler is invoked. The JTAG functions TRST, TCK, TMS, TDI, and TDO, are selected on pins PIO0_7 to PIO0_11 by hardware when the part is in boundary scan mode. 5.2 i.MXRT500 Pinouts: 249 FOWLP package Pinouts 82 i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 NXP Semiconductors

(249FOW LP) Pin Name DEFAULT Func 0 Func 1 Func 2 Func 3 Func 4 Func 5 Func 6 Func 7 Func 8 Func 15 F14 PIO0_0 PIO0_0 PIO0_0 FC0_SCK CTIMER0_ MAT0 I2S_BRID GE_CLK_I N GPIO_INT _BMAT SEC_PIO0 G16 PIO0_1 PIO0_1 PIO0_1 FC0_TXD_ SCL_MIS O_WS CTIMER0_ MAT1 I2S_BRID GE_WS_I N SEC_PIO0 H16 PIO0_2 PIO0_2 PIO0_2 FC0_RXD _SDA_MO SI_DATA CTIMER0_ MAT2 I2S_BRID GE_DATA _IN SEC_PIO0 H15 PIO0_3 PIO0_3 PIO0_3 FC0_CTS_ SDA_SSE CTIMER0_ MAT3 FC1_SSEL SEC_PIO0 H14 PIO0_4 PIO0_4 PIO0_4 FC0_RTS_ SCL_SSE CTIMER_I NP0 FC1_SSEL CMP0_OU T SEC_PIO0 F16 PIO0_5 / ADC0_0 PIO0_5 PIO0_5 FC0_SSEL SCT0_GPI SCT0_OU CTIMER_I NP1 SEC_PIO0 F17 PIO0_6 / ADC0_8 PIO0_6 PIO0_6 FC0_SSEL SCT0_GPI SCT0_OU CTIMER0_ MAT0 SEC_PIO0 J15 PIO0_7 / TRST PIO0_7 PIO0_7 FC1_SCK SCT0_GPI SCT0_OU CTIMER1_ MAT0 I2S_BRID GE_CLK_ OUT SEC_PIO0 H12 PIO0_8 / TCK PIO0_8 PIO0_8 FC1_TXD_ SCL_MIS O_WS SCT0_GPI SCT0_OU CTIMER1_ MAT1 I2S_BRID GE_WS_O UT SEC_PIO0 H17 PIO0_9 / TMS PIO0_9 PIO0_9 FC1_RXD _SDA_MO SI_DATA SCT0_GPI SCT0_OU CTIMER1_ MAT2 I2S_BRID GE_DATA _OUT SEC_PIO0 K16 PIO0_10 / TDI PIO0_10 PIO0_10 FC1_CTS_ SDA_SSE SCT0_GPI SCT0_OU CTIMER1_ MAT3 FC0_SSEL SEC_PIO0 _10 K15 PIO0_11 / TDO PIO0_11 PIO0_11 FC1_RTS_ SCL_SSE SCT0_GPI SCT0_OU CTIMER_I NP2 FC0_SSEL SEC_PIO0 _11 Table continues on the next page... Pinouts i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 83 NXP Semiconductors

(249FOW LP) Pin Name DEFAULT Func 0 Func 1 Func 2 Func 3 Func 4 Func 5 Func 6 Func 7 Func 8 Func 15 E14 PIO0_12 / ADC0_1 PIO0_12 PIO0_12 FC1_SSEL SCT0_GPI SCT0_OU CTIMER_I NP3 SEC_PIO0 _12 F15 PIO0_13 / ADC0_9 PIO0_13 PIO0_13 FC1_SSEL SCT0_GPI SCT0_OU CTIMER0_ MAT1 SEC_PIO0 _13 B12 PIO0_14 PIO0_14 PIO0_14 FC2_SCK SCT0_GPI SCT0_OU CTIMER2_ MAT0 I2S_BRID GE_CLK_I N SEC_PIO0 _14 B15 PIO0_15 PIO0_15 PIO0_15 FC2_TXD_ SCL_MIS O_WS SCT0_GPI SCT0_OU CTIMER2_ MAT1 I2S_BRID GE_WS_I N SEC_PIO0 _15 A16 PIO0_16 PIO0_16 PIO0_16 FC2_RXD _SDA_MO SI_DATA SCT0_GPI SCT0_OU CTIMER2_ MAT2 I2S_BRID GE_DATA _IN SEC_PIO0 _16 B17 PIO0_17 PIO0_17 PIO0_17 FC2_CTS_ SDA_SSE SCT0_GPI SCT0_OU CTIMER2_ MAT3 FC5_SSEL SEC_PIO0 _17 B16 PIO0_18 PIO0_18 PIO0_18 FC2_RTS_ SCL_SSE SCT0_GPI SCT0_OU CTIMER_I NP4 FC5_SSEL SEC_PIO0 _18 F13 PIO0_19 / ADC0_2 PIO0_19 PIO0_19 FC2_SSEL SCT0_GPI SCT0_OU CTIMER_I NP5 UTICK_CA SEC_PIO0 _19 A14 PIO0_21 PIO0_21 PIO0_21 FC3_SCK SCT0_GPI SCT0_OU CTIMER3_ MAT0 CTIMER_I NP11 TRACECL K SEC_PIO0 _21 B14 PIO0_22 PIO0_22 PIO0_22 FC3_TXD_ SCL_MIS O_WS SCT0_GPI SCT0_OU CTIMER3_ MAT1 CTIMER_I NP7 TRACEDA TA[0] SEC_PIO0 _22 C13 PIO0_23 PIO0_23 PIO0_23 FC3_RXD _SDA_MO SI_DATA SCT0_GPI SCT0_OU CTIMER3_ MAT2 CTIMER0_ MAT3 TRACEDA TA[1] SEC_PIO0 _23 D13 PIO0_24 PIO0_24 PIO0_24 FC3_CTS_ SDA_SSE SCT0_GPI SCT0_OU CTIMER3_ MAT3 FC2_SSEL TRACEDA TA[2] CLKOUT SEC_PIO0 _24 Table continues on the next page... Pinouts 84 i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 NXP Semiconductors

(249FOW LP) Pin Name DEFAULT Func 0 Func 1 Func 2 Func 3 Func 4 Func 5 Func 6 Func 7 Func 8 Func 15 C12 PIO0_25 PIO0_25 PIO0_25 FC3_RTS_ SCL_SSE FREQME_ GPIO_CLK CTIMER_I NP6 FC2_SSEL TRACEDA TA[3] CLKIN SEC_PIO0 _25 A12 PIO0_28 PIO0_28 PIO0_28 FC4_SCK CTIMER4_ MAT0 I2S_BRID GE_CLK_ OUT SEC_PIO0 _28 B11 PIO0_29 PIO0_29 PIO0_29 FC4_TXD_ SCL_MIS O_WS CTIMER4_ MAT1 I2S_BRID GE_WS_O UT SEC_PIO0 _29 D14 PIO0_30 PIO0_30 PIO0_30 FC4_RXD _SDA_MO SI_DATA CTIMER4_ MAT2 I2S_BRID GE_DATA _OUT SEC_PIO0 _30 D12 PIO0_31 PIO0_31 PIO0_31 FC4_CTS_ SDA_SSE SCT0_GPI SCT0_OU CTIMER4_ MAT3 FC3_SSEL SEC_PIO0 _31 A10 PIO1_0 PIO1_0 PIO1_0 FC4_RTS_ SCL_SSE SCT0_GPI SCT0_OU CTIMER_I NP8 FC3_SSEL K2 PIO1_3 PIO1_3 PIO1_3 FC5_SCK HS_SPI1_ SCK K1 PIO1_4 PIO1_4 PIO1_4 FC5_TXD_ SCL_MIS O_WS HS_SPI1_ MISO L2 PIO1_5 PIO1_5 PIO1_5 FC5_RXD _SDA_MO SI_DATA HS_SPI1_ MOSI N4 PIO1_6 PIO1_6 PIO1_6 FC5_CTS_ SDA_SSE SCT0_GPI SCT0_OU FC4_SSEL HS_SPI1_ SSELN0 M1 PIO1_7 PIO1_7 PIO1_7 FC5_RTS_ SCL_SSE SCT0_GPI SCT0_OU CTIMER_I NP9 FC4_SSEL HS_SPI1_ SSELN1 M5 PIO1_10 PIO1_10 PIO1_10 MCLK FREQME_ GPIO_CLK CTIMER_I NP10 CLKOUT Table continues on the next page... Pinouts i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 85 NXP Semiconductors

(249FOW LP) Pin Name DEFAULT Func 0 Func 1 Func 2 Func 3 Func 4 Func 5 Func 6 Func 7 Func 8 Func 15 K13 PIO1_11 PIO1_11 PIO1_11 HS_SPI0_ SCK CTIMER2_ MAT0 K14 PIO1_12 PIO1_12 PIO1_12 HS_SPI0_ MISO CTIMER2_ MAT1 K17 PIO1_13 PIO1_13 PIO1_13 HS_SPI0_ MOSI CTIMER2_ MAT2 L16 PIO1_14 PIO1_14 PIO1_14 HS_SPI0_ SSELN0 CTIMER2_ MAT3 M16 PIO1_15 / ISP0 PIO1_15 PIO1_15 HS_SPI0_ SSELN1 CTIMER3_ MAT0 T17 PIO1_18 PIO1_18 PIO1_18 FLEXSPI0 _SCLK SCT0_GPI CTIMER3_ MAT3 U16 PIO1_19 PIO1_19 PIO1_19 FLEXSPI0 _SS0_N SCT0_OU CTIMER4_ MAT0 CLKOUT T15 PIO1_20 PIO1_20 PIO1_20 FLEXSPI0 _DATA0 SCT0_GPI CTIMER4_ MAT1 T14 PIO1_21 PIO1_21 PIO1_21 FLEXSPI0 _DATA1 SCT0_OU CTIMER4_ MAT2 R13 PIO1_22 PIO1_22 PIO1_22 FLEXSPI0 _DATA2 SCT0_GPI CTIMER4_ MAT3 R12 PIO1_23 PIO1_23 PIO1_23 FLEXSPI0 _DATA3 SCT0_OU CTIMER_I NP8 N12 PIO1_24 PIO1_24 PIO1_24 FLEXSPI0 _DATA4 SCT0_GPI R14 PIO1_25 PIO1_25 PIO1_25 FLEXSPI0 _DATA5 SCT0_OU P14 PIO1_26 PIO1_26 PIO1_26 FLEXSPI0 _DATA6 SCT0_GPI P13 PIO1_27 PIO1_27 PIO1_27 FLEXSPI0 _DATA7 SCT0_OU U14 PIO1_28 PIO1_28 PIO1_28 FLEXSPI0 _DQS SCT0_GPI Table continues on the next page... Pinouts 86 i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 NXP Semiconductors

(249FOW LP) Pin Name DEFAULT Func 0 Func 1 Func 2 Func 3 Func 4 Func 5 Func 6 Func 7 Func 8 Func 15 U12 PIO1_29 PIO1_29 PIO1_29 FLEXSPI0 _SS1_N SCT0_OU UTICK_CA CTIMER_I NP13 FLEXSPI0 _SCLK_N R5 PIO1_30 PIO1_30 PIO1_30 SD0_CLK SCT0_GPI R6 PIO1_31 PIO1_31 PIO1_31 SD0_CMD SCT0_GPI U4 PIO2_0 PIO2_0 PIO2_0 SD0_D[0] SCT0_GPI SmartDMA _PIO0 T4 PIO2_1 PIO2_1 PIO2_1 SD0_D[1] SCT0_GPI SmartDMA _PIO1 T7 PIO2_2 PIO2_2 PIO2_2 SD0_D[2] SCT0_OU SmartDMA _PIO2 U6 PIO2_3 PIO2_3 PIO2_3 SD0_D[3] SCT0_OU SmartDMA _PIO3 P6 PIO2_4 PIO2_4 PIO2_4 SD0_WR_ PRT SCT0_OU T2 SD0_DS SmartDMA _PIO4 P5 PIO2_5 PIO2_5 PIO2_5 SD0_D[4] SCT0_OU T3 FC8_SCK SmartDMA _PIO5 R4 PIO2_6 PIO2_6 PIO2_6 SD0_D[5] SCT0_GPI CTIMER1_ MAT0 FC8_TXD_ SCL_MIS O_WS SmartDMA _PIO6 P4 PIO2_7 PIO2_7 PIO2_7 SD0_D[6] SCT0_GPI CTIMER1_ MAT1 FC8_RXD _SDA_MO SI_DATA SmartDMA _PIO7 T6 PIO2_8 PIO2_8 PIO2_8 SD0_D[7] SCT0_OU CTIMER1_ MAT2 FC8_CTS_ SDA_SSE SmartDMA _PIO8 T3 PIO2_9 PIO2_9 PIO2_9 SD0_CAR D_DET_N SCT0_OU CTIMER1_ MAT3 FC8_CTS_ SDA_SSE SmartDMA _PIO9 N5 PIO2_10 PIO2_10 PIO2_10 SD0_RES ET_N SCT0_GPI CTIMER2_ MAT0 FC8_SSEL SmartDMA _PIO10 Table continues on the next page... Pinouts i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 87 NXP Semiconductors

(249FOW LP) Pin Name DEFAULT Func 0 Func 1 Func 2 Func 3 Func 4 Func 5 Func 6 Func 7 Func 8 Func 15 R2 PIO2_11 PIO2_11 PIO2_11 SD0_VOL T SCT0_GPI CTIMER2_ MAT1 FC8_SSEL SmartDMA _PIO11 E15 PIO2_14 / CMP0_A PIO2_14 PIO2_14 SCT0_OU CTIMER_I NP1 32KHZ_CL KOUT SmartDMA _PIO14 D17 PIO2_15 / CMP0_D PIO2_15 PIO2_15 SCT0_OU T9 CLKIN SmartDMA _PIO15 N3 PIO2_24 PIO2_24 PIO2_24 SWO GPIO_INT _BMAT SmartDMA _PIO24 M2 PIO2_25 PIO2_25 PIO2_25 SWCLK SmartDMA _PIO25 M4 PIO2_26 PIO2_26 PIO2_26 SWDIO SmartDMA _PIO26 M3 PIO2_27 PIO2_27 PIO2_27 USB1_OV ERCURRE NTN SmartDMA _PIO27 P1 PIO2_28 PIO2_28 PIO2_28 USB1_PO RTPWRN SmartDMA _PIO28 B10 PIO2_29 PIO2_29 PIO2_29 I3C0_SCL SCT0_OU T0 CLKOUT SmartDMA _PIO029 D10 PIO2_30 PIO2_30 PIO2_30 I3C0_SDA SCT0_OU T3 CLKIN CMP0_OU T SmartDMA _PIO30 C14 PIO2_31 / CMP0_B PIO2_31 PIO2_31 I3C0_PUR SCT0_OU UTICK_CA CTIMER_I NP15 SWO SmartDMA _PIO31 T2 USB1_VB US USB1_VB US K5 USB1_VD D3V3 USB1_VD D3V3 T1 USB1_DM USB1_DM U2 USB1_DP USB1_DP E4 PMIC_MO DE1 PMIC_MO DE1 D3 PMIC_MO DE0 PMIC_MO DE0 Table continues on the next page... Pinouts 88 i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 NXP Semiconductors

(249FOW LP) Pin Name DEFAULT Func 0 Func 1 Func 2 Func 3 Func 4 Func 5 Func 6 Func 7 Func 8 Func 15 K6 PMIC_I2C _SDA PMIC_I2C _SDA K4 PMIC_I2C _SCL PMIC_I2C _SCL D5 PMIC_IRQ PMIC_IRQ C5 LDO_ENA BLE PMIC_LD O_ENABL E B4 XTALIN XTALIN A4 XTALOUT XTALOUT A2 RTCXIN RTCXIN B3 RTCXOUT RTCXOUT C4 RESETN RESETN F12 VREFP VREFP G12 VREFN VREFN D16 PIO3_1 PIO3_1 PIO3_1 PDM_CLK PDM_DAT A23 FC0_TXD_ SCL_MIS O_WS I3C1_SCL C16 PIO3_2 PIO3_2 PIO3_2 PDM_CLK PDM_DAT A45 FC0_RXD _SDA_MO SI_DATA I3C1_SDA D15 PIO3_3 PIO3_3 PIO3_3 PDM_CLK PDM_DAT A67 LCD_D23 FC0_CTS_ SDA_SSE I3C1_PUR CMP0_OU T A8 PIO3_8 PIO3_8 PIO3_8 SD1_CLK LCD_D9 CTIMER0_ MAT0 FC10_SC K B8 PIO3_9 PIO3_9 PIO3_9 SD1_CMD LCD_D10 CTIMER0_ MAT1 FC10_TXD _SCL_MIS O Table continues on the next page... Pinouts i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 89 NXP Semiconductors

(249FOW LP) Pin Name DEFAULT Func 0 Func 1 Func 2 Func 3 Func 4 Func 5 Func 6 Func 7 Func 8 Func 15 C8 PIO3_10 PIO3_10 PIO3_10 SD1_D[0] LCD_D11 CTIMER0_ MAT2 FC10_RX D_SDA_M OSI C10 PIO3_11 PIO3_11 PIO3_11 SD1_D[1] LCD_D12 CTIMER0_ MAT3 FC10_CTS _SDA_SS ELN0 A6 PIO3_12 PIO3_12 PIO3_12 SD1_D[2] LCD_D13 CTIMER_I NP0 FC10_RTS _SCL_SS ELN1 B7 PIO3_13 PIO3_13 PIO3_13 SD1_D[3] LCD_D14 CTIMER_I NP1 FC10_SSE LN2 D9 PIO3_14 / CMP0_E PIO3_14 PIO3_14 SD1_WR_ PRT LCD_D15 CTIMER3_ MAT0 SD1_DS FC10_SSE LN3 E10 PIO3_15 PIO3_15 PIO3_15 SD1_D[4] LCD_D16 CTIMER3_ MAT1 FC5_SCK C9 PIO3_16 PIO3_16 PIO3_16 SD1_D[5] LCD_D17 CTIMER3_ MAT2 FC5_TXD_ SCL_MIS O_WS D8 PIO3_17 PIO3_17 PIO3_17 SD1_D[6] LCD_D18 CTIMER3_ MAT3 FC5_RXD _SDA_MO SI_DATA B6 PIO3_18 PIO3_18 PIO3_18 SD1_D[7] LCD_D19 CTIMER4_ MAT0 FC5_CTS_ SDA_SSE C6 PIO3_19 PIO3_19 PIO3_19 SD1_CAR D_DET_N LCD_D20 CTIMER4_ MAT1 MCLK D6 PIO3_20 PIO3_20 PIO3_20 SD1_RES ET_N LCD_D21 CTIMER4_ MAT2 E5 PIO3_21 PIO3_21 PIO3_21 SD1_VOL T LCD_D22 CTIMER4_ MAT3 GPIO_INT _BMAT R16 PIO3_25 PIO3_25 PIO3_25 FC6_SCK T16 PIO3_26 PIO3_26 PIO3_26 FC6_TXD_ SCL_MIS O_WS Table continues on the next page... Pinouts 90 i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 NXP Semiconductors

(249FOW LP) Pin Name DEFAULT Func 0 Func 1 Func 2 Func 3 Func 4 Func 5 Func 6 Func 7 Func 8 Func 15 N14 PIO3_27 PIO3_27 PIO3_27 FC6_RXD _SDA_MO SI_DATA N13 PIO3_28 / ISP1 PIO3_28 PIO3_28 FC6_CTS_ SDA_SSE M13 PIO3_29 / ISP2 PIO3_29 PIO3_29 FC6_RTS_ SCL_SSE N15 PIO4_0 PIO4_0 PIO4_0 FC7_SCK FREQME_ GPIO_CLK CLKOUT M15 PIO4_1 PIO4_1 PIO4_1 FC7_TXD_ SCL_MIS O_WS CLKIN M17 PIO4_2 PIO4_2 PIO4_2 FC7_RXD _SDA_MO SI_DATA M14 PIO4_3 PIO4_3 PIO4_3 FC7_CTS_ SDA_SSE P17 PIO4_4 PIO4_4 PIO4_4 FC7_RTS_ SCL_SSE FC1_SCK P16 PIO4_5 PIO4_5 PIO4_5 FC7_SSEL FC1_TXD_ SCL_MIS O_WS P15 PIO4_6 PIO4_6 PIO4_6 FC7_SSEL FC1_RXD _SDA_MO SI_DATA D2 MIPI_DSI_ CLKP MIPI_DSI_ CLKP D1 MIPI_DSI_ CLKN MIPI_DSI_ CLKN Table continues on the next page... Pinouts i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 91 NXP Semiconductors

(249FOW LP) Pin Name DEFAULT Func 0 Func 1 Func 2 Func 3 Func 4 Func 5 Func 6 Func 7 Func 8 Func 15 B1 MIPI_DSI_ D0P MIPI_DSI_ D0P C2 MIPI_DSI_ D0N MIPI_DSI_ D0N E3 MIPI_DSI_ D1P MIPI_DSI_ D1P F3 MIPI_DSI_ D1N MIPI_DSI_ D1N J8 MIPI_DSI_ VDD11 MIPI_DSI_ VD11 F8 MIPI_DSI_ VDD18 MIPI_DSI_ VDD18 MIPI_DSI_ VDDA_CA P MIPI_DSI_ VDDA_CA P F4 MIPI_DSI_ VSS MIPI_DSI_ VSS H2 PIO4_11 PIO4_11 PIO4_11 FC2_SCK FLEXSPI1 _SCLK SD1_CLK H1 PIO4_12 PIO4_12 PIO4_12 FC2_TXD_ SCL_MIS O_WS FLEXSPI1 _DATA0 SD1_CMD G2 PIO4_13 PIO4_13 PIO4_13 FC2_RXD _SDA_MO SI_DATA FLEXSPI1 _DATA1 SD1_D[0] F1 PIO4_14 PIO4_14 PIO4_14 FC2_CTS_ SDA_SSE FLEXSPI1 _DATA2 SD1_D[1] K3 PIO4_15 PIO4_15 PIO4_15 FC2_RTS_ SCL_SSE FLEXSPI1 _DATA3 SD1_D[2] H3 PIO4_16 PIO4_16 PIO4_16 FC2_SSEL FLEXSPI1 _DQS SD1_D[3] Table continues on the next page... Pinouts 92 i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 NXP Semiconductors

(249FOW LP) Pin Name DEFAULT Func 0 Func 1 Func 2 Func 3 Func 4 Func 5 Func 6 Func 7 Func 8 Func 15 F2 PIO4_17 PIO4_17 PIO4_17 FC2_SSEL FLEXSPI1 _SS1_N FLEXSPI1 _SCLK_N SD1_WR_ PRT E13 PIO4_18 / ADC0_6 PIO4_18 PIO4_18 FLEXSPI1 _SS0_N SD1_D[4] R8 PIO4_20 PIO4_20 PIO4_20 DBI_CSX SD1_D[6] FC11_SC K FLEXIO_D P10 PIO4_21 PIO4_21 PIO4_21 DBI_DCX SD1_D[7] FC11_TXD _SCL_MIS O FLEXIO_D U10 PIO4_22 PIO4_22 PIO4_22 SD1_CAR D_DET_N FC11_RX D_SDA_M OSI FLEXIO_D T8 PIO4_23 PIO4_23 PIO4_23 DBI_RWD X LCD_ENA BLE SD1_RES ET_N FC11_CTS _SDA_SS ELN0 TRACECL K FLEXIO_D T10 PIO4_24 PIO4_24 PIO4_24 DBI_WRX LCD_DTC LK SD1_VOL T FC11_RTS _SCL_SS ELN1 TRACEDA TA[0] FLEXIO_D T11 PIO4_25 PIO4_25 PIO4_25 DBI_E LCD_HSY NC FC11_SSE LN2 TRACEDA TA[1] FLEXIO_D T12 PIO4_26 PIO4_26 PIO4_26 LCD_VSY NC FC11_SSE LN3 TRACEDA TA[2] FLEXIO_D P9 PIO4_27 PIO4_27 PIO4_27 LCD_D0 DBI_D0 TRACEDA TA[3] FLEXIO_D U8 PIO4_28 PIO4_28 PIO4_28 LCD_D1 DBI_D1 FLEXIO_D P8 PIO4_29 PIO4_29 PIO4_29 LCD_D2 DBI_D2 FLEXIO_D N8 PIO4_30 PIO4_30 PIO4_30 LCD_D3 DBI_D3 FC12_TXD _SCL_MIS O FLEXIO_D Table continues on the next page... Pinouts i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 93 NXP Semiconductors

(249FOW LP) Pin Name DEFAULT Func 0 Func 1 Func 2 Func 3 Func 4 Func 5 Func 6 Func 7 Func 8 Func 15 N10 PIO4_31 PIO4_31 PIO4_31 LCD_D4 DBI_D4 FC12_RX D_SDA_M OSI FLEXIO_D P12 PIO5_0 PIO5_0 PIO5_0 LCD_D5 DBI_D5 FC12_CTS _SDA_SS ELN0 FLEXIO_D M9 PIO5_1 PIO5_1 PIO5_1 LCD_D6 DBI_D6 FC12_RTS _SCL_SS ELN1 FLEXIO_D R9 PIO5_2 PIO5_2 PIO5_2 LCD_D7 DBI_D7 FC12_SSE LN2 LOW_FRE Q_CLKOU T FLEXIO_D R10 PIO5_3 PIO5_3 PIO5_3 LCD_D8 DBI_D8 FC12_SSE LN3 LOW_FRE Q_CLKOU T_N FLEXIO_D P2 PIO5_4 PIO5_4 PIO5_4 LCD_D9 DBI_D9 PDM_CLK P3 PIO5_8 PIO5_8 PIO5_8 LCD_D13 DBI_D13 PDM_DAT A01 H5 PIO5_15 PIO5_15 PIO5_15 LCD_D20 FLEXSPI1 _DATA4 FC4_CTS_ SDA_SSE H4 PIO5_16 PIO5_16 PIO5_16 LCD_D21 FLEXSPI1 _DATA5 FC4_RTS_ SCL_SSE J3 PIO5_17 PIO5_17 PIO5_17 LCD_D22 FLEXSPI1 _DATA6 FC4_SSEL J4 PIO5_18 PIO5_18 PIO5_18 LCD_D23 FLEXSPI1 _DATA7 FC4_SSEL J12, J13,K12, M10,M12 VDDIO_0 Table continues on the next page... Pinouts 94 i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 NXP Semiconductors

(249FOW LP) Pin Name DEFAULT Func 0 Func 1 Func 2 Func 3 Func 4 Func 5 Func 6 Func 7 Func 8 Func 15 E9, F10,F11, F9,J5 J6 VDDIO_1 N6, P7 VDDIO_2 M8 N9 VDDIO_3 F6, F7 VDDIO_4 G9, H10,H8, H9,J10, J11,J9, K10,K8, K9, L9 VDDCORE D4, B2 VDD_AO1 H13 VDDA_AD C1V8 E12 VDDA_BIA S D11, D7 VSSA A1, A17, C3, C7, C11, C15, E7, E11, G3, G4, G5, G7, G8, G10, G11, G13, G14, G15, H11, K7, K11, L3, L4, L5, L6, L7, L8, L10, L11, L12, L13, L14, L15, VSS Table continues on the next page... Pinouts i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 95 NXP Semiconductors

(249FOW LP) Pin Name DEFAULT Func 0 Func 1 Func 2 Func 3 Func 4 Func 5 Func 6 Func 7 Func 8 Func 15 M7, M11, N7, N11, P11, R3, R7, R11, R15, U1, U17 G6, M6, H7, J7, J14, H6, VDD1V8 E8 VDD1V8_1 Pinouts 96 i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 NXP Semiconductors

5.3 i.MX RT500 Pinouts: 141 CSP package Pinouts i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 97 NXP Semiconductors

(141WLC SP) Pin Name DEFAULT Func 0 Func 1 Func 2 Func 3 Func 4 Func 5 Func 6 Func 7 Func 8 Func 15 J1 PIO0_0 PIO0_0 PIO0_0 FC0_SCK CTIMER0_ MAT0 I2S_BRID GE_CLK_I N GPIO_INT _BMAT G3 PIO0_1 PIO0_1 PIO0_1 FC0_TXD_ SCL_MIS O_WS CTIMER0_ MAT1 I2S_BRID GE_WS_I N F1 PIO0_10 / TDI PIO0_10 PIO0_10 FC1_CTS_ SDA_SSE SCT0_GPI SCT0_OU CTIMER1_ MAT3 FC0_SSEL E3 PIO0_11 / TDO PIO0_11 PIO0_11 FC1_RTS_ SCL_SSE SCT0_GPI SCT0_OU CTIMER_I NP2 FC0_SSEL G5 PIO0_12 / ADC0_1 PIO0_12 PIO0_12 FC1_SSEL SCT0_GPI SCT0_OU CTIMER_I NP3 J2 PIO0_13 / ADC0_9 PIO0_13 PIO0_13 FC1_SSEL SCT0_GPI SCT0_OU CTIMER0_ MAT1 K6 PIO0_14 PIO0_14 PIO0_14 FC2_SCK SCT0_GPI SCT0_OU CTIMER2_ MAT0 I2S_BRID GE_CLK_I N K4 PIO0_15 PIO0_15 PIO0_15 FC2_TXD_ SCL_MIS O_WS SCT0_GPI SCT0_OU CTIMER2_ MAT1 I2S_BRID GE_WS_I N M3 PIO0_16 PIO0_16 PIO0_16 FC2_RXD _SDA_MO SI_DATA SCT0_GPI SCT0_OU CTIMER2_ MAT2 I2S_BRID GE_DATA _IN M2 PIO0_17 PIO0_17 PIO0_17 FC2_CTS_ SDA_SSE SCT0_GPI SCT0_OU CTIMER2_ MAT3 FC5_SSEL J4 PIO0_18 PIO0_18 PIO0_18 FC2_RTS_ SCL_SSE SCT0_GPI SCT0_OU CTIMER_I NP4 FC5_SSEL H4 PIO0_19 / ADC0_2 PIO0_19 PIO0_19 FC2_SSEL SCT0_GPI SCT0_OU CTIMER_I NP5 UTICK_CA Table continues on the next page... Pinouts 98 i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 NXP Semiconductors

(141WLC SP) Pin Name DEFAULT Func 0 Func 1 Func 2 Func 3 Func 4 Func 5 Func 6 Func 7 Func 8 Func 15 H2 PIO0_2 PIO0_2 PIO0_2 FC0_RXD _SDA_MO SI_DATA CTIMER0_ MAT2 I2S_BRID GE_DATA _IN M4 PIO0_21 PIO0_21 PIO0_21 FC3_SCK SCT0_GPI SCT0_OU CTIMER3_ MAT0 CTIMER_I NP11 TRACECL K J5 PIO0_22 PIO0_22 PIO0_22 FC3_TXD_ SCL_MIS O_WS SCT0_GPI SCT0_OU CTIMER3_ MAT1 CTIMER_I NP7 TRACEDA TA[0] L5 PIO0_23 PIO0_23 PIO0_23 FC3_RXD _SDA_MO SI_DATA SCT0_GPI SCT0_OU CTIMER3_ MAT2 CTIMER0_ MAT3 TRACEDA TA[1] L4 PIO0_24 PIO0_24 PIO0_24 FC3_CTS_ SDA_SSE SCT0_GPI SCT0_OU CTIMER3_ MAT3 FC2_SSEL TRACEDA TA[2] CLKOUT H6 PIO0_25 PIO0_25 PIO0_25 FC3_RTS_ SCL_SSE FREQME_ GPIO_CLK CTIMER_I NP6 FC2_SSEL TRACEDA TA[3] CLKIN M6 PIO0_28 PIO0_28 PIO0_28 FC4_SCK CTIMER4_ MAT0 I2S_BRID GE_CLK_ OUT J7 PIO0_29 PIO0_29 PIO0_29 FC4_TXD_ SCL_MIS O_WS CTIMER4_ MAT1 I2S_BRID GE_WS_O UT G2 PIO0_3 PIO0_3 PIO0_3 FC0_CTS_ SDA_SSE CTIMER0_ MAT3 FC1_SSEL L3 PIO0_30 PIO0_30 PIO0_30 FC4_RXD _SDA_MO SI_DATA CTIMER4_ MAT2 I2S_BRID GE_DATA _OUT J6 PIO0_31 PIO0_31 PIO0_31 FC4_CTS_ SDA_SSE SCT0_GPI SCT0_OU CTIMER4_ MAT3 FC3_SSEL Table continues on the next page... Pinouts i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 99 NXP Semiconductors

(141WLC SP) Pin Name DEFAULT Func 0 Func 1 Func 2 Func 3 Func 4 Func 5 Func 6 Func 7 Func 8 Func 15 F4 PIO0_4 PIO0_4 PIO0_4 FC0_RTS_ SCL_SSE CTIMER_I NP0 FC1_SSEL CMP0_OU T H3 PIO0_5 / ADC0_0 PIO0_5 PIO0_5 FC0_SSEL SCT0_GPI SCT0_OU CTIMER_I NP1 K1 PIO0_6 / ADC0_8 PIO0_6 PIO0_6 FC0_SSEL SCT0_GPI SCT0_OU CTIMER0_ MAT0 E4 PIO0_7 / TRST PIO0_7 PIO0_7 FC1_SCK SCT0_GPI SCT0_OU CTIMER1_ MAT0 I2S_BRID GE_CLK_ OUT G1 PIO0_8 / TCK PIO0_8 PIO0_8 FC1_TXD_ SCL_MIS O_WS SCT0_GPI SCT0_OU CTIMER1_ MAT1 I2S_BRID GE_WS_O UT F3 PIO0_9 / TMS PIO0_9 PIO0_9 FC1_RXD _SDA_MO SI_DATA SCT0_GPI SCT0_OU CTIMER1_ MAT2 I2S_BRID GE_DATA _OUT L7 PIO1_0 PIO1_0 PIO1_0 FC4_RTS_ SCL_SSE SCT0_GPI SCT0_OU CTIMER_I NP8 FC3_SSEL D3 PIO1_11 PIO1_11 PIO1_11 HS_SPI0_ SCK CTIMER2_ MAT0 E2 PIO1_12 PIO1_12 PIO1_12 HS_SPI0_ MISO CTIMER2_ MAT1 D2 PIO1_13 PIO1_13 PIO1_13 HS_SPI0_ MOSI CTIMER2_ MAT2 C2 PIO1_14 PIO1_14 PIO1_14 HS_SPI0_ SSELN0 CTIMER2_ MAT3 D1 PIO1_15 / ISP0 PIO1_15 PIO1_15 HS_SPI0_ SSELN1 CTIMER3_ MAT0 A5 PIO1_18 PIO1_18 PIO1_18 FLEXSPI0 _SCLK SCT0_GPI CTIMER3_ MAT3 D4 PIO1_19 PIO1_19 PIO1_19 FLEXSPI0 _SS0_N SCT0_OU CTIMER4_ MAT0 CLKOUT Table continues on the next page... Pinouts 100 i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 NXP Semiconductors

(141WLC SP) Pin Name DEFAULT Func 0 Func 1 Func 2 Func 3 Func 4 Func 5 Func 6 Func 7 Func 8 Func 15 B5 PIO1_20 PIO1_20 PIO1_20 FLEXSPI0 _DATA0 SCT0_GPI CTIMER4_ MAT1 C5 PIO1_21 PIO1_21 PIO1_21 FLEXSPI0 _DATA1 SCT0_OU CTIMER4_ MAT2 D5 PIO1_22 PIO1_22 PIO1_22 FLEXSPI0 _DATA2 SCT0_GPI CTIMER4_ MAT3 C6 PIO1_23 PIO1_23 PIO1_23 FLEXSPI0 _DATA3 SCT0_OU CTIMER_I NP8 A6 PIO1_28 PIO1_28 PIO1_28 FLEXSPI0 _DQS SCT0_GPI F11 PIO1_3 PIO1_3 PIO1_3 FC5_SCK HS_SPI1_ SCK F12 PIO1_4 PIO1_4 PIO1_4 FC5_TXD_ SCL_MIS O_WS HS_SPI1_ MISO E12 PIO1_5 PIO1_5 PIO1_5 FC5_RXD _SDA_MO SI_DATA HS_SPI1_ MOSI E9 PIO1_6 PIO1_6 PIO1_6 FC5_CTS_ SDA_SSE SCT0_GPI SCT0_OU FC4_SSEL HS_SPI1_ SSELN0 F9 PIO1_7 PIO1_7 PIO1_7 FC5_RTS_ SCL_SSE SCT0_GPI SCT0_OU CTIMER_I NP9 FC4_SSEL HS_SPI1_ SSELN1 PIO1_9 / ADC0_12 / CMP1_B PIO1_9 PIO1_9 FC5_SSEL SCT0_GPI UTICK_CA CTIMER1_ MAT3 HS_SPI1_ SSELN3 K2 PIO2_14 / CMP0_A PIO2_14 PIO2_14 SCT0_OU CTIMER_I NP1 32KHZ_CL KOUT SmartDMA _PIO14 L1 PIO2_15 / CMP0_D PIO2_15 PIO2_15 SCT0_OU T9 CLKIN SmartDMA _PIO15 E8 PIO2_24 PIO2_24 PIO2_24 SWO GPIO_INT _BMAT SmartDMA _PIO24 Table continues on the next page... Pinouts i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 101 NXP Semiconductors

(141WLC SP) Pin Name DEFAULT Func 0 Func 1 Func 2 Func 3 Func 4 Func 5 Func 6 Func 7 Func 8 Func 15 F10 PIO2_25 PIO2_25 PIO2_25 SWCLK SmartDMA _PIO25 E11 PIO2_26 PIO2_26 PIO2_26 SWDIO SmartDMA _PIO26 E10 PIO2_27 PIO2_27 PIO2_27 USB1_OV ERCURRE NTN SmartDMA _PIO27 M7 PIO2_29 PIO2_29 PIO2_29 I3C0_SCL SCT0_OU T0 CLKOUT SmartDMA _PIO29 K7 PIO2_30 PIO2_30 PIO2_30 I3C0_SDA SCT0_OU T3 CLKIN CMP0_OU T SmartDMA _PIO30 K5 PIO2_31 / CMP0_B PIO2_31 PIO2_31 I3C0_PUR SCT0_OU UTICK_CA CTIMER_I NP15 SWO SmartDMA _PIO31 A4 PIO3_28 / ISP1 PIO3_28 PIO3_28 FC6_CTS_ SDA_SSE B4 PIO3_29 / ISP2 PIO3_29 PIO3_29 FC6_RTS_ SCL_SSE B8 PIO4_20 PIO4_20 PIO4_20 DBI_CSX SD1_D[6] FC11_SC K FLEXIO_D B7 PIO4_21 PIO4_21 PIO4_21 DBI_DCX SD1_D[7] FC11_TXD _SCL_MIS O FLEXIO_D A8 PIO4_22 PIO4_22 PIO4_22 SD1_CAR D_DET_N FC11_RX D_SDA_M OSI FLEXIO_D E7 PIO4_23 PIO4_23 PIO4_23 DBI_RWD X LCD_ENA BLE SD1_RES ET_N FC11_CTS _SDA_SS ELN0 TRACECL K FLEXIO_D C7 PIO4_24 PIO4_24 PIO4_24 DBI_WRX LCD_DTC LK SD1_VOL T FC11_RTS _SCL_SS ELN1 TRACEDA TA[0] FLEXIO_D Table continues on the next page... Pinouts 102 i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 NXP Semiconductors

(141WLC SP) Pin Name DEFAULT Func 0 Func 1 Func 2 Func 3 Func 4 Func 5 Func 6 Func 7 Func 8 Func 15 D7 PIO4_25 PIO4_25 PIO4_25 DBI_E LCD_HSY NC FC11_SSE LN2 TRACEDA TA[1] FLEXIO_D D6 PIO4_26 PIO4_26 PIO4_26 LCD_VSY NC FC11_SSE LN3 TRACEDA TA[2] FLEXIO_D C8 PIO4_27 PIO4_27 PIO4_27 LCD_D0 DBI_D0 TRACEDA TA[3] FLEXIO_D B10 PIO4_28 PIO4_28 PIO4_28 LCD_D1 DBI_D1 FLEXIO_D D8 PIO4_29 PIO4_29 PIO4_29 LCD_D2 DBI_D2 FLEXIO_D C9 PIO4_30 PIO4_30 PIO4_30 LCD_D3 DBI_D3 FC12_TXD _SCL_MIS O FLEXIO_D B9 PIO4_31 PIO4_31 PIO4_31 LCD_D4 DBI_D4 FC12_RX D_SDA_M OSI FLEXIO_D D9 PIO5_4 PIO5_4 PIO5_4 LCD_D9 DBI_D9 PDM_CLK C11 PIO5_8 PIO5_8 PIO5_8 LCD_D13 DBI_D13 PDM_DAT A01 C4 PIO6_27 PIO6_27 PIO6_27 MCLK J12 MIPI_DSI_ CLKN MIPI_DSI_ CLKN H11 MIPI_DSI_ CLKP MIPI_DSI_ CLKP H9 MIPI_DSI_ D0N MIPI_DSI_ D0N H8 MIPI_DSI_ D0P MIPI_DSI_ D0P H12 MIPI_DSI_ VDD11 Table continues on the next page... Pinouts i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 103 NXP Semiconductors

(141WLC SP) Pin Name DEFAULT Func 0 Func 1 Func 2 Func 3 Func 4 Func 5 Func 6 Func 7 Func 8 Func 15 G10 MIPI_DSI_ VDD18 K12 MIPI_DSI_ VDDA_CA P J11 MIPI_DSI_ VSS K9 PMIC_IRQ PMIC_IRQ K10 PMIC_MO DE0 PMIC_MO DE0 J9 PMIC_MO DE1 PMIC_MO DE1 L11 RESETN RESETN J10 RTCXIN RTCXIN K11 RTCXOUT RTCXOUT B11 USB1_DM USB1_DM B12 USB1_DP USB1_DP D10 USB1_VD D3V3 USB1_VD D3V3 K3 VREFN/ VSSA VREFN VREFP/ VDDA_AD C1V8/ VDDA_BIA S VREFP L9 XTALIN XTALIN K8 XTALOUT XTALOUT A3, B1, B6, E1, F2, VDDIO_0 Table continues on the next page... Pinouts 104 i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 NXP Semiconductors

(141WLC SP) Pin Name DEFAULT Func 0 Func 1 Func 2 Func 3 Func 4 Func 5 Func 6 Func 7 Func 8 Func 15 D11, G6, H5, L6, M5 VDDIO_1 NC VDDIO_2 E5 VDDIO_3 NC VDDIO_4 A10, B2, C1, C3, C10, C12, E6, F6, G7, G12, VDDCORE A11, L12, M11, F5, VDD1V8 L10 VDD_AO1 M10 VDD1V8_1 J8 VSSA A1, A2, A12, B3, F7, F8, G8, G11, H1, H7, G9, H10, M1, M9, M12 VSS Pinouts i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 105 NXP Semiconductors

5.5 Termination of unused pins

The following table shows how to terminate pins that are not used in the application. software to minimize the overall power consumption of the part. smaller packages as outputs driven LOW with their internal pull-up disabled. Table 50. Termination of unused pins PMIC_MODEn 0 Leave unconnected. RESETN I Tie high if not used in the system. RTCXOUT - Leave unconnected. PHY is disabled, the pins are floating. USB1_VBUS F Leave unconnected. USB1_VDD3V3 F Leave unconnected. VDD_AO1V8 F Tie to 1.8V power. VDDA_ADC1V8 F Tie to 1.8V power. Table continues on the next page...

Table 50. Termination of unused pins (continued) VDDA_BIAS F Tie to 1.8V power. XTALOUT - Leave unconnected.

1. Z = Input, pull-up, and pull-down disabled; PU = Pull-Up enabled; F = Floating, High-Z

5.6 Pin states in different power modes

Table 51. Pin states in different power modes disabled), except for a few pins where the pull-up and input are enabled.

1. Default and programmed pin states are retained in sleep and deep-sleep.

5.7 Obtaining package dimensions

Package dimensions are provided in package drawings.

6 Power supply for pins

VDDIO_3 supply pin can be powered between 1.71V to 3.6V. Table 52. Power supply for pins

7 Revision history

Table 53. Revision history

Revision history

110 i.MX RT500 Low-Power Crossover Processor, Rev. 0, 02/2021 NXP Semiconductors

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NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Applications — Applications that are described herein for any of these products are for illustrative purposes only. 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© 2021 NXP B.V. This addendum identifies changes to Rev. 0 of the i.MX RT500 Low-Power Crossover Processor Data Sheet. The changes described in this addendum have not been implemented in the specified pages.

1 Update the table “General operating conditions”

Add the following row to Table 5, “General operating conditions” Location: Section 1.1.6, Table 5, Page 14 Symbol Parameter Conditions Min. Typ. Max. Unit fotp_clk (fclk/OTP_CLK_DIV[DIV]) OTP clock frequency For OTP programmin g only - - 120 MHz Document Number: IMXRT500ECAD Rev. 0, 04/2021 Addendum to Rev. 0 of the i.MX RT500 Low-Power Crossover Processor Data Sheet

Addendum to i.MX RT500 Low-Power Crossover Processor Data Sheet, Rev. 0 NXP Semiconductors Update the section “Termination of unused pins”

2 Update the section “Termination of unused pins”

Replace the paragraph text within the section “Termination of unused pins” with the text below. The following table shows how to terminate pins on functions that are not used in the application. In many cases, unused pins should be connected externally or configured correctly by software to minimize the overall power consumption of the part. By default, unused pins with GPIO functions are tri-stated with the input buffer disabled and can remain floating. All power pins in the domains listed below must be connected to the recommended voltage.

3 Update the table “Termination of unused pins”

Replace Table 50 “Termination of unused pins” with the following table. Location: Section 5,5, Page 107 Location: Section 5.5, Table 50, Page 107 Function Pin Name Default state1 Recommended termination of unused pins GPIO All PIOn pins Z Leave unconnected. PMIC Control PMIC_I2C_SCL/SDA Z Leave unconnected. PMIC Control PMIC_IRQ_N I, Z 10 kΩ resistor to VDD_AO1V8. PMIC Control PMIC_MODEn O Leave unconnected. Control LDO_ENABLE I 10 k Ω resistor to ground. Control RESETN I 100 k Ω resistor to VDD_AO1V8.

Addendum to i.MX RT500 Low-Power Crossover Processor Data Sheet, Rev. 0 NXP Semiconductors Update the table “Termination of unused pins” Oscillator RTCXIN I Connect to ground. Oscillator RTCXOUT - Leave unconnected. Oscillator XTALIN I Connect to ground. Oscillator XTALOUT - Leave unconnected. USB1 USB1_DM/DP - Leave unconnected. USB1 USB1_VBUS - Leave unconnected. USB1 USB1_VDD3V3 - Leave unconnected. MIPI_DSI MIPI_DSI_VDD11 - 10 k Ω resistor to ground. MIPI_DSI MIPI_DSI_VDD18 - 10 k Ω resistor to ground. MIPI_DSI MIPI_DSI_VDDA_C AP - Leave unconnected. MIPI_DSI MIPI_DSI_VSS - Connect to ground. MIPI_DSI MIPI_DSI_D0N/D 0P - Leave unconnected. MIPI_DSI MIPI_DSI_D1N/D 1P - Leave unconnected. MIPI_DSI MIPI_DSI_CLK P - Leave unconnected. MIPI_DSI MIPI_DSI_CLK N - Leave unconnected. Analog VREFP - Connect to VDDA_ADC1V8. Analog VREFN - Connect to ground. Power VDDCORE - Connect to 1.0V power. Power VDD1V8 - Connect to 1.8V power. Power VDD_1V8_1 - Connect to 1.8V power during active. Can be powered off during deep sleep mode to reduce current consumption by approximately 22 uA. Power VDD_AO1V8 - Connect to 1.8V power. Power VDDIO_n Connect to 1.8V power. Power VDDA_ADC1V8 - Connect to 1.8V power. Power VDDA_BIAS - Connect to 1.8V power. Power VSSA - Connect to ground. Power VSS - Connect to ground.

1 Z = high impedance; I = Input; O = Output

Addendum to i.MX RT500 Low-Power Crossover Processor Data Sheet, Rev. 0 NXP Semiconductors Update the table “Power supply for pins”

4 Update the table “Power supply for pins”

Add the following rows to Table 52 “Power supply for pins”. Replace the following rows in Table 52 “Power supply for pins”, with the ones shown in the table. VDDIO_1: PIO1_2 to PIO1_7 (Fail Safe Pads) VDDIO_1: PIO1_10 (Fail Safe Pads) VDDIO_3: PIO5_0 to PIO5_4, PIO5_8 (Fail Safe Pads) Location: Section 6, Table 52, Page 109 Pin GPIO pins VDDIO_0 PIO6_27 (Fail Safe Pad) VDDIO_1 PIO5_4 and PIO5_8 (Fail Safe Pads) Pin GPIO pins VDDIO_1 PIO1_3 to PIO1_7 (Fail Safe Pads) PIO1_9 to PIO1_10 (Fail Safe Pads) VDDIO_3 PIO5_0 to PIO5_3 (Fail Safe Pads)

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