IMXRT1024IEC NXP | Alldatasheet
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Technical content
Data Sheet: Technical Data Document Number: IMXRT1024IEC Rev. 0, 11/2020 MIMXRT1024CAG4A
Package Information
144-Pin LQFP , 20 x 20 mm, 0.5 mm pitch
Ordering Information
NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. 1 i.MX RT1024 introduction The i.MX RT1024 is a processor of i.MX RT family featuring NXP’s advanced implementation of the Arm® Cortex®-M7 core, which operates at speeds up to 396 MHz to provide high CPU performance and real-time response. The i.MX RT1024 processor has 4 MB on-chip flash.
256 KB on-chip RAM can be flexibly configured as
TCM or general-purpose on-chip RAM. The i.MX RT1024 integrates advanced power management module with DCDC and LDO that reduces complexity of external power supply and simplifies power sequencing. The i.MX RT1024 also provides various memory interfaces, including SDRAM, RAW NAND FLASH, NOR FLASH, SD/eMMC, Quad SPI, and a wide range of connectivity interfaces including UART, SPI, I2C, USB, and CAN; for connecting peripherals including WLAN, Bluetooth™, and GPS. The i.MX RT1024 also has rich audio features, including SPDIF and I2S audio interface. Various analog IP integration, including ADC, analog comparator, temperature sensor, etc. i.MX RT1024 Crossover Processors Data Sheet for Industrial Products 3.2. Recommended connections for unused analog
i.MX RT1024 Crossover Processors Data Sheet for Industrial Products, Rev. 0, 11/2020
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i.MX RT1024 introduction The i.MX RT1024 is specifically useful for applications such as:
- Industrial
- Motor Control
- Home Appliance
- I o T
1.1 Features
The i.MX RT1024 processors are based on Arm Cortex-M7 Core Platform, which has the following features:
- Supports single Arm Cortex-M7 with: — 16 KB L1 Instruction Cache — 16 KB L1 Data Cache — Full featured Floating Point Unit (FPU ) with support of the VFPv5 architecture — Support the Armv7-M Thumb instruction set
- Integrated MPU, up to 16 individual protection regions
- Up to 256 KB I-TCM and D-TCM in total
- Frequency of 396 MHz
- Cortex M7 CoreSight™ components integration for debug
- Frequency of the core, as per Table 11, "Operating ranges," on page 19. The SoC-level memory system consists of the following additional components: — Boot ROM (96 KB) — On-chip Flash (4 MB) — On-chip RAM (256 KB) – Configurable RAM size up to 256 KB shared with CM7 TCM
- External memory interfaces: — 8/16-bit SDRAM, up to SDRAM-133 — 8/16-bit SLC NAND FLASH, with ECC handled in software —S D / e M M C — SPI NOR FLASH — Parallel NOR FLAS H with XIP support — Single/Dual channel Quad SPI FLASH with XIP support
- Timers and PWMs: — Two General Programmable Timers – 4-channel generic 32-bit resolution timer – Each support standard capture and compare operation — Four Periodical Interrupt Timers – Generic 32-bit resolution timer
i.MX RT1024 introduction i.MX RT1024 Crossover Processors Data Sheet for Industrial Products, Rev. 0, 11/2020 NXP Semiconductors 3 – Periodical interrupt generation —T w o Q u a d T i m e r s – 4-channel generic 16-bit resolution timer each – Each support standard capture and compare operation – Quadrature decoder integrated — Two FlexPWMs – Up to 8 individual PWM channels per each – 16-bit resolution PWM suitable for Motor Control applications — Two Quadrature Encoders/Decoders Each i.MX RT1024 processor enables the following interfaces to external devices (some of them are muxed and not available simultaneously):
- Audio: — S/PDIF input and output — Three synchronous audio in terface (SAI) modules supporting I2S, AC97, TDM, and codec/DSP interfaces — MQS interface for medium quality audio via GPIO pads
- Connectivity: — One USB 2.0 OTG controller with integrated PHY interface — Two Ultra Secure Digital Host Controller (uSDHC) interfaces – MMC 4.5 compliance support up to 100 MB/sec – SD/SDIO 3.0 compliance with 200 MHz SD R signaling to support up to 100 MB/sec – Support for SDXC (extended capacity) — One 10M/100M Ethernet cont roller with IEEE1588 supported — Eight universal async hronous receiver/transmitter (UARTs) modules — Four I2C modules — Four SPI modules — Two FlexCAN modules
- GPIO and Pin Multiplexing: — General-purpose input/output (GPIO) modules with interrupt capability — Input/output multiplexing cont roller (IOMUXC) to provide centralized pad control — 90 GPIOs for 144-pin LQFP package — One FlexIO The i.MX RT1024 processors integrate Analog module: — Two Analog-Digital-Converters (ADC), one of which supports differential inputs, up to 19 channels — Four Analog Comparators (ACMP) The i.MX RT1024 processors integrate advanced power management unit and controllers:
- Full PMIC integration, including on-chip DCDC and LDOs
i.MX RT1024 Crossover Processors Data Sheet for Industrial Products, Rev. 0, 11/2020
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i.MX RT1024 introduction
- Temperature sensor with programmable trip points
- GPC hardware power management controller The i.MX RT1024 processors support the following system debug:
- Arm CortexM7 CoreSight debug and trace architecture
- Trace Port Interface Unit (TPIU) to support off-chip real-time trace
- Support for 5-pin (JTAG) and SWD debug interfaces selected by eFuse Security functions are enabled and accelerated by the following hardware:
- High Assurance Boot (HAB)
- Data Co-Processor (DCP): — AES-128, ECB, and CBC mode — SHA-1 and SHA-256 — CRC-32
- Bus Encryption Engine (BEE) — AES-128, ECB, and CTR mode — On-the-fly QSPI Flash decryption
- True random number generation (TRNG)
- Secure Non-V olatile Storage (SNVS) — Secure real-time clock (RTC) — Zero Master Key (ZMK)
- Secure JTAG Controller (SJC) NOTE The actual feature set depends on the part numbers as described in Table 2. Functions such as display and camera interfaces, connectivity interfaces, and security features are not offered on all derivatives.
Table 1 lists the comparison between RT1020 and RT1024. Table 1. The comparison between RT1020 and RT1024
396 MHz, Industrial grade
500 MHz, Consumer grade
1588 EVENT 4 2
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1.2 Ordering information
Table 2 provides examples of orderable part numbers covered by this data sheet. contact an NXP representative for details. Table 2. Ordering information
Figure 1. Part number nomenclature—i.MX RT1024
400 MHz 4
500 MHz 5
600 MHz 6
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1.3 Package marking information
Figure 2 describes the package marking format about the i.MX RT1024 Crossover Processors. Figure 2. Package marking format
- First line: aaaaaaaaaaaaaaa
- Second line: mmmmm
- Third line: xxxyywwx Table 3 lists the identifier decoder.
Table 3. Identifier decoder
2 Architectural overview
The following subsections provide an architectural overview of the i.MX RT1024 processor system.
2.1 Block diagram
Figure 3 shows the functional modules in the i.MX RT1024 processor system1. Figure 3. i.MX RT1024 system block diagram
- Some modules shown in this block diagram are not offered on all derivatives. See Table 2 for details.
16 KB D-cache
16 KB I-cache
96 KB ROM 4 x Analog Comparator
256 KB SRAM/TCM
4 MB Flash
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3 Modules list
modules in alphabetical order. Table 4. i.MX RT1024 modules list voltage (rail-to-rail operation). values of the four selected inputs (A, B, C, D).
- System memory and peripheral registers
- All debug configuration registers The DAP also provides debugger access to JTAG scan chains. The DAP module is internal to the Cortex-M7 Core Platform. DCDC DCDC Converter Analog The DCDC module is used for generating power supply for core logic. Main features are:
- Adjustable high efficiency regulator
- Supports 3.3 V input voltage
- Supports nominal run and low power standby modes
- Supports at 0.9 ~ 1.3 V output in run mode
- Supports at 0.9 ~ 1.0 V output in standby mode
- Over current and over voltage detection
- The eDMA is a 32 channel DMA engine, which is capable of performing complex data transfers with minimal intervention from a host processor.
- The DMA_MUX is capable of multiplexing up to 128 DMA request sources to the 32 DMA channels of eDMA. ENC Quadrature Encoder/Decoder Timer Peripherals The enhanced quadrature encoder/decoder module provides interfacing capability to position/speed sensors. There are five input signals: PHASEA, PHASEB, INDEX, TRIGGER, and HOME. This module is used to decode shaft position, revolution count, and speed. ENET Ethernet Controller Connectivity Peripherals The Ethernet Media Access Controller (MAC) is designed to support 10/100 Mbit/s Ethernet/IEEE 802.3 networks. An external transceiver interface and transceiver function are required to complete the interface to the media. The module has dedicated hardware to support the IEEE 1588 standard. See the ENET chapter of the reference manual for details. EWM External Watchdog Monitor Timer Peripherals The EWM modules is designed to monitor external circuits, as well as the software flow. This provides a back-up mechanism to the internal WDOG that can reset the system. The EWM differs from the internal WDOG in that it does not reset the system. The EWM, if allowed to time-out, provides an independent trigger pin that when asserted resets or places an external circuit into a safe mode. FLEXCAN1 FLEXCAN2 Flexible Controller Area Network Connectivity Peripherals The CAN protocol was primarily, but not only, designed to be used as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the Electromagnetic interference (EMI) environment of a vehicle, cost-effectiveness and required bandwidth. The FlexCAN module is a full implementation of the CAN protocol specification, Version 2.0 B, which supports both standard and extended message frames. FlexIO1 Flexible Input/output Connectivity and Communications The FlexIO is capable of supporting a wide range of protocols including, but not limited to: UART, I2C, SPI, I2S, camera interface, display interface, PWM waveform generation, etc. The module can remain functional when the chip is in a low power mode provided the clock it is using remain active.
Table 4. i.MX RT1024 modules list (continued)
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Used for general purpose input/output to external ICs. Each GPIO module supports up to 32 bits of I/O. on an external clock or on an internal clock.
- Multiple-key detection
- Long key-press detection
- Standby key-press detection
- Supports a 2-point and 3-point contact key matrix LPI2C1 LPI2C2 LPI2C3 LPI2C4 Low Power Inter-integrated Circuit Connectivity and Communications The LPI2C is a low power Inter-Integrated Circuit (I2C) module that supports an efficient interface to an I2C bus as a master. The I2C provides a method of communication between a number of external devices. More detailed information, see Section 4.8.2, LPI2C module timing parameters.
SPI bus as a master and/or a slave.
- It can continue operating while the chip is in stop modes, if an appropriate clock is available
- Designed for low CPU overhead, with DMA off loading of FIFO register access LPUART1 LPUART2 LPUART3 LPUART4 LPUART5 LPUART6 LPUART7 LPUART8 UART Interface Connectivity Peripherals Each of the UART modules support the following serial data transmit/receive protocols and configurations:
- 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd or none)
- Programmable baud rates up to 5 Mbps. MQS Medium Quality Sound Multimedia Peripherals MQS is used to generate 2-channel medium quality PWM-like audio via two standard digital GPIO pins. QuadTimer1 QuadTimer2 QuadTimer Timer Peripherals The quad-timer provides four time channels with a variety of controls affecting both individual and multi-channel features.Specific features include up/down count, cascading of counters, programmable module, count once/repeated, counter preload, compare registers with preload, shared use of input signals, prescaler controls, independent capture/compare, fault input control, programmable input filters, and multi-channel synchronization. ROMCP ROM Controller with Patch Memories and Memory Controllers The ROMCP acts as an interface between the Arm advanced high-performance bus and the ROM. The on-chip ROM is only used by the Cortex-M7 core during boot up. Size of the ROM is 96 KB. RTC OSC Real Time Clock Oscillator Clock Sources and Control The RTC OSC provides the clock source for the Real-Time Clock module. The RTC OSC module, in conjunction with an external crystal, generates a 32.678 kHz reference clock for the RTC. RTWDOG Watch Dog Timer Peripherals The RTWDG module is a high reliability independent timer that is available for system to use. It provides a safety feature to ensure software is executing as planned and the CPU is not stuck in an infinite loop or executing unintended code. If the WDOG module is not serviced (refreshed) within a certain period, it resets the MCU. Windowed refresh mode is supported as well. SAI1 SAI2 SAI3 Synchronous Audio Interface Multimedia Peripherals The SAI module provides a synchronous audio interface (SAI) that supports full duplex serial interfaces with frame synchronization, such as I2S, AC97, TDM, and codec/DSP interfaces. SA-TRNG Standalone True Random Number Generator Security The SA-TRNG is hardware accelerator that generates a 512-bit entropy as needed by an entropy consuming module or by other post processing functions.
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optimized for both high-performance and low pin-count. temperature-dependent voltage to time conversion.
- One high-speed OTG 2.0 module with integrated HS USB PHY
- Support eight Transmit (TX) and eight Receive (Rx) endpoints, including endpoint 0
- Fully compliant with MMC command/response sets and Physical Layer as defined in the Multimedia including high-capacity (size > 2 GB) cards HC MMC.
- Fully compliant with SD command/response sets and Physical Layer as defined in the SD Memory Card Specifications, v3.0 including high-capacity SDXC cards up to 2 TB.
- Fully compliant with SDIO command/response sets and interrupt/read-wait mode as defined in the SDIO Card Specification, Part E1, v3.0 Two ports support:
- 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR104 mode (104 MB/s max)
- 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR and DDR modes (104 MB/s max)
- 4-bit transfer mode specifications for eMMC chips up to 100 MHz in HS200 mode (100 MB/s max) WDOG1 WDOG2 Watch Dog Timer Peripherals The Watch Dog Timer supports two comparison points during each counting period. Each of the comparison points is configurable to evoke an interrupt to the Arm core, and a second point evokes an external event on the WDOG line. XBAR Cross BAR Cross Trigger Each crossbar s witch is an array of muxes with shared inputs. Each mux output provides one output of the crossbar. The number of inputs and the number of muxes/outputs are user configurable and registers are provided to select which of the shared inputs are routed to each output.
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3.1 Special signal considerations
Table 5. Special signal considerations DCDC_PSWITCH PAD is in DCDC_IN domain and connected the ground to bypass DCDC. To enable DCDC function, assert to DCDC_IN with at least 1ms delay for DCDC_IN rising edge. crystal, (100 k ESR, 10 pF load) should be connected between RTC_XTALI and RTC_XTALO. startup margin. Typically RTC_XTALI and RTC_XTALO should bias to approximately 0.5 V. value depends on the typical load capacitance of crystal used and PCB design. capacitor. The logic level of this forcing clock cannot exceed NVCC_PLL level. requirements. See OSC24M chapter and relevant interface specifications chapters for details. GPANAIO This signal is reserved for NXP manufacturin g use only. This output must remain unconnected. followed. For example, do not use an external pull down on an input that has on-chip pull-up. to the same signal. JTAG_MOD must be externally connected to GND for normal operation.
3.2 Recommended connections for unused analog interfaces
Table 7 shows the recommended connections for unused analog interfaces. NC These signals are No Connect (NC) a nd should be disconnected by the user. POR_B This cold reset negative logic input resets all modules and logic in the IC. and external signals are considered active low). pressed for the defined time. TEST_MODE TEST_MODE is for NXP factory use. The user must tie this pin directly to GND. Table 6. JTAG controller interface summary Table 7. Recommended connections for unused analog interfaces Table 5. Special signal considerations (continued)
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Electrical characteristics
4 Electrical characteristics
This section provides the device and module-level electrical characteristics for the i.MX RT1024 processors.
4.1 Chip-level conditions
This section provides the device-level electrical characteristics for the IC. See Table 8 for a quick reference to the individual tables and sections.
4.1.1 Absolute maximum ratings
Stress beyond those listed under Table 9 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Table 9 shows the absolute maximum operating ratings. Table 8. i.MX RT1024 chip-Level conditions Table 9. Absolute maximum ratings
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4.1.2 Thermal resistance
Following sections provide the thermal resistance data. 4.1.2.1 20 x 20 mm package thermal resistance Table 10 displays the 20 x 20 mm LQFP package thermal characteristics.
4.1.3 Operating ranges
Table 11 provides the operating ranges of the i.MX RT1024 processors. For details on the chip's power structure, see the “Power Management Unit (PMU)” chapter of the i.MX RT1024 Reference Manual (IMXRT1024RM). IO supply for GPIO in SDIO1 bank (3.3 V mode) NVCC_SD0 3 3.6 V IO supply for GPIO in SDIO1 bank (1.8 V mode) 1.65 1.95 V IO supply for GPIO bank (3.3 V mode) NVCC_GPIO 3 3.6 V ESD Damage Immunity: Human Body Model (HBM) Charge Device Model (CDM) Vesd 1000 500 V Input/Output Voltage range V in/Vout -0.5 OVDD + 0.3 1 V Storage Temperature range T STORAGE -40 150 o C 1 OVDD is the I/O supply voltage. Table 10. 20 x 20 mm package thermal characteristics meant to predict the performance of a package in an application-specific environment. 2 Thermal test board meets JEDEC specification for this package (JESD51-7). Table 11. Operating ranges Table 9. Absolute maximum ratings (continued)
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Run Mode VDD_SOC_IN M7 core at 396 MHz 1.15 — 1.26 V — —VDD_SOC_IN M7 core at 132 MHz 1.15 — 1.26 M7 core at 24 MHz 0.925 — 1.26 IDLE Mode VDD_SOC_IN M7 core operation at 396 MHz or below 1.15 — 1.26 V — SUSPEND (DSM) Mode VDD_SOC_IN — 0.925 — 1.26 V Refer to Table 14 Low power mode current and power consumption SNVS Mode VDD_SOC_IN — 0 1.26 V — Power for DCDC DCDC_IN — 3.0 3.3 3.6 — VDD_HIGH internal regulator VDD_HIGH_IN 2 — 3.0 — 3.6 V Must match the range of voltages that the rechargeable backup battery supports. Backup battery supply range VDD_SNVS_IN3 — 2.40 — 3.6 V Can be combined with VDDHIGH_IN, if the system does not require keeping real time and other data on OFF state. USB supply voltages USB_OTG1_VBUS — 4.40 — 5.5 V — GPIO supplies NVCC_GPIO — 3.0 3.3 3.6 V All digital I/O supplies (NVCC_xxxx) must be powered (unless otherwise specified in this data sheet) under normal conditions whether the associated I/O pins are in use or not. NVCC_SD0 1.65 1.8, 3.3 3.6 V A/D converter VDDA_ADC_3P3 — 3.0 3.3 3.6 V VDDA_ADC_3P3 must be powered even if the ADC is not used. VDDA_ADC_3P3 cannot be powered when the other SoC supplies (except VDD_SNVS_IN) are off. Temperature Operating Ranges Junction temperature Tj Standard Commercial -40 — 105 oC See the application note, i.MX RT1024 Product Lifetime Usage Estimates for information on product lifetime (power-on years) for this processor. 1 Applying the maximum voltage results in maximum power consumption and heat generation. NXP recommends a voltage set point = (Vmin + the supply tolerance). This result in an optimized power/speed ratio. 2 Applying the maximum voltage results in shorten lifetime. 3.6 V usage limited to < 1% of the use profile. Reset of profile limited to below 3.49 V. Table 11. Operating ranges (continued)
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4.1.4 External clock sources
Each i.MX RT1024 processor has two external input system clocks: a low frequency (RTC_XTALI) and a high frequency (XTALI). The RTC_XTALI is used for low-frequency functions. It supplies the clock for wake-up circuit, power-down real time clock operation, and slow system and watch-dog counters. The clock input can be connected to either external oscillator or a crystal using internal oscillator amplifier. Additionally, there is an internal ring oscillator, which can be used instead of the RTC_XTALI if accuracy is not important. The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other peripherals. The system clock input can be connected to either external oscillator or a crystal using internal oscillator amplifier. Table 12 shows the interface frequency requirements. The typical values shown in Table 12 are required for use with NXP SDK to ensure precise time keeping and USB operation. For RTC_XTALI operation, two clock sources are available.
- On-chip 40 kHz ring oscillat or—this clock source has th e following characteristics: — Approximately 25 µA more Idd than crystal oscillator — Approximately ±50% tolerance — No external component required — Starts up quicker than 32 kHz crystal oscillator
- External crystal os cillator with on-chip support circuit: — At power up, ring oscillator is utilized. After crystal oscillator is stable, the clock circuit switches over to the crystal oscillator automatically. — Higher accuracy th an ring oscillator — If no external crystal is present, then the ring oscillator is utilized The decision of choosing a clock source should be taken based on real-time clock use and precision time-out. 3 In setting VDD_SNVS_IN voltage with regards to Charging Currents and RTC, refer to the i.MX RT1024 Hardware Development Guide (IMXRT1024HDG).
Table 12. External input clock frequency 1 External oscillator or a crystal with internal oscillator amplifier. Development Guide for i.MX RT1024 Crossover Processors (IMXRT1024HDG). 3 Recommended nominal frequency 32.768 kHz. 4 External oscillator or a fundamental frequency crystal with internal oscillator amplifier.
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4.1.5 Maximum supply currents
The data shown in Table 13 represent a use case designed specifically to show the maximum current consumption possible. All cores are running at the defined maximum frequency and are limited to L1 cache accesses only to ensure no pipeline stalls. Although a valid condition, it would have a very limited practical use case, if at all, and be limited to an extremely low duty cycle unless the intention was to specifically show the worst case power consumption. See the i.MX RT1024 Power Consumption Measurement Application Note for more details on typical power consumption under various use case definitions.
4.1.6 Low power mode supply currents
Table 14 shows the current core consumption (not including I/O) of i.MX RT1024 processors in selected low power modes. Table 13. Maximum supply currents A typical, 750 A max, for each ADC.
100 Ohm max loading for touch panel,
In this equation, Imax is in Amps, C in Farads, V in Volts, and F in Hertz. Table 14. Low power mode current and power consumption
- LDO_2P5 set to 2.5 V, LDO_1P1 set to 1.1 V
- CPU in WFI, CPU clock gated
- 24 MHz XTAL is ON
- System PLL is active, other PLLs are power down
- Peripheral clock gated, but remain powered DCDC_IN (3.3 V) 4 mA VDD_HIGH_IN (3.3 V) 5.2 VDD_SNVS_IN (3.3 V) 0.036 Total 30.479 mW
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4.1.7 USB PHY current consumption
4.1.7.1 Power down mode
In power down mode, everything is powered down, including the USB VBUS valid detectors in typical condition. Table 15 shows the USB interface current consumption in power down mode. NOTE The currents on the VDD_HIGH_CAP and VDD_USB_CAP were identified to be the voltage divider circuits in the USB-specific level shifters.
4.2 System power and clocks
This section provide the information about the system power and clocks. LOW POWER IDLE • LDO_SOC is in the Bypass mode, LDO_ARM is in the PG mode
- LDO_2P5 and LDO_1P1 are set to Weak mode
- CPU in Power Gate mode
- All PLLs are power down
- 24 MHz XTAL is off, 24 MHz RCOSC used as clock source
- Peripheral are powered off DCDC_IN (3.3 V) 2 mA VDD_HIGH_IN (3.3 V) 0.4 VDD_SNVS_IN (3.3 V) 0.05 Total 8.085 mW SUSPEND (DSM)
- LDO_SOC is in the Bypass mode, LDO_ARM is in the PG mode
- LDO_2P5 and LDO_1P1 are shut off
- CPU in Power Gate mode
- All PLLs are power down
- 24 MHz XTAL is off, 24 MHz RCOSC is off
- All clocks are shut off, except 32 kHz RTC
- Peripheral are powered off DCDC_IN (3.3 V) 0.3 mA VDD_HIGH_IN (3.3 V) 0.09 VDD_SNVS_IN (3.3 V) 0.03 Total 1.386 mW SNVS (RTC) • All SOC digital logic, analog module are shut off
- 32 kHz RTC is alive DCDC_IN (0 V) 0 mA VDD_HIGH_IN (0 V) 0 VDD_SNVS_IN (3.3 V) 0.020 Total 0.066 mW 1 The typical values shown here are for information only and are not guaranteed. These values are average values measured on a typical process wafer at 25oC.
Table 15. USB PHY current consumption in power down mode Table 14. Low power mode current and power consumption (continued)
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4.2.1 Power supplies requirements and restrictions
The system design must comply with power-up sequence, power-down sequence, and steady state guidelines as described in this section to guarantee the reliable operation of the device. Any deviation from these sequences may result in the following situations:
- Excessive current during power-up phase
- Prevention of the device from booting
- Irreversible damage to the pr ocessor (worst-case scenario)
4.2.1.1 Power-up sequence
The below restrictions must be followed:
- VDD_SNVS_IN supply must be turned on befo re any other power supply or be connected (shorted) with VDD_HIGH_IN supply.
- If a coin cell is used to power VDD_SNVS_IN, then ensure that it is connected before any other supply is switched on.
- When internal DCDC is enabled, external delay circuit is required to delay the “DCDC_PSWITCH” signal 1 ms after DCDC_IN is stable.
- POR_B should be held low dur ing the entire power up sequence. NOTE The POR_B input (if used) must be immediately asserted at power-up and remain asserted until after the last power rail reaches its working voltage. In the absence of an external reset feeding the POR_B input, the internal POR module takes control. See the i.MX RT1024 Reference Manual (IMXRT1024RM) for further details and to ensure that all necessary requirements are being met. NOTE Need to ensure that there is no back voltage (leakage) from any supply on the board towards the 3.3 V supply (for example, from the external components that use both the 1.8 V and 3.3 V supplies). NOTE USB_OTG1_VBUS and VDDA_ADC_3P3 are not part of the power supply sequence and may be powered at any time.
4.2.1.2 Power-down sequence
The following restrictions must be followed:
- VDD_SNVS_IN supply must be turn ed off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply.
- If a coin cell is used to power VDD_SNVS_IN, then ensure that it is removed after any other supply is switched off.
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4.2.1.3 Power supplies usage
All I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx) is OFF. This can cause internal latch-up and malfunctions due to reverse current flows. For information about I/O power supply of each pin, see “Power Rail” columns in pin list tables of Section 7, Package information and contact assignments.”
4.2.2 Integrated LDO volt age regulator parameters
Various internal supplies can be powered ON from internal LDO voltage regulators. All the supply pins named *_CAP must be connected to external capacitors. The onboard LDOs are intended for internal use only and should not be used to power any external circuitry. See the i.MX RT1024 Reference Manual (IMXRT1024RM) for details on the power tree scheme. NOTE The *_CAP signals should not be powered externally. These signals are intended for internal LDO operation only.
4.2.2.1 Digital regulators (LDO_SNVS)
There are one digital LDO regulator (“Digital”, because of the logic loads that they drive, not because of their construction). The advantages of the regulator is to reduce the input supply variation because of its input supply ripple rejection and its on-die trimming. This translates into more stable voltage for the on-chip logics. The regulator has two basic modes:
- Power Gate. The regulation FET is switched full y off limiting the current draw from the supply. The analog part of the regulator is powered down here limiting the power consumption.
- Analog regulation mode. The regulation FET is c ontrolled such that the output voltage of the regulator equals the programmed target voltage. The target voltage is fully programmable in 25 mV steps. For additional information, see the i.MX RT1024 Reference Manual (IMXRT1024RM).
4.2.2.2 Regulators for analog modules
4.2.2.2.1 LDO_1P1
The LDO_1P1 regulator implements a programmable linear-regulator function from VDD_HIGH_IN (see Table 11 for minimum and maximum input requirements). Typical Programming Operating Range is 1.0 V to 1.2 V with the nominal default setting as 1.1 V . The LDO_1P1 supplies the USB Phy, and PLLs. A programmable brown-out detector is included in the regulator that can be used by the system to determine when the load capability of the regulator is being exceeded to take the necessary steps. Current-limiting can be enabled to allow for in-rush current requirements during start-up, if needed. Active-pull-down can also be enabled for systems requiring this feature.
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For information on external capacitor requirements for this regulator, see the Hardware Development Guide for i.MX RT1024 Crossover Processors (IMXRT1024HDG). For additional information, see the i.MX RT1024 Reference Manual (IMXRT1024RM).
4.2.2.2.2 LDO_2P5
The LDO_2P5 module implements a programmable linear-regulator function from VDD_HIGH_IN (see Table 11 for minimum and maximum input requirements). Typical Programming Operating Range is 2.25 V to 2.75 V with the nominal default setting as 2.5 V . LDO_2P5 supplies the USB PHY , E-fuse module, and PLLs. A programmable brown-out detector is included in the regulator that can be used by the system to determine when the load capability of the regulator is being exceeded, to take the necessary steps. Current-limiting can be enabled to allow for in-rush current requirements during start-up, if needed. Active-pull-down can also be enabled for systems requiring this feature. An alternate self-biased low-precision weak-regulator is included that can be enabled for applications needing to keep the output voltage alive during low-power modes where the main regulator driver and its associated global bandgap reference module are disabled. The output of the weak-regulator is not programmable and is a function of the input supply as well as the load current. Typically, with a 3 V input supply the weak-regulator output is 2.525 V and its output impedance is approximately 40 . For information on external capacitor requirements for this regulator, see the Hardware Development Guide for i.MX RT1024 Crossover Processors (IMXRT1024HDG). For additional information, see the i.MX RT1024 Reference Manual (IMXRT1024RM).
4.2.2.2.3 LDO_USB
The LDO_USB module implements a programmable linear-regulator function from the USB VUSB voltages (4.4 V–5.5 V) to produce a nominal 3.0 V output voltage. A programmable brown-out detector is included in the regulator that can be used by the system to determine when the load capability of the regulator is being exceeded, to take the necessary steps. This regulator has a built in power-mux that allows the user to select to run the regulator from either USB VBUS supply, when both are present. If only one of the USB VBUS voltages is present, then, the regulator automatically selects this supply. Current limit is also included to help the system meet in-rush current targets. For information on external capacitor requirements for this regulator, see the Hardware Development Guide for i.MX RT1024 Crossover Processors (IMXRT1024HDG). For additional information, see the i.MX RT1024 Reference Manual (IMXRT1024RM).
4.2.2.2.4 DCDC
DCDC can be configured to operate on power-save mode when the load current is less than 50 mA. During the power-save mode, the converter operates with reduced switching frequency in PFM mode and with a minimum quiescent current to maintain high efficiency. DCDC can detect the peak current in the P-channel switch. When the peak current exceeds the threshold, DCDC will give an alert signal, and the threshold can be configured. By this way, DCDC can roughly detect the current loading.
i.MX RT1024 Crossover Processors Data Sheet for Industrial Products, Rev. 0, 11/2020 NXP Semiconductors 27 DCDC also includes the following protection functions:
- Over current protection. In run mode, DCDC shuts down when detecting abnormal large current in the P-type power switch. In power save mode, DCDC stop charging inductor when detecting large current in the P-type power switch. The threshold is also different in run mode and in power save mode: the former is 1 A–2A, and the latter is 200 mA–250 mA.
- Over voltage protection. DCDC shuts down when detecting the output voltage is too high.
- Low voltage detection. DCDC shuts down when detecting the input voltage is too low. For additional information, see the i.MX RT1024 Reference Manual (IMXRT1024RM).
4.2.3 PLL’s electrical characteristics
This section provides PLL electrical characteristics.
4.2.3.1 Audio/Video PLL’s electrical parameters
4.2.3.2 System PLL
4.2.3.3 Ethernet PLL
Table 16. Audio/video PLL’s electrical parameters Table 17. System PLL’s electrical parameters Table 18. Ethernet PLL’s electrical parameters
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4.2.3.4 USB PLL
4.2.4 On-chip oscillators
4.2.4.1 OSC24M
This block implements an amplifier that when combined with a suitable quartz crystal and external load capacitors implement an oscillator. The oscillator is powered from NVCC_PLL. The system crystal oscillator consists of a Pierce-type structure running off the digital supply. A straight forward biased-inverter implementation is used.
4.2.4.2 OSC32K
This block implements an amplifier that when combined with a suitable quartz crystal and external load capacitors implement a low power oscillator. It also implements a power mux such that it can be powered from either a ~3 V backup battery (VDD_SNVS_IN) or VDD_HIGH_IN such as the oscillator consumes power from VDD_HIGH_IN when that supply is available and transitions to the backup battery when VDD_HIGH_IN is lost. In addition, if the clock monitor determines that the OSC32K is not present, then the source of the 32 K will automatically switch to a crude internal ring oscillator. The frequency range of this block is approximately 10–45 kHz. It highly depends on the process, voltage, and temperature. The OSC32k runs from VDD_SNVS_CAP supply, which comes from the VDD_HIGH_IN/VDD_SNVS_IN. The target battery is a ~3 V coin cell. Proper choice of coin cell type is necessary for chosen VDD_HIGH_IN range. Appropriate series resistor (Rs) must be used when connecting the coin cell. Rs depends on the charge current limit that depends on the chosen coin cell. For example, for Panasonic ML621:
- Average Discharge V oltage is 2.5 V
- Maximum Charge Current is 0.6 mA
Table 19. USB PLL’s electrical parameters
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4.3 I/O parameters
This section provide parameters on I/O interfaces.
4.3.1 I/O DC parameters
This section includes the DC parameters of the following I/O types:
- XTALI and RTC_XTALI (Clock Inputs) DC Parameters
- General Purpose I/O (GPIO) NOTE The term ‘NVCC_XXXX’ in this section refers to the associated supply rail of an input or output.
Table 20. OSC32K main characteristics Fosc — 32.768 KHz — This frequency is nominal and determined mainly by the crystal selected. consumption will depend on what the digital portion of the RTC consumes. ring oscillator is not running. up and maintain oscillations. increases current oscillating through the crystal. value will decrease the oscillating margin.
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Figure 4. Circuit for parameters Voh and Vol for I/O cells
4.3.1.1 XTALI and RTC_XTALI (clock inputs) DC parameters
Table 21 shows the DC parameters for the clock inputs.
4.3.1.2 Single voltage general pur pose I/O (GPIO) DC parameters
operating ranges in Table 11, unless otherwise noted. Table 21. XTALI and RTC_XTALI DC parameters1 1 The DC parameters are for external clock input only. Table 22. Single voltage GPIO DC parameters
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4.3.2 I/O AC parameters
This section includes the AC parameters of the following I/O types:
- General Purpose I/O (GPIO) Figure 5 shows load circuit for output, and Figure 6 show the output transition time waveform.
Figure 5. Load circuit for output level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s. 3 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled. Table 22. Single voltage GPIO DC parameters (continued)
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Figure 6. Output transition time waveform
4.3.2.1 General purpose I/O AC parameters
Table 23. General purpose I/O AC parameters 1.8 V mode 1 Hysteresis mode is recommended for inputs with transition times greater than 25 ns. Table 24. General purpose I/O AC parameters 3.3 V mode 1 Hysteresis mode is recommended for inputs with transition times greater than 25 ns.
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4.3.3 Output buffer impedance parameters
This section defines the I/O impedance parameters of the i.MX RT1024 processors for the following I/O types:
- Single V oltage General Purpose I/O (GPIO) NOTE GPIO I/O output driver impedance is measured with “long” transmission line of impedance Ztl attached to I/O pad and incident wave launched into transmission line. Rpu/Rpd and Ztl form a voltage divider that defines specific voltage of incident wave relative to NVCC_XXXX. Output driver impedance is calculated from this voltage divider (see Figure 7).
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Figure 7. Impedance matching load for measurement
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4.3.3.1 Single voltage GP IO output buffer impedance
Table 25 shows the GPIO output buffer impedance (NVCC_XXXX 1.8 V). Table 26 shows the GPIO output buffer impedance (NVCC_XXXX 3.3 V).
4.4 System modules
This section contains the timing and electrical parameters for the modules in the i.MX RT1024 processor.
4.4.1 Reset timings parameters
Figure 8 shows the reset timing and Table 27 lists the timing parameters. Figure 8. Reset timing diagram Table 25. GPIO output buffer average impedance (NVCC_XXXX 1.8 V) Table 26. GPIO Output buffer average impedance (NVCC_XXXX 3.3 V) Table 27. Reset timing parameters
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4.4.2 WDOG reset timing parameters
Figure 9 shows the WDOG reset timing and Table 28 lists the timing parameters. Figure 9. WDOGn_B timing diagram manual for detailed information.
4.4.3 SCAN JTAG Controller (SJC) timing parameters
Figure 10 depicts the SJC test clock input timing. Figure 11 depicts the SJC boundary scan timing. Figure 12 depicts the SJC test access port. Signal parameters are listed in Table 29. Figure 10. Test clock input timing diagram Table 28. WDOGn_B timing parameters
i.MX RT1024 Crossover Processors Data Sheet for Industrial Products, Rev. 0, 11/2020 NXP Semiconductors 37 Figure 11. Boundary scan (JTAG) timing diagram
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Figure 12. Test access port timing diagram Figure 13. JTAG_TRST_B timing diagram Table 29. JTAG timing
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4.4.4 Debug trace ti ming specifications
Figure 14. ARM_TRACE_CLK specifications
1 TDC = target frequency of SJC
2 VM = mid-point voltage
Table 30. Debug trace operating behaviors Table 29. JTAG timing (continued)
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Figure 15. Trace data specifications
4.5 External memory interface
The following sections provide information about external memory interfaces.
4.5.1 SEMC specifications
The following sections provide information on SEMC interface. Measurements are with a load of 15 pf and an input slew rate of 1 V/ns.
4.5.1.1 SEMC output timing
There are ASYNC and SYNC mode for SEMC output timing.
4.5.1.1.1 SEMC output timing in ASYNC mode
Table 31 shows SEMC output timing in ASYNC mode. Table 31. SEMC output timing in ASYNC mode detail about SEMC_*CR0.AH register field.
i.MX RT1024 Crossover Processors Data Sheet for Industrial Products, Rev. 0, 11/2020 NXP Semiconductors 41 Figure 16 shows the output timing in ASYNC mode. Figure 16. SEMC output timing in ASYNC mode
4.5.1.1.2 SEMC output timing in SYNC mode
Table 32 shows SEMC output timing in SYNC mode. SEMC_*CR0.AS register field. detail about SEMC_*CR0.WEH register field. about SEMC_*CR0.WEL register field. Table 32. SEMC output timing in SYNC mode
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Figure 17 shows the output timing in SYNC mode. Figure 17. SEMC output timing in SYNC mode
4.5.1.2 SEMC input timing
There are ASYNC and SYNC mode for SEMC input timing.
4.5.1.2.1 SEMC input timing in ASYNC mode
Table 33 shows SEMC output timing in ASYNC mode. Figure 18 shows the input timing in ASYNC mode. Table 33. SEMC output timing in ASYNC mode
i.MX RT1024 Crossover Processors Data Sheet for Industrial Products, Rev. 0, 11/2020 NXP Semiconductors 43 Figure 18. SEMC input timing in ASYNC mode
4.5.1.2.2 SEMC input timing in SYNC mode
Table 34 and Table 35 show SEMC input timing in SYNC mode. Figure 19 shows the input timing in SYNC mode. Table 34. SEMC input timing in SYNC mode (SEMC_MCR.DQSMD = 0x0) Table 35. SEMC input timing in SYNC mode (SEMC_MCR.DQSMD = 0x1)
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Figure 19. SEMC input timing in SYNC mode
4.5.2 FlexSPI parameters 1
Measurements are with a load 15 pf and input slew rate of 1 V/ns.
4.5.2.1 FlexSPI input/read timing
- Dummy read strobe generated by FlexSPI controller and looped back internally (FlexSPIn_MCR0[RXCLKSRC] = 0x0)
- Dummy read strobe generated by FlexSPI controller and looped back through the DQS pad (FlexSPIn_MCR0[RXCLKSRC] = 0x1)
- Read strobe provided by memory device and input from DQS pad (FlexSPIn_MCR0[RXCLKSRC] = 0x3) The following sections describe input signal timing for each of these four internal sample clock sources.
4.5.2.1.1 SDR mode with FlexSPI n_MCR0[RXCLKSRC] = 0x0, 0x1
- The FlexSPI is used for internal flash by default for RT1024.
Table 36. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X0 Table 37. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X1
i.MX RT1024 Crossover Processors Data Sheet for Industrial Products, Rev. 0, 11/2020 NXP Semiconductors 45 Figure 20. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X0, 0X1 falling edge, and FlexSPI controller sampling read data on the falling edge.
4.5.2.1.2 SDR mode with FlexSPI n_MCR0[RXCLKSRC] = 0x3
- A1–Memory generates both read data and read strobe on SCK rising edge (or falling edge)
- A2–Memory generates read data on SCK falling edge and generates read strobe on SCK rising edgeSCK rising edge
Figure 21. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X3 (Case A1) Table 38. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A1)
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Timing shown is based on the memory generating read data and read strobe on the SCK rising edge. The FlexSPI controller samples read data on the DQS falling edge. Figure 22. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X3 (Case A2) samples read data on a half cycle delayed DQS falling edge.
4.5.2.1.3 DDR mode with FlexSPI n_MCR0[RXCLKSRC] = 0x0, 0x1
Table 39. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A2) Table 40. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0
i.MX RT1024 Crossover Processors Data Sheet for Industrial Products, Rev. 0, 11/2020 NXP Semiconductors 47 Figure 23. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1
4.5.2.1.4 DDR mode with FlexSPI n_MCR0[RXCLKSRC] = 0x3
- B1–Memory generates both read data and read strobe on SCK edge
- B2–Memory generates read data on SCK edge and generates read strobe on SCK2 edge
Table 41. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1 Table 42. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case B1)
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Figure 24. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case B1) Figure 25. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case B2)
4.5.2.2 FlexSPI output/write timing
4.5.2.2.1 SDR mode
Table 43. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case B2) Table 44. FlexSPI output timing in SDR mode
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4.5.2.2.2 DDR mode
RT1024 Reference Manual (IMXRT1024RM) for more details. Table 45. FlexSPI output timing in DDR mode Table 44. FlexSPI output timing in SDR mode (continued)
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Figure 27. FlexSPI output timing in DDR mode
4.6 Audio
This section provide information about SAI/I2S and SPDIF.
4.6.1 SAI/I2S switching specifications
This section provides the AC timings for the SAI in master (clocks driven) and slave (clocks input) modes. (SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below. Table 46. Master mode SAI timing
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4.6.2 SPDIF timing parameters
The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal. Table 48 and Figure 30 and Figure 31 show SPDIF timing parameters for the Sony/Philips Digital Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode. Figure 30. SPDIF_SR_CLK timing diagram Table 48. SPDIF timing parameters
- Skew
- Transition rising
- Transition falling 1.5 24.2 31.3 ns SPDIF_OUT1 output (Load = 30pf)
- Skew
- Transition rising
- Transition falling 1.5 13.6 18.0 ns Modulating Rx clock (SPDIF_SR_CLK) period srckp 40.0 — ns SPDIF_SR_CLK high period srckph 16.0 — ns SPDIF_SR_CLK low period srckpl 16.0 — ns Modulating Tx clock (SPDIF_ST_CLK) period stclkp 40.0 — ns SPDIF_ST_CLK high period stclkph 16.0 — ns SPDIF_ST_CLK low period stclkpl 16.0 — ns SPDIF_SR_CLK (Output) VM VM srckp srckphsrckpl
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4.7 Analog
The following sections provide information about analog interfaces.
4.7.1 DCDC
Table 49 introduces the DCDC electrical specification.
4.7.2 A/D converter
This section introduces information about A/D converter. Table 49. DCDC electrical specifications
- Support discontinuous mode Configurable by register Inductor 4.7 H— Capacitor 33 F— Over voltage protection 1.6 V Detect VDDSOC, when the voltage is higher than 1.6 V, shutdown DCDC. Over Current protection 1 A Detect the peak current
- Run mode: when the current is larger than 1 A, shutdown DCDC.
- Stop mode: when the current is larger than 250 mA, stop charging the inductor. Low battery detection 2.6 V Detect the bat tery, when battery is lower than 2.6 V, shutdown DCDC. SPDIF_ST_CLK (Input) VM VM stclkp stclkphstclkpl
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4.7.2.1 12-bit ADC electrical characteristics The section provide information about 12-bit ADC electrical characteristics. 4.7.2.1.1 12-bit ADC operating conditions Table 50. 12-bit ADC operating conditions only and are not tested in production.
2 DC potential differences
i.MX RT1024 Crossover Processors Data Sheet for Industrial Products, Rev. 0, 11/2020 NXP Semiconductors 55 Figure 32. 12-bit ADC input impedance equivalency diagram Table 51. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSAD)
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Sample Cycles ADLSMP=0, ADSTS=00 Csamp — 2 — cycles — ADLSMP=0, ADSTS=01 ADLSMP=0, ADSTS=10 ADLSMP=0, ADSTS=11 ADLSMP=1, ADSTS=00 ADLSMP=1, ADSTS=01 ADLSMP=1, ADSTS=10 ADLSMP=1, ADSTS=11 Conversion Cycles ADLSMP=0 ADSTS=00 Cconv — 28 — cycles — ADLSMP=0 ADSTS=01 ADLSMP=0 ADSTS=10 ADLSMP=0 ADSTS=11 ADLSMP=1 ADSTS=00 ADLSMP=1 ADSTS=01 ADLSMP=1 ADSTS=10 ADLSMP=1, ADSTS=11 Table 51. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSAD) (continued)
i.MX RT1024 Crossover Processors Data Sheet for Industrial Products, Rev. 0, 11/2020 NXP Semiconductors 57 Conversion Time ADLSMP=0 ADSTS=00 Tconv — 0.7 — µs Fadc = 40 MHz ADLSMP=0 ADSTS=01 0.75 ADLSMP=0 ADSTS=10 0.8 ADLSMP=0 ADSTS=11 0.85 ADLSMP=1 ADSTS=00 0.95 ADLSMP=1 ADSTS=01 1.05 ADLSMP=1 ADSTS=10 1.15 ADLSMP=1, ADSTS=11 1.25 Total Unadjusted Error 12 bit mode TUE — 3.4 — LSB
1 LSB =
(VREFH - VREFL)/2 N AVGE = 1, AVGS = 11 10 bit mode — 1.5 — 8 bit mode — 1.2 — Differential Non-Linearity 12 bit mode DNL — 0.76 — LSB AVGE = 1, AVGS = 11 10bit mode — 0.36 — 8 bit mode — 0.14 — Integral Non-Linearity 12 bit mode INL — 2.78 — LSB AVGE = 1, AVGS = 11 10bit mode — 0.61 — 8 bit mode — 0.14 — Zero-Scale Error 12 bit mode E ZS — -1.14 — LSB AVGE = 1, AVGS = 11 10bit mode — -0.25 — 8 bit mode — -0.19 — Full-Scale Error 12 bit mode E FS — -1.06 — LSB AVGE = 1, AVGS = 11 10bit mode — -0.03 — 8 bit mode — -0.02 — Effective Number of Bits 12 bit mode ENOB 10.1 10.7 — Bits AVGE = 1, AVGS = 11 Signal to Noise plus Distortion See ENOB SINAD SINAD = 6.02 x ENOB + 1.76 dB AVGE = 1, AVGS = 11
1 All accuracy numbers assume the ADC is calibrated with VREFH=VDDAD
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The ADC electrical spec is met with the calibration enabled configuration. Figure 33. Minimum Sample Time Vs Ras (Cas = 2pF) Figure 34. Minimum Sample Time Vs Ras (Cas = 5 pF) only and are not tested in production.
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4.7.3 ACMP
Table 52 lists the ACMP electrical specifications. Table 52. Comparator and 6-bit DAC electrical specifications
- CR0[HYSTCTR] = 00 — 1 2
- CR0[HYSTCTR] = 01 — 21 54
- CR0[HYSTCTR] = 10 — 42 108
- CR0[HYSTCTR] = 11 — 64 184 V CMPOH Output high V DD - 0.5 — — V VCMPOI Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN = 1, PMODE = 1)2 —2 54 0n s tDLS Propagation delay, low-speed mode (EN = 1, PMODE = 0)2 —5 09 0n s tDInit Analog comparator initialization delay3 —1 . 5 — s IDAC6b 6-bit DAC current adder (enabled) — 5 — A
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4.8 Communication interfaces
The following sections provide the information about communication interfaces.
4.8.1 LPSPI timing parameters
The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic LPSPI timing modes. All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as well as input signal transitions of 3 ns and a 30 pF maximum load on all LPSPI pins. RDAC6b 6-bit DAC reference inputs — V DD —V INLDAC6b 6-bit DAC integral non-linearity -0.3 — 0.3 LSB 4 DNLDAC6b 6-bit DAC differential non-linearity -0.15 — 0.15 LSB 4 1 Typical hysteresis is measured with input voltage range limited to 0.7 to VDD - 0.7 V in high speed mode. 2 Signal swing is 100 mV. 3 Comparator initialization delay is defined as the time between software writes to the enable comparator module and the comparator output setting to a stable level. 4 1 LSB = Vreference / 64 Table 53. LPSPI Master mode timing guaranteed this limit is not exceeded. Table 52. Comparator and 6-bit DAC electrical specifications (continued)
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s Figure 38. LPSPI Slave mode timing (CPHA = 0) Table 54. LPSPI Slave mode timing guaranteed this limit is not exceeded.
3 Time to data active from high-impedance state
4 Hold time to high-impedance state
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4.8.2 LPI2C module timing parameters
This section describes the timing parameters of the LPI2C module. Table 55. LPI2C module timing parameters 1 Hs-mode is only supported in slave mode. 2 See General switching specifications.
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4.8.3 Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC) AC
This section describes the electrical information of the uSDHC, which includes SD/eMMC4.3 (Single 4.8.3.1 SD/eMMC4.3 (single data rate) AC timing Figure 40 depicts the timing of SD/eMMC4.3, and Table 56 lists the SD/eMMC4.3 timing characteristics. Figure 40. SD/eMMC4.3 timing Table 56. SD/eMMC4.3 interface timing specification
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4.8.3.3 SDR50/SDR104 AC timing
Figure 42 depicts the timing of SDR50/SDR104, and Table 58 lists the SDR50/SDR104 timing characteristics. Figure 42. SDR50/SDR104 timing Table 58. SDR50/SDR104 interface timing specification 1Data window in SDR104 mode is variable.
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4.8.3.4 HS200 mode timing
Figure 43 depicts the timing of HS200 mode, and Table 59 lists the HS200 timing characteristics. Figure 43. HS200 mode timing "Single voltage GPIO DC parameters," on page 30.
4.8.4 Ethernet controller (ENET) AC electrical specifications
at timing specs/constraints for the physical interface. Table 59. HS200 interface timing specification 1HS200 is for 8 bits while SDR104 is for 4 bits.
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4.8.4.1 ENET MII mode timing
This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal timings.
4.8.4.1.1 MII receive signal timing (ENET_RX_DATA3,2,1,0, ENET_RX_EN,
ENET_RX_ER, and ENET_RX_CLK) The receiver functions correctly up to an ENET_RX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the ENET_RX_CLK frequency. Figure 44 shows MII receive signal timings. Table 60 describes the timing parameters (M1–M4) shown in the figure. Figure 44. MII receive signal timing diagram 1 ENET_RX_EN, ENET_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode.
4.8.4.1.2 MII transmit si gnal timing (ENET_TX_DATA3,2,1,0, ENET_TX_EN,
The transmitter functions correctly up to an ENET_TX_CLK maximum frequency of 25 MHz + 1%. twice the ENET_TX_CLK frequency. Table 60. MII receive signal timing
i.MX RT1024 Crossover Processors Data Sheet for Industrial Products, Rev. 0, 11/2020 NXP Semiconductors 69 Figure 45 shows MII transmit signal timings. Table 61 describes the timing parameters (M5–M8) shown in the figure. Figure 45. MII transmit signal timing diagram 1 ENET_TX_EN, ENET_TX_CLK, and ENET0_TXD0 have the same timing in 10-Mbps 7-wire interface mode.
4.8.4.1.3 MII asynchronou s inputs signal timing (ENET_CRS and ENET_COL)
Figure 46. MII async inputs timing diagram 1 ENET_COL has the same timing in 10-Mbit 7-wire interface mode. Table 61. MII transmit signal timing Table 62. MII asynchronous inputs signal timing
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4.8.4.1.4 MII serial mana gement channel timing (ENET_MDIO and ENET_MDC)
The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3 MII specification. However the ENET can function correctly with a maximum MDC frequency of 15 MHz. Figure 47 shows MII asynchronous input timings. Table 63 describes the timing parameters (M10–M15) shown in the figure. Figure 47. MII serial management channel timing diagram
4.8.4.2 RMII mode timing
ENET_TX_EN, ENET_TX_DATA[1:0], ENET_RX_DATA[1:0] and ENET_RX_ER. Table 63. MII serial management channel timing M10 ENET_MDC falling edge to ENET_MDIO output invalid (min. M11 ENET_MDC falling edge to ENET_MDIO output valid (max.
i.MX RT1024 Crossover Processors Data Sheet for Industrial Products, Rev. 0, 11/2020 NXP Semiconductors 71 Figure 48 shows RMII mode timings. Table 64 describes the timing parameters (M16–M21) shown in the figure. Figure 48. RMII mode signal timing diagram
4.8.5 Flexible Controller Area N etwork (FLEXCAN) AC electrical
Please refer to Section 4.3.2.1, General purpose I/O AC parameters.
4.8.6 LPUART electrical specifications
Please refer to Section 4.3.2.1, General purpose I/O AC parameters. Table 64. RMII signal timing
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4.8.7 USB PHY parameters
This section describes the USB-OTG PHY parameters. The USB PHY meets the electrical compliance requirements defined in the Universal Serial Bus Revision 2.0 OTG with the following amendments.
- USB ENGINEERING CHANGE NOTICE — Title: 5V Short Circuit Wi thstand Requirement Change — Applies to: Universal Serial Bus Specification, Revision 2.0
- Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
- USB ENGINEERING CHANGE NOTICE — Title: Pull-up/Pull-down resistors — Applies to: Universal Serial Bus Specification, Revision 2.0
- USB ENGINEERING CHANGE NOTICE — Title: Suspend Current Limit Changes — Applies to: Universal Serial Bus Specification, Revision 2.0
- USB ENGINEERING CHANGE NOTICE — Title: USB 2.0 Phase Locked SOFs — Applies to: Universal Serial Bus Specification, Revision 2.0
- On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification — Revision 2.0 plus errata and ecn June 4, 2010
- Battery Charging Specificati on (available from USB-IF) — Revision 1.2, December 7, 2010 — Portable device only
4.9 Timers
This section provide information on timers.
4.9.1 Pulse Width Modula tor (PWM) characteristics
This section describes the electrical information of the PWM.
4.9.2 Quad timer timing
Table 66 listed the timing parameters. Table 65. PWM timing parameters
i.MX RT1024 Crossover Processors Data Sheet for Industrial Products, Rev. 0, 11/2020 NXP Semiconductors 73 Figure 49. Quad timer timing Table 66. Quad Timer Timing 1 T = clock cycle. For 60 MHz operation, T = 16.7 ns.
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5 Flash
This section introduces the on-chip flash electrical parameters. Table 67 shows the operating ranges of on-chip flash power supply by NVCC_GPIO. For details about the flash AC parameters, refer to the following link. Table 67. Operating ranges
6 Boot mode configuration
6.1 Boot mode configuration pins
sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse. Fuse Map document and the System Boot chapter in i.MX RT1024 Reference Manual (IMXRT1024RM).
6.2 Boot device interface allocation
which are configured during boot when appropriate. Table 68. Fuses and associated pins used for boot settings for BT_FUSE_SEL = ‘0’. Table 69. Boot trough NAND
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Table 70. Boot trough NOR
Table 71. Boot through FlexSPI Table 72. Boot through SD1
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Table 73. Boot through SD2 Table 74. Boot through SPI-1 Table 75. Boot through SPI-2 Table 76. Boot through SPI-3
Table 77. Boot through SPI-4 Table 78. Boot through SEMC Table 79. Boot through UART1 Table 80. Boot through UART2 Table 76. Boot through SPI-3 (continued)
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Package information and contact assignments
7 Package information and contact assignments
This section includes the contact assignment information and mechanical package drawing. 7.1 20 x 20 mm package information 7.1.1 20 x 20 mm, 0.5 mm pitch, ball matrix Figure 50 shows the top, bottom, and side views of the 20 x 20 mm LQFP package.
Figure 50. 20 x 20 mm LQFP, case x package top and side views
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Table 81 shows the device connection list for ground, sense, and reference contact signals. Table 82 shows an alpha-sorted list of functional contact assignments for the 20 x 20 mm package. Table 81. 20 x 20 mm supplies contact Assignment Table 82. 20 x 20 mm functional contact assignments
Table 82. 20 x 20 mm functional contact assignments (continued)
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Figure 51 shows the pin assignments of the 20 x 20 mm package. Figure 51. The pin assignments of the 20 x 20 mm package1
- For the differences about NC pins between RT1020 and RT1024, please see the i.MX RT1024 Migration Guide for details.
108 GPIO_AD_B0_03
116 GPIO_EMC_40
124 GPIO_EMC_32
132 GPIO_EMC_24
140 GPIO_EMC_18
Revision history
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8 Revision history
Table 83 provides a revision history for this data sheet. Table 83. i.MX RT1024 data sheet document revision history
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