82C89 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Pin Compatible with Bipolar 8289
  • Performance Compatible with:
  • Provides Multi-Master System Bus Control and Arbitration
  • Provides Simple Interface with 82C88/8288 Bus Controller
  • Synchronizes 80C86/8086, 80C88/8088 Processors with Multi-Master Bus
  • Bipolar Drive Capability
  • Four Operating Modes for Flexible System Configura- tion
  • Low Power Operation
  • Operating Temperature Ranges oC to +70oC

Description

The Intersil 82C89 Bus Arbiter is manufactured using a self- aligned silicon gate CMOS process (Scaled SAJI IV). This cir- cuit, along with the 82C88 bus controller, provides full bus arbi- tration and control for multi-processor systems. The 82C89 is typically used in medium to large 80C86 or 80C88 systems where access to the bus by several processors must be coordi- nated. The 82C89 also provides high output current and capac- itive drive to eliminate the need for additional bus buffering. Static CMOS circuit design insures low operating power. The advanced Intersil SAJI CMOS process results in perfor- mance equal to or greater than existing equivalent products at a significant power savings. Pinouts 82C89 (CERDIP) TOP VIEW 82C89 (PLCC, CLCC) TOP VIEW

Ordering Information

PKG. NO. CP82C89 20 Ld PDIP 0 oC to +70oC E20.3 IP82C89 -40 oC to +85oC E20.3 CS82C89 20 Ld PLCC 0 oC to +70oC N20.35 IS82C89 -40 oC to +85oC N20.35 CD82C89 20 Ld CERDIP 0oC to +70oC F20.3 ID82C89 -40 oC to +85oC F20.3 MD82C89/B -55 oC to +125oC F20.3 5962-8552801RA SMD# F20.3 MR82C89/B 20 Pad CLCC -55 oC to +125oC J20.A 5962-85528012A SMD# J20.A

1 VCC

File Number 2980.1CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999

SYMBOL NUMBER TYPE DESCRIPTION VCC 20 V CC : The +5V Power supply pin. A 0.1µF capacitor between pins 10 and 20 is recommended for decoupling. GND 10 GROUND. S0,S1,S2 1, 18-19 I STATUS INPUT PINS: The status input pins from an 80C86, 80C88 or 8089 processor. The 82C89 decodes these pins to initiate bus request and surrender actions. (See Table 1). CLK 17 I CLOCK: From the 82C84A or 82C85 clock chip and serves to establish when bus arbiter actions are initiated. LOCK 16 I LOCK: A processor generated signal which when activated (low) prevents the arbiter from surren- dering the multi-master system bus to any other bus arbiter, regardless of its priority. CRQLCK 15 I COMMON REQUEST LOCK: An active low signal which prevents the arbiter from surrendering the multi-master system bus to any other bus arbiter requesting the bus through theCBRQ input pin. RESB 4 I RESIDENT BUS: A strapping option to configure the arbiter to operate in systems having both a multi-master system bus and a Resident Bus. Strapped high, the multi-master system bus is re- quested or surrendered as a function of the SYSB/ RESB input pin. Strapped low, the SYSB/RESB input is ignored. ANYRQST 14 I ANY REQUEST: A strapping option which permits the multi-master system bus to be surrendered to a lower priority arbiter as if it were an arbiter of higher priority (i.e., when a lower priority arbiter requests the use of the multi-master system bus, the bus is surrendered as soon as it is possible). When ANYRQST is strapped low, the bus is surrendered according to Table A in Design Informa- tion. If ANYRQST is strapped high and CBRQ is activated, the bus is surrendered at the end of the present bus cycle. StrappingCBRQ low and ANYRQST high forces the 82C89 arbiter to sur- render the multi-master system bus after each transfer cycle. Note that when surrender occurs BREQ is driven false (high). CONTROL ARBITRATION MULTIBUS INTERFACE LOCAL BUS INTERFACE +5V GND CONTROL/ STRAPPING OPTIONS 80C86/ 80C88 STATUS COMMAND SIGNALS MULTIBUS TM SYSTEM SIGNALS MULTIBUS TM IS AN INTEL CORP. TRADEMARK BPRN SYSB/ RESB INIT BCLK BREQ BPRO BUSY CBRQ AEN CLK RESB ANYRQST LOCK S 1 IOB CRQLCK S 0 S 2 STATUS DECODER 82C89

IOB 2 I IO BUS: A strapping option which configures the 82C89 Arbiter to operate in systems having both an IO Bus (Peripheral Bus) and a multi-master system bus. The arbiter requests and surrenders the use of the multi-master system bus as a function of the status line, S2. The multi-master sys- tem bus is permitted to be surrendered while the processor is performing IO commands and is requested whenever the processor performs a memory command. Interrupt cycles are assumed as coming from the peripheral bus and are treated as an IO command. AEN 13 O ADDRESS ENABLE: The output of the 82C89 Arbiter to the processor’s address latches, to the 82C88 Bus Controller and 82C84A or 82C85 Clock Generator.AEN serves to instruct the Bus Controller and address latches when to three-state their output drivers. INIT 6 I INITIALIZE: An active low multi-master system bus input signal used to reset all the bus arbiters on the multi-master system bus. After initialization, no arbiters have the use of the multi-master system bus. SYSB/ RESB 3 I SYSTEM BUS/RESIDENT BUS: An input signal when the arbiter is configured in the System/Res- ident Mode (RESB is strapped high) which determines when the multi-master system bus is re- quested and multi-master system bus surrendering is permitted. The signal is intended to originate from a form of address-mapping circuitry, such as a decoder or PROM attached to the resident address bus. Signal transitions and glitches are permitted on this pin fromθ1 of T4 toθ1 of T2 of the processor cycle. During the period fromθ1 of T2 toθ1 of T4, only clean transitions are permit- ted on this pin (no glitches). If a glitch occurs, the arbiter may capture or miss it, and the multi-mas- ter system bus may be requested or surrendered, depending upon the state of the glitch. The arbiter requests the multi-master system bus in the System/Resident Mode when the state of the SYSB/ RESB pin is high and permits the bus to be surrendered when this pin is low. CBRQ 12 I/O COMMON BUS REQUEST: An input signal which instructs the arbiter if there are any other arbi- ters of lower priority requesting the use of the multi-master system bus. The CBRQ pins (open-drain output) of all the 82C89 Bus Arbiters which surrender to the multi- master system bus upon request are connected together. The Bus Arbiter running the current transfer cycle will not itself pull theCBRQ line low. Any other arbiter connected to theCDRQ line can request the multi-master system bus. The arbiter presently running the current transfer cycle drops itsBREQ signal and surrenders the bus whenever the proper surrender conditions exist. StrappingCBRQ low and ANYRQST high allows the multi-mas- ter system bus to be surrendered after each transfer cycle. See the pin definition of ANYRQST. BCLK 5 I BUS CLOCK: The multi-master system bus clock to which all multi-master system bus interface signals are synchronized. BREQ 7 O BUS REQUEST: An active low output signal in the Parallel Priority Resolving Scheme which the arbiter activates to request the use of the multi-master system bus. BPRN 9 I BUS PRIORITY IN: The active low signal returned to the arbiter to instruct it that it may acquire the multi-master system bus on the next falling edge ofBCLK. BPRN active indicates to the arbiter that it is the highest priority requesting arbiter presently on the bus. The loss ofBPRN instructs the ar- biter that it has lost priority to a higher priority arbiter. BPR O 8 O BUS PRIORITY OUT: An active low output signal used in the serial priority resolving scheme where BPRO is daisy-chained toBPRN of the next lower priority arbiter. BUSY 11 I/O BUSY: An active low open-drain multi-master system bus interface signal used to instruct all the arbiters on the bus when the multi-master system bus is available. When the multi-master system bus is available the highest requesting arbiter (determined by BPRN) seizes the bus and pulls BUSY low to keep other arbiters off of the bus. When the arbiter is done with the bus, it releases theBUSY signal, permitting it to go high and thereby allowing another arbiter to acquire the multi- master system bus. Pin Description (Continued) PIN SYMBOL NUMBER TYPE DESCRIPTION 82C89

cessor to indicate “READY” from the accessed slave device. lower priority master completes its present transfer cycle. surrendered or requested under different sets of conditions. niques, and rotating priority techniques. ority resolving scheme employed to settle. FIGURE 1. PARALLEL PRIORITY RESOLVING TECHNIQUE FIGURE 2. HIGHER PRIORITY ARBITER OBTAINING THE BUS

  1. Higher priority bus arbiter requests the Multi-Master system bus.
  2. Lower priority bus arbiter releases
  3. Higher priority bus arbiter then acquires the bus and pullsBUSY

3 TO 8

  • •
  • • BREQ BPRN BREQ BPRN BREQ BPRN BREQ BPRN B USY CBRQ BCLK BREQ BPRN B USY 3 4 82C89

the next lower priority. See Figure 3. chance to use the multi-master system bus, over time. bus while not requiring too much logic to implement. treated as I/O devices and are addressed by I/O commands. ability and being dedicated to that one master. Resident Bus, and an I/O Bus. sible I/O Processor system configuration. ter as to whether or not the system bus is to be accessed. response to its status lines inputs, is shown in Table 1. FIGURE 3. SERIAL PRIORITY RESOLVING arbiters may be daisychained.

FIGURE 4. TYPICAL MEDIUM COMPLEXITY CPU SYSTEM

FIGURE 5. TYPICAL MEDIUM COMPLEXITY IOB SYSTEM

FIGURE 6. 82C89 BUS ARBITER SHOWN IN SYSTEM - RESIDENT BUS CONFIGURATION access to two multi-master buses.

TABLE 1. SUMMARY OF 82C89 MODES, REQUESTING AND RELINQUISHING THE MULTI-MASTER SYSTEM BUS

  1. X = Multi-Master System Bus is allowed to be Surrendered.
  2. † = Multi-Master System Bus is Requested.
  • LOCK prevents surrender of Bus to any other arbiter,CRQLCK prevents surrender of Bus to any lower priority arbiter.

** Except for HALT and Passive or IDLE Status.

  1. + is read as “OR” and • as “AND”
  2. TI = Processor Idle Status
  3. HLT = Processor Halt StatusS2,S1,S0 = 011

Absolute Maximum Ratings Thermal Information Operating Conditions Operating Temperature Range oC to +70oC Thermal Resistance θJA (oC/W) θJC (oC/W) oC to +150oC Maximum Junction Temperature (PLCC - Lead Tips Only) Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TA = 0oC to +70oC (C82C89); TA = -40oC to +85oC (I82C89); TA = -55oC to +125oC (M82C89) SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS VIH Logical One Input Voltage 2.0 2.2 V V C82C89, I82C89 M82C89, Note 1 VIL Logical Zero Input Voltage - 0.8 V Note 1 VIHC CLK Logical One Input Voltage 0.7 VCC - V VILC CLK Logical Zero Input Voltage - 0.2 VCC V VOL Output Low Voltage BUSY, CBRQ AEN BPR O, BREQ 0.45 0.45 0.45 V V V I OL = 20mA IOL = 16mA IOL = 8mA VOH1 Output High Voltage BUSY, CBRQ Open-Drain VOH2 Output High Voltage All Other Outputs 3.0 VCC -0.4 V IOH = -2.5mA IOH = -100µA II Input Leakage Current -1.0 1.0 µAV IN = GND or VCC , DIP Pins 1-6, 9, 14-19 IO I/O Leakage -10.0 10.0 µAV O = GND or VCC , DIP Pins 11-12 ICCSB Standby Power Supply - 10 µAV CC = 5.5V, VIN = VCC or GND, Outputs Open ICCOP Operating Power Supply Current - 1 mA/MHz V CC = 5.5V, Outputs Open, Note 2 NOTES: 1. Does not apply toIOB, RESB, or ANYRQST. These are strap options and should be held to VCC or GND. 2. Maximum current defined by CLK or BCLK, whichever has the highest operating frequency Capacitance TA = +25oC SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS CIN Input Capacitance 10 pF FREQ = 1MHz, all measurements are referenced to device GND COUT Output Capacitance 10 pF CIO I/O Capacitance 15 pF 82C89

TA = 0oC to +70oC (C82C89); TA = -40oC to +85oC (I82C89); TA = -55oC to +125oC (M82C89) SYMBOL PARAMETER MIN MAX UNIT TEST CONDITIONS (1) TCLCL CLK Cycle Period 125 - ns Note 3 (2) TCLCH CLK Low Time 55 - ns Note 3 (3) TCHCL CLK High Time 35 - ns Note 3 (4) TSVCH Status Active Setup 65 TCLCL-10 ns Note 3 (5) TSHCL Status Inactive Setup 50 TCLCL-10 ns Note 3 (6) THVCH Status Inactive Hold 10 - ns Note 3 (7) THVCL Status Active Hold 10 - ns Note 3 (8) TBYSBL BUSY ↓↑ Setup toBCLK ↓ 20 - ns Note 3 (9) TCBSBL CBRQ ↓↑ Setup toBCLK ↓ 20 - ns Note 3 (10) TBLBL BCLK Cycle Time 100 - ns Note 3 (11) TBHCL BCLK High Time 30 0.65 (TBLBL) ns Note 3 (12) TCLLL1 LOCK Inactive Hold 10 - ns Note 3 (13) TCLLL2 LOCK Active Setup 40 - ns Note 3 (14) TPNBL BPRN ↓↑ to BCLK Setup Time 20 - ns Note 3 (15) TCLSR1 SYSB/ RESB Setup 0 - ns Note 3 (16) TCLSR2 SYSB/ RESB Hold 30 - ns Note 3 (17) TIVIH Initialization Pulse Width 675 - ns Note 3 (18) TBLBRL BCLK toBREQ Delay↓↑ - 35 ns Note 3 (19) TBLPOH BCLK toBPR O ↓↑ - 35 ns Note 1 and 3 (20) TPNPO BPRN ↓↑ toBPR O ↓↑ Delay - 22 ns Note 1 and 3 (21) TBLBYL BCLK toBUSY Low - 60 ns Note 3 (22) TBLBYH BCLK toBUSY Float - 35 ns Note 2 and 3 (23) TCLAEH CLK to AEN High - 65 ns Note 3 (24) TBLAEL BCLK toAEN Low - 40 ns Note 3 (25) TBLCBL BCLK toCBRQ Low - 60 ns Note 3 (26) TBLCBH BCLK toCBRQ Float - 40 ns Note 2 and 3 (27) TOLOH Output Rise Time - 20 ns From 0.8V to 2.0V, Note 4 (28) TOHOL Output Fall Time - 12 ns From 2.0V to 0.8V, Note 4 (29) TILIH Input Rise Time - 20 ns From 0.8V to 2.0V (30) TIHIL Input Fall Time - 20 ns From 2.0V to 0.8V NOTES: BCLK generates the firstBPR O wherein subsequentBPR O changes lower in the chain are generated through BPRON. 2. Measured at 0.5V above GND. 3. All AC parameters tested as per AC test load circuits. Input rise and fall times are driven at 1ns/V. 4. Except BUSY and CBRQ 82C89

B USY, CBRQ LOAD CIRCUIT AEN LOAD CIRCUIT BPR O, BREQ LOAD CIRCUIT NOTE: Includes Stray and Jig Capacitance AC Testing Input, Output Waveform AC Testing: Inputs are driven at VIH +0.4V for a logic “1” and VIL ing measurements are made at 1.5V for both a logic “1” and “0”. TEST POINT 100pF 102Ω OUTPUT FROM DEVICE UNDER TEST 2.5V (NOTE) TEST POINT 2.9V 100pF OUTPUT FROM DEVICE UNDER TEST 157.2Ω (NOTE) TEST POINT 2.9V 100pF OUTPUT FROM DEVICE UNDER TEST 249.6Ω (NOTE) 1.5V 1.5V VIL -0.4V INPUT VIH +0.4V VOL OUTPUT VOH 82C89

NOTES: 1. LOCK active can occur during any state, as long as the relationships shown above with respect to the CLK are maintained.LOCK inactive has no critical time and can be asynchronous.CRQLCK has no critical timing and is considered an asynchronous input signal. 2. Glitching of SYSB/RESB is permitted during this time. Afterθ2 of T1, and beforeθ1 of T4, SYSB/RESB should be stable to maintain sys- tem efficiency. 3. AEN leading edge is related toBCLK, trailing edge to CLK. The trailing edge ofAEN occurs after bus priority is lost. ADDITIONAL NOTES: The signals related to CLK are typical processor signals, and do not relate to the depicted sequence of events of the signals referenced to BCLK. The signals shown related to theBCLK represent a hypothetical sequence of events for illustration. Assume 3 bus arbiters of priori- ties 1, 2 and 3 configured in serial priority resolving scheme (as shown in Figure 3). Assume arbiter 1 has the bus and is holding BUSY low. Arbiter #2 detects its processor wants the bus and pulls lowBREQ #2. IfBPRN #2 is high (as shown), arbiter #2 will pull lowCBRQ line. CBRQ signals to the higher priority arbiter #1 that a lower priority arbiter wants the bus. [A higher priority arbiter would be grantedBPRN when it makes the bus request rather than having to wait for another arbiter to release the bus throughCBRQ]. *Arbiter #1 will relinquish the multi-master system bus when it enters a state not requiring it (see Table 1), by lowering itsBPR O #1 (tied toBPRN #2) and releasingBUSY . Arbiter #2 now sees that is has priority fromBPRN #2 being low and releasesCBRQ. As soon asBUSY signifies the bus is available (high), arbiter #2 pullsBUSY low on next falling edge ofBCLK. Note that if arbiter #2 didn’t want the bus at the time it received priority, it would pass priority to the next lower priority arbiter by lowering itsBPR O #2 [TPNPO]. Note that even a higher priority arbiter which is acquiring the bus throughBPRN will momentarily dropCBRQ until it has acquired the bus. STATE CLK S2,S1,S0 LOCK (SEE NOTE 1) SYSB/ RESB AEN (SEE NOTE 3) PROCESSOR CLK RELATED BUS CLK RELATED BCLK BREQ #2 BPRN #2 (BPR O #1) BPR O #2 (BPRN #3) B USY CBRQ (20) TPnPO (14) TPNBL (22) TBLBYH (11) TBHCL (24) TBLAEL (13) TCLL2 (12) TCLLL1 (6) THVCH (4) TSVCH (7) THVCL (2) TCLCH (16) TCLSR2 (SEE NOTE 2) (23) TCLAEH (10) TBLBL TBYSBL (8) TCBSBL (9)(26) TBLCBH TCLSR1 (15) (SEE NOTE 2) TSHCL (5) (25) TBLCBL (18) TBLBRL T4 T1 T2 T3 T4 TCLCL(1) (3) TCHCL TBLPOH (19) TBLBYL (21) 82C89

NOTES: 1. VCC = 5.5V± 0.5V, GND = 0V 2. VIH = 4.5V± 10%, VIL = -0.2V to +0.4V 3. Components Values: R2 = 47kΩ , 1/4W, 5% C1 = 0.01µF minimum F0 = 100kHz± 10% F1 = F0/2 F2 = F1/2. . . . F14 = F13/2 1 20F7 F13 F14 F12 VCC VCC/2 VCC VCC/2 F11 F10 91 0 1 1 1 2 13 321 2 0 1 9 F10 F11 F12 F0 R2 VCC VCC/ 2 VCC F13 F7 R 2 F14 R 2 R 2 R 2 R 2 R 1 R 1R 1 VCC/ 2 82C89

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 Die Characteristics DIE DIMENSIONS: 92.9 x 95.7 x 19± 1mils METALLIZATION: Type: Si - Al Thickness: 11k Å ± 2kÅ GLASSIVATION: Type: Nitrox Thickness: 10k Å ± 2kÅ WORST CASE CURRENT DENSITY: 1.8 x 105 A/cm2 Metallization Mask Layout 82C89 CLK LOCK CRQLCK ANYRQST SYSB/ RESB IOB VCC ANYRQST BPR O BPRN GND B USY CBRQ AEN RESB BCLK INIT BREQ 82C89