82C55A INTERSIL | Alldatasheet

Document overview

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  • PDF pages: 26

Technical content

Features

  • Pin Compatible with NMOS 8255A
  • 24 Programmable I/O Pins
  • Fully TTL Compatible
  • High Speed, No “Wait State” Operation with 5MHz and 8MHz 80C86 and 80C88
  • Direct Bit Set/Reset Capability
  • Enhanced Control Word Read Capability
  • L7 Process
  • 2.5mA Drive Capability on All I/O Ports

Description

The Intersil 82C55A is a high performance CMOS version of the industry standard 8255A and is manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). It is a general purpose programmable I/O device which may be used with many different microprocessors. There are 24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation. The high performance and industry standard configuration of the 82C55A make it compatible with the 80C86, 80C88 and other microprocessors. Static CMOS circuit design insures low operating power. TTL compatibility over the full military temperature range and bus hold circuitry eliminate the need for pull-up resistors. The Intersil advanced SAJI process results in performance equal to or greater than existing functionally equivalent products at a fraction of the power.

Ordering Information

PKG. NO.5MHz 8MHz CP82C55A-5 CP82C55A 40 Ld PDIP 0oC to 70oC E40.6 IP82C55A-5 IP82C55A -40 oC to 85oC E40.6 CS82C55A-5 CS82C55A 44 Ld PLCC 0oC to 70oC N44.65 IS82C55A-5 IS82C55A -40 oC to 85oC N44.65 CD82C55A-5 CD82C55A 40 Ld CERDIP 0oC to 70oC F40.6 ID82C55A-5 ID82C55A -40 oC to 85oC F40.6 MD82C55A-5/B MD82C55A/B -55 oC to 125oC F40.6 8406601QA 8406602QA SMD# F40.6 MR82C55A-5/B MR82C55A/B 44 Pad CLCC -55oC to 125oC J44.A 8406601XA 8406602XA SMD# J44.A Pinouts 82C55A (DIP) TOP VIEW 82C55A (CLCC) TOP VIEW 82C55A (PLCC) TOP VIEW PA3 PA2 PA1 PA0 RD CS GND PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB1 PB2 PA4 PA5 PA6 PA7 WR RESE T V CC PB7 PB6 PB5 PB4 PB3 4065 321 4 4 4 3 4 2 4 14 18 19 20 21 22 23 24 25 26 27 28 GND NC PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 V CC NC NC RESET NC CS RD PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 WR CS GND PC7 PC6 PC5 PC4 PC0 PC1 PC3 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 NC NC RESET V CC RD PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 WR NC PC2 NC 44 4342 41 40 2827 123456 262524232221201918 File Number 2969.2CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999

VCC 26 V CC : The +5V power supply pin. A 0.1µF capacitor between pins 26 and 7 is recommended for decoupling. GND 7 GROUND D0-D7 27-34 I/O DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the system data bus. RESET 35 I RESET: A high on this input clears the control register and all ports (A, B, C) are set to the input mode with the “Bus Hold” circuitry turned on. CS 6 I CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the Data Bus for CPU communications. RD 5 I READ: Read is an active low input control signal used by the CPU to read status information or data via the data bus. WR 36 I WRITE: Write is an active low input control signal used by the CPU to load control words and data into the 82C55A. A0-A1 8, 9 I ADDRESS: These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word register. A0 and A1 are normally connected to the least significant bits of the Address Bus A0, A1. PA0-PA7 1-4, 37-40 I/O PORT A: 8-bit input and output port. Both bus hold high and bus hold low circuitry are present on this port. PB0-PB7 18-25 I/O PORT B: 8-bit input and output port. Bus hold high circuitry is present on this port. PC0-PC7 10-17 I/O PORT C: 8-bit input and output port. Bus hold circuitry is present on this port. GROUP A PORT A (8) GROUP A PORT C UPPER (4) GROUP B PORT C LOWER (4) GROUP B PORT B (8) GROUP B CONTROL GROUP A CONTROL DATA BUS BUFFER READ WRITE CONTROL LOGIC RD WR RESET CS D7-D0 POWER SUPPLIES +5V GND BI-DIRECTIONAL DATA BUS I/O PA7-PA0 I/O PC7-PC4 I/O PC3-PC0 I/O PB7-PB0 8-BIT INTERNAL DATA BUS 82C55A

tion are also transferred through the data bus buffer. external transfers of both Data and Control or Status words. and in turn, issues commands to both of the Control Groups. communcation between the 82C55A and the CPU. essence, it allows the CPU to “read from” the 82C55A. write data or control words into the 82C55A. bits of the address bus (A0 and A1). tializes the functional configuration of the 82C55A. proper commands to its associated ports. control word format for both Read and Write operations. “1”, as this implies control word mode information.

00010 Port A→ Data Bus

01010 Port B→ Data Bus

10010 Port C→ Data Bus

11010 Control Word→ Data Bus

00100 Data Bus→ Port A

01100 Data Bus→ Port B

10100 Data Bus→ Port C

11100 Data Bus→ Control

FIGURE 1. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER,

are present on Port A. See Figure 2A. data input buffer. See Figure 2B. port is initialized to all zeros when the control word is written. FIGURE 2. BUS-HOLD CONFIGURATION FIGURE 3. BASIC MODE DEFINITIONS AND BUS INTERFACE

8 I/O

4 I/O

FIGURE 4. MODE DEFINITION FORMAT

port almost any peripheral device with no external logic. requirements in control-based applications. operation just as if they were output ports. bit set/reset function of port C. other device in the interrupt structure. ten to or read from a specific port.

  • Two 8-bit ports and two 4-bit ports
  • Any Port can be input or output
  • Outputs are latched
  • Input are not latched
  • 16 different Input/Output configurations possible

FIGURE 5. BIT SET/RESET FORMAT

Mode 0 (Basic Input) Mode 0 (Basic Output) Mode 0 Configurations CONTROL WORD #0 CONTROL WORD #2 CONTROL WORD #1 CONTROL WORD #3 tRA tHR tRR tIR tAR tRD tDF RD INPUT CS, A1, A0 D7-D0 tAW tWA tWB tWW tWDtDW WR D7-D0 CS, A1, A0 OUTPUT PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C 82C55A

CONTROL WORD #4 CONTROL WORD #8 CONTROL WORD #5 CONTROL WORD #9 CONTROL WORD #6 CONTROL WORD #10 CONTROL WORD #7 CONTROL WORD #11 Mode 0 Configurations (Continued) PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C 82C55A

to generate or accept these “hand shaking” signals.

  • Two Groups (Group A and Group B)
  • Each group contains one 8-bit port and one 4-bit control/data port
  • The 8-bit data port can be either input or output. Both inputs and outputs are latched.
  • The 4-bit port is used for control and status of the 8-bit port. Input Control Signal Definition (Figures 6 and 7) STB (Strobe Input) A “low” on this input loads data into the input latch. IBF (Input Buffer Full F/F) A “high” on this output indicates that the data has been loaded into the input latch: in essence, and acknowledg- ment. IBF is set by STB input being low and is reset by the rising edge of theRD input. CONTROL WORD #12 CONTROL WORD #14 CONTROL WORD #13 CONTROL WORD #15 Mode 0 Configurations (Continued) PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C

FIGURE 6. MODE 1 INPUT

FIGURE 14. MODE 2 COMBINATIONS

FIGURE 23. BASIC FLOPPY DISC INTERFACE FIGURE 24. MACHINE TOOL CONTROLLER INTERFACE

Absolute Maximum Ratings TA = 25oC Thermal Information Operating Conditions Operating Temperature Range oC to 70oC Thermal Resistance (Typical, Note 1) θJA θJC Maximum Junction Temperature (PLCC Lead Tips Only) Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical SpecificationsVCC = 5.0V±10%; TA = 0oC to +70oC (C82C55A); TA = -40oC to +85oC (I82C55A); TA = -55oC to +125oC (M82C55A) SYMBOL PARAMETER LIMITS UNITS TEST CONDITIONSMIN MAX VIH Logical One Input Voltage 2.0 2.2 - V I82C55A, C82C55A, M82C55A VIL Logical Zero Input Voltage - 0.8 V VOH Logical One Output Voltage 3.0 VCC -0.4 -V I OH = -2.5mA, IOH = -100µA VOL Logical Zero Output Voltage - 0.4 V I OL +2.5mA II Input Leakage Current -1.0 +1.0 µAV IN = VCC or GND, DIP Pins: 5, 6, 8, 9, 35, 36 IO I/O Pin Leakage Current -10 +10 µA VO = V CC or GND DIP Pins: 27 - 34 IBHH Bus Hold High Current -50 -400 µA VO = 3.0V. Ports A, B, C IBHL Bus Hold Low Current 50 400 µA VO = 1.0V. Port A ONLY IDAR Darlington Drive Current -2.5 Note 2, 4 mA Ports A, B, C. Test Condition 3 ICCSB Standby Power Supply Current - 10 µAV CC = 5.5V, VIN = VCC or GND. Output Open ICCOP Operating Power Supply Current - 1 mA/MHz T A = +25oC, VCC = 5.0V, Typical (See Note 3) NOTES: 2. No internal current limiting exists on Port Outputs. A resistor must be added externally to limit the current. 3. ICCOP = 1mA/MHz of Peripheral Read/Write cycle time. (Example: 1.0µs I/O Read/Write cycle time = 1mA). 4. Tested as V OH at -2.5mA. Capacitance TA = 25oC SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS CIN Input Capacitance 10 pF FREQ = 1MHz, All Measurements are referenced to device GND CI/O I/O Capacitance 20 pF 82C55A

TA = -40oC to +85oC (I82C55A) (I82C55A-5); TA = 0oC to +70oC (C82C55A) (C82C55A-5) SYMBOL PARAMETER 82C55A-5 82C55A UNITS TEST CONDITIONSMIN MAX MIN MAX READ TIMING (1) tAR Address Stable Before R D 0-0- n s (2) tRA Address Stable After R D 0-0- n s (3) tRR RD Pulse Width 250 - 150 - ns (4) tRD Data Valid From RD - 200 - 120 ns 1 (5) tDF Data Float After RD 10 75 10 75 ns 2 (6) tRV Time Between RDs and/orWRs 300 - 300 - ns WRITE TIMING (7) tAW Address Stable Before W R 0-0- n s (8) tWA Address Stable After WR 20 - 20 - ns (9) tWW WR Pulse Width 100 - 100 - ns (10) tDW Data Valid to WR High 100 - 100 - ns (11) tWD Data Valid After WR High 30 - 30 - ns OTHER TIMING (12) tWB WR = 1 to Output - 350 - 350 ns 1 (13) tIR Peripheral Data Before R D 0-0- n s (14) tHR Peripheral Data After R D 0-0- n s (15) tAK ACK Pulse Width 200 - 200 - ns (16) tST STB Pulse Width 100 - 100 - ns (17) tPS Peripheral Data Before STB High 20 - 20 - ns (18) tPH Peripheral Data After STB High 50 - 50 - ns (19) tAD ACK = 0 to Output - 175 - 175 ns 1 (20) tKD ACK = 1 to Output Float 20 250 20 250 ns 2 (21) tWOB WR = 1 to OBF = 0 - 150 - 150 ns 1 (22) tAOB ACK = 0 to OBF = 1 - 150 - 150 ns 1 (23) tSIB STB = 0 to IBF = 1 - 150 - 150 ns 1 (24) tRIB RD = 1 to IBF = 0 - 150 - 150 ns 1 (25) tRIT RD = 0 to INTR = 0 - 200 - 200 ns 1 (26) tSIT STB = 1 to INTR = 1 - 150 - 150 ns 1 (27) tAIT ACK = 1 to INTR = 1 - 150 - 150 ns 1 (28) tWIT WR = 0 to INTR = 0 - 200 - 200 ns 1 (29) tRES Reset Pulse Width 500 - 500 - ns 1, (Note) NOTE: Period of initial Reset pulse after power-on must be at least 50µsec. Subsequent Reset pulses may be 500ns minimum. 82C55A

FIGURE 30. WRITE TIMING FIGURE 31. READ TIMING FALL times are driven at 1ns/V.

  1. All resistors are 47kΩ± 5%

DIE DIMENSIONS: 95 x 100 x 19 ±1mils METALLIZATION: Type: Silicon - Aluminum Thickness: 11k Å ±1kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ ±1kÅ WORST CASE CURRENT DENSITY: 0.78 x 105 A/cm2 Metallization Mask Layout 82C55A RD PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 WR CS GND PC7 PC6 PC5 PC4 PC0 PC1 PC2 PD3 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 VCC RESET 82C55A

Dual-In-Line Plastic Packages (PDIP) NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be per- pendicular to datum . 7. eB and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. eA -C- CL E eA C eB eC -B- INDEX 1 2 3 N/2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E40.6(JEDEC MS-011-AC ISSUE B)

40 LEAD DUAL-IN-LINE PLASTIC PACKAGE

A - 0.250 - 6.35 4 A1 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.030 0.070 0.77 1.77 8 C 0.008 0.015 0.204 0.381 - D 1.980 2.095 50.3 53.2 5 D1 0.005 - 0.13 - 5 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 e 0.100 BSC 2.54 BSC - e A 0.600 BSC 15.24 BSC 6 eB - 0.700 - 17.78 7 L 0.115 0.200 2.93 5.08 4 N4 0 4 0 9 Rev. 0 12/93

Plastic Leaded Chip Carrier Packages (PLCC) NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allow- able mold protrusion is 0.010 inch (0.25mm) per side. Dimen- sions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. -C- A SEATING PLANE 0.020 (0.51) MIN VIEW “A” D2/E2 0.025 (0.64) 0.045 (1.14)R 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP EE1 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER CL D 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) MIN 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN VIEW “A” TYP. 0.004 (0.10)C -C- D2/E2 CL N44.65 (JEDEC MS-018AC ISSUE A)

44 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE

A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 0.685 0.695 17.40 17.65 - D1 0.650 0.656 16.51 16.66 3 D2 0.291 0.319 7.40 8.10 4, 5 E 0.685 0.695 17.40 17.65 - E1 0.650 0.656 16.51 16.66 3 E2 0.291 0.319 7.40 8.10 4, 5 N4 4 4 4 6 Rev. 2 11/97

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli- able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 82C55A Ceramic Dual-In-Line Frit Seal Packages (CERDIP) NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N,N/2, and N/2+1) may beconfigured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. bbb C A - BS c Q L A SEATING BASE D PLANE PLANE -D--A- -C- -B- α D E b A e M (c) (b) SECTION A-A BASE LEAD FINISH METAL eA/2 A M S S ccc C A - BM DS S aaa C A - BM DS S eA F40.6MIL-STD-1835 GDIP1-T40 (D-5, CONFIGURATION A)

40 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

A - 0.225 - 5.72 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 2.096 - 53.24 5 E 0.510 0.620 12.95 15.75 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC - eA/2 0.300 BSC 7.62 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.070 0.38 1.78 6 S1 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 N4 0 4 0 8 Rev. 0 4/94

Ceramic Leadless Chip Carrier Packages (CLCC) D j x 45o B h x 45o A A1 E L L3 e PLANE 2 PLANE 1

0.010 E HS S

0.010 E FS S

-E-

0.007 E FM S HS

-H- -F- J44.A MIL-STD-1835 CQCC1-N44 (C-5)

44 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE

A 0.064 0.120 1.63 3.05 6, 7 A1 0.054 0.088 1.37 2.24 - B 0.033 0.039 0.84 0.99 4 B1 0.022 0.028 0.56 0.71 2, 4 B2 0.072 REF 1.83 REF - B3 0.006 0.022 0.15 0.56 - D 0.640 0.662 16.26 16.81 - D1 0.500 BSC 12.70 BSC - D2 0.250 BSC 6.35 BSC - D3 - 0.662 - 16.81 2 E 0.640 0.662 16.26 16.81 - E1 0.500 BSC 12.70 BSC - E2 0.250 BSC 6.35 BSC - E3 - 0.662 - 16.81 2 e 0.050 BSC 1.27 BSC - e1 0.015 - 0.38 - 2 h 0.040 REF 1.02 REF 5 j 0.020 REF 0.51 REF 5 L 0.045 0.055 1.14 1.40 - L1 0.045 0.055 1.14 1.40 - L2 0.075 0.095 1.90 2.41 - L3 0.003 0.015 0.08 0.38 - ND 11 11 3 NE 11 11 3 N4 4 4 4 3 Rev. 0 5/18/94 NOTES: 1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. 2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. Symbol “N” is the maximum number of terminals. Symbols “ND” and “NE” are the number of terminals along the sides of length “D” and “E”, respectively. 4. The required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer’s option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Dimension “A” controls the overall package thickness. The maxi- mum “A” dimension is package height before being solder dipped. 8. Dimensioning and tolerancing per ANSI Y14.5M-1982. 9. Controlling dimension: INCH.