82C54 INTERSIL | Alldatasheet
Document overview
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Technical content
Features
- 8MHz to 12MHz Clock Input Frequency
- Compatible with NMOS 8254 - Enhanced Version of NMOS 8253
- Three Independent 16-Bit Counters
- Six Programmable Counter Modes
- Status Read Back Command
- Binary or BCD Counting
- Fully TTL Compatible
- Single 5V Power Supply
- Low Power
- Operating Temperature Ranges oC to +70oC
Description
The Intersil 82C54 is a high performance CMOS Program- mable Interval Timer manufactured using an advanced 2 micron CMOS process. The 82C54 has three independently programmable and functional 16-bit counters, each capable of handling clock input frequencies of up to 8MHz (82C54) or 10MHz (82C54-10) or 12MHz (82C54-12). The high speed and industry standard configuration of the 82C54 make it compatible with the Intersil 80C86, 80C88, and 80C286 CMOS microprocessors along with many other industry standard processors. Six programmable timer modes allow the 82C54 to be used as an event counter, elapsed time indicator, programmable one-shot, and many other applications. Static CMOS circuit design insures low power operation. The Intersil advanced CMOS process results in a significant reduction in power with performance equal to or greater than existing equivalent products. Pinouts 82C54 (PDIP, CERDIP, SOIC) TOP VIEW 82C54 (PLCC/CLCC) TOP VIEW CLK 0 OUT 0 GATE 0 GND VCC RD CS OUT 2 CLK 1 GATE 1 OUT 1 WR CLK 2 GATE 2 GND NC OUT 1 GATE 1 CLK 1 OUT 0 GATE 0 NC VCC WR RD CS CLK2 NC GATE 2 OUT 2 1234 12 13 14 15 16 17 18 262728 NC CLK 0 File Number 2970.1CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999
Ordering Information
RANGE PACKAGE PKG. NO.8MHz 10MHz 12MHz CP82C54 CP82C54-10 CP82C54-12 0 oC to +70oC 24 Lead PDIP E24.6 IP82C54 IP82C54-10 IP82C54-12 -40 oC to +85oC 24 Lead PDIP E24.6 CS82C54 CS82C54-10 CS82C54-12 0 oC to +70oC 28 Lead PLCC N28.45 IS82C54 IS82C54-10 IS82C54-12 -40 oC to +85oC 28 Lead PLCC N28.45 CD82C54 CD82C54-10 CD82C54-12 0 oC to +70oC 24 Lead CERDIP F24.6 ID82C54 ID82C54-10 ID82C54-12 -40 oC to +85oC 24 Lead CERDIP F24.6 MD82C54/B MD82C54-10/B MD82C54-12/B -55 oC to +125oC 24 Lead CERDIP F24.6 MR82C54/B MR82C54-10/B MR82C54-12/B -55 oC to +125oC 28 Lead CLCC J28.A SMD # 8406501JA - 8406502JA -55 oC to +125oC 24 Lead CERDIP F24.6 SMD# 84065013A - 84065023A -55 oC to +125oC 28 Lead CLCC J28.A CM82C54 CM82C54-10 CM82C54-12 0 oC to +70oC 24 Lead SOIC M24.3 Pin Description SYMBOL DIP PIN NUMBER TYPE DEFINITION D7 - D0 1 - 8 I/O DATA: Bi-directional three-state data bus lines, connected to system data bus. CLK 0 9 I CLOCK 0: Clock input of Counter 0. OUT 0 10 O OUT 0: Output of Counter 0. GATE 0 11 I GATE 0: Gate input of Counter 0. GND 12 GROUND: Power supply connection. OUT 1 13 O OUT 1: Output of Counter 1. GATE 1 14 I GATE 1: Gate input of Counter 1. CLK 1 15 I CLOCK 1: Clock input of Counter 1. GATE 2 16 I GATE 2: Gate input of Counter 2. OUT 2 17 O OUT 2: Output of Counter 2. CONTROL WORD REGISTER READ/ WRITE LOGIC DATA/ BUS BUFFER COUNTER COUNTER COUNTER INTERNAL BUS INTERNAL BUS CONTROL LOGIC CONTROL WORD REGISTER STATUS LATCH STATUS REGISTER CLK n GATE n OUT n OUT 2 GATE 2 CLK 2 OUT 1 GATE 1 CLK 1 OUT 0 GATE 0 CLK 0 WR RD D 7 - D0 A 0 A 1 CS OL M OL L CE CR M CR L COUNTER INTERNAL BLOCK DIAGRAM 82C54
array of I/O ports in the system software. able length delays can easily be accommodated.
- Real time clock
- Event counter
- Digital one-shot
- Programmable rate generator
- Square wave generator
- Binary rate multiplier
- Complex waveform generator
- Complex motor controller Data Bus Buffer This three-state, bi-directional, 8-bit buffer is used to inter- face the 82C54 to the system bus (see Figure 1). Read/Write Logic The Read/Write Logic accepts inputs from the system bus and generates control signals for the other functional blocks of the 82C54. A1 and A0 select one of the three counters or the Con- trol Word Register to be read from/written into. A “low” on the RD input tells the 82C54 that the CPU is reading one of the counters. A “low” on the WR input tells the 82C54 that the CPU is writing either a Control Word or an initial count. BothRD and WR are qualified byCS; RD and WR are ignored unless the 82C54 has been selected by holdingCS low. CLK 2 18 I CLOCK 2: Clock input of Counter 2. A0, A1 19 - 20 I ADDRESS: Select inputs for one of the three counters or Control Word Register for read/write operations. Normally connected to the system address bus. CS 21 I CHIP SELECT: A low on this input enables the 82C54 to respond to RD and WR signals.RD and WR are ignored otherwise. RD 22 I READ: This input is low during CPU read operations. WR 23 I WRITE: This input is low during CPU write operations. VCC 24 V CC : The +5V power supply pin. A 0.1µF capacitor between pins VCC and GND is recommended for decoupling. Pin Description (Continued) SYMBOL DIP PIN NUMBER TYPE DEFINITION A1 A0 SELECTS 0 0 Counter 0 0 1 Counter 1 1 0 Counter 2 1 1 Control Word Register CONTROL WORD REGISTER COUNTER COUNTER COUNTER INTERNAL BUS OUT 2 GATE 2 CLK 2 OUT 1 GATE 1 CLK 1 OUT 0 GATE 0 CLK 0 WR RD D 7 - D0 A 0 A 1 CS
FIGURE 1. DATA BUS BUFFER AND READ/WRITE LOGIC
Mode, count value, and output of all Counters are undefined. be used. Unused counters need not be programmed. ifies which Counter is being programmed. count is determined by the Control Word used. FIGURE 4. 82C54 SYSTEM INTERFACE The programming procedure for the 82C54 is very flexible.
- For Each Counter, the Control Word must be written
before the initial count is written.
- The initial count must follow the count format specified in the
only, or least significant byte and then most significant byte). sequence that follows the conventions above is acceptable. 0 1 Read/Write least significant byte only. 1 0 Read/Write most significant byte only.
0 Binary Counter 16-bit
1 Binary Coded Decimal (BCD) Counter (4 Decades)
A new initial count may be written to a Counter at any time without affecting the Counter’s programmed Mode in any way. Counting will be affected as described in the Mode definitions. The new count must follow the programmed count format. If a Counter is programmed to read/write two-byte counts, the following precaution applies. A program must not transfer control between writing the first and second byte to another routine which also writes into that same Counter. Otherwise, the Counter will be loaded with an incorrect count. Read Operations It is often desirable to read the value of a Counter without disturbing the count in progress. This is easily done in the 82C54. There are three possible methods for reading the Counters. The first is through the Read-Back command, which is explained later. The second is a simple read operation of the Counter, which is selected with the A1, A0 inputs. The only requirement is that the CLK input of the selected Counter must be inhibited by using either the GATE input or external logic. Otherwise, the count may be in process of changing when it is read, giving an undefined result. Counter Latch Command The other method for reading the Counters involves a spe- cial software command called the “Counter Latch Com- mand”. Like a Control Word, this command is written to the Control Word Register, which is selected when A1, A0 = 11. Also, like a Control Word, the SC0, SC1 bits select one of the three Counters, but two other bits, D5 and D4, distin- guish this command from a Control Word. The selected Counter’s output latch (OL) latches the count when the Counter Latch Command is received. This count is held in the latch until it is read by the CPU (or until the Counter is reprogrammed). The count is then unlatched automatically and the OL returns to “following” the counting element (CE). This allows reading the contents of the Counters “on the fly” without affecting counting in progress. Multiple Counter Latch Commands may be used to latch more than one Counter. Each latched Counter’s OL holds its count until read. Counter Latch Commands do not affect the programmed Mode of the Counter in any way. If a Counter is latched and then, some time later, latched again before the count is read, the second Counter Latch Command is ignored. The count read will be the count at the time the first Counter Latch Command was issued. With either method, the count must be read according to the programmed format; specifically, if the Counter is pro- grammed for two byte counts, two bytes must be read. The two bytes do not have to be read one right after the other; read or write or programming operations of other Counters may be inserted between them. Another feature of the 82C54 is that reads and writes of the same Counter may be interleaved; for example, if the Counter is programmed for two byte counts, the following sequence is valid. LSB of Count - Counter 1 0 1 LSB of Count - Counter 0 0 0 MSB of Count - Counter 0 0 0 MSB of Count - Counter 1 0 1 MSB of Count - Counter 2 1 0 Possible Programming Sequence A1 A0 Control Word - Counter 2 1 1 Control Word - Counter 1 1 1 Control Word - Counter 0 1 1 LSB of Count - Counter 2 1 0 MSB of Count - Counter 2 1 0 LSB of Count - Counter 1 0 1 MSB of Count - Counter 1 0 1 LSB of Count - Counter 0 0 0 MSB of Count - Counter 0 0 0 Possible Programming Sequence A1 A0 Control Word - Counter 1 1 1 Control Word - Counter 0 1 1 LSB of Count - Counter 1 0 1 Control Word - Counter 2 1 1 LSB of Count - Counter 0 0 0 MSB of Count - Counter 1 0 1 LSB of Count - Counter 2 1 0 MSB of Count - Counter 0 0 0 MSB of Count - Counter 2 1 0 NOTE: In all four examples, all counters are programmed to Read/Write two-byte counts. These are only four of many programming sequences. Possible Programming Sequence (Continued) A1 A0 A1, A0 = 11;CS = 0;RD = 1;WR = 0 D7 D6 D5 D4 D3 D2 D1 D0 S C 1 S C 0 00XXXX SC1, SC0 - specify counter to be latched SC1 SC0 COUNTER 00 0 01 1 10 2 1 1 Read-Back Command D5, D4 - 00 designates Counter Latch Command, X - Don’t Care. NOTE: Don’t Care bits (X) should be 0 to insure compatibility with future products. 82C54
- Read least significant byte.
- Write new least significant byte.
- Read most significant byte.
- Write new most significant byte.
another routine which also reads from that same Counter. Otherwise, an incorrect count will be read. and Null Count flag of the selected counter(s). read-back command was issued. accessed by a read from that counter. eliminating some hardware from a system. just written. The operation of Null Count is shown below. count set to 1. Null count bits of other counters are unaffected.
11 COUNT STATUS CNT 2 CNT 1 CNT 0 0
FIGURE 5. READ-BACK COMMAND FORMAT FIGURE 6. STATUS BYTE
11000010 Read-Back Count and Status of Counter 0Count and Status Latched for Counter 0
11100100 Read-Back Status of Counter 1 Status Latched for Counter 1
11101100 Read-Back Status of Counters 2, 1 Status Latched for Counter 2,
11011000 Read-Back Count of Counter 2 Count Latched for Counter 2
11000100 Read-Back Count and Status of Counter 1Count Latched for Counter 1,
11100010 Read-Back Status of Counter 1 Command Ignored, Status Already
ignored. This is illustrated in Figure 7. reads return unlatched count. A rising edge of a Counter’s Gate input. GATE = 1 enables counting; GATE = 0 disables counting. pulses after the initial count is written. immediately (no clock pulse required). loaded on the next CLK pulse. pulses after the new count of N is written. load the counter as this has already been done. FIGURE 9. MODE 0 NOTES: The following conventions apply to all mode timing diagrams.
- Counters are programmed for binary (not BCD) counting and for
reading/writing least significant byte (LSB) only.
- The counter is always selected (CS always low).
- CW stands for “Control Word”; CW = 10 means a control word of
10, Hex is written to the counter.
- LSB stands for Least significant “byte” of count.
- Numbers below diagrams are count values. The lower number is
only, the most significant byte cannot be read.
- N stands for an undefined count.
- Vertical lines show transitions between count values.
01000 Write into Counter 0
01001 Write into Counter 1
01010 Write into Counter 2
01011 Write Control Word
00100 Read from Counter 0
00101 Read from Counter 1
00110 Read from Counter 2
00111 No-Operation (Three-State)
FIGURE 8. READ/WRITE OPERATIONS SUMMARY
of N results in a square wave with a period of N CLK cycles. the GATE input can be used to synchronize the Counter. be synchronized by software also. end of the current half-cycle. FIGURE 12. MODE 3 count. The above process is repeated indefinitely. and then decremented by two on succeeding CLK pulses. high for (N + 1)/2 counts and low for (N - 1)/2 counts. ing sequence is “Triggered” by writing the initial count. GATE = 1 enables counting; GATE = 0 disables counting. low until N + 1 CLK pulses after the initial count is written. (1)Writing the first byte has no effect on counting. loaded on the next CLK pulse. strobes low N + 1 CLK pulses after the new count of N is written.
for binary counting and 104 for BCD counting. FIGURE 15. GATE PIN OPERATIONS SUMMARY FIGURE 16. MINIMUM AND MAXIMUM INITIAL COUNTS
0 Disables Counting - Enables Counting
Absolute Maximum Ratings Thermal Information Operating Conditions Operating Temperature Range oC to +70oC Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W) oC to +150oC Maximum Lead Temperature Package (Soldering 10s) . . . . +300oC (PLCC and SOIC - Lean Tips Only) Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TA = -40oC to +85oC (I82C54, I82C54-10, I82C54-12) TA = -55oC to +125oC (M82C54, M82C54-10, M82C54-12 SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS VIH Logical One Input Voltage 2.0 - V C82C54, I82C54 2.2 - V M82C54 VIL Logical Zero Input Voltage - 0.8 V VOH Output HIGH Voltage 3.0 - V IOH = -2.5mA VCC -0.4 - V IOH = -100 µA VOL Output LOW Voltage - 0.4 V IOL = +2.5mA II Input Leakage Current -1 +1 µA VIN = GND or V CC DIP Pins 9,11,14-16,18-23 IO Output Leakage Current -10 +10 µA VOUT = GND or V CC DIP Pins 1-8 ICCSB Standby Power Supply Current - 10 µAV CC = 5.5V, VIN = GND or VCC , Outputs Open, Counters Programmed ICCOP Operating Power Supply Current - 10 mA V CC = 5.5V, CLK0 = CLK1 = CLK2 = 8MHz, VIN = GND or V CC , Outputs Open Capacitance TA = +25oC; All Measurements Referenced to Device GND, Note 1 SYMBOL PARAMETER TYP UNITS TEST CONDITIONS CIN Input Capacitance 20 pF FREQ = 1MHz COUT Output Capacitance 20 pF FREQ = 1MHz CI/O I/O Capacitance 20 pF FREQ = 1MHz NOTE: 1. Not tested, but characterized at initial design and at major process/design changes. 82C54
TA = -40oC to +85oC (I82C54, I82C54-10, I82C54-12) TA = -55oC to +125oC (M82C54, M82C54-10, M82C54-12) SYMBOL PARAMETER 82C54 82C54-10 82C54-12 UNITS TEST CONDITIONSMIN MAX MIN MAX MIN MAX READ CYCLE (1) TAR Address Stable Before RD 30 - 25 - 25 - ns 1 (2) TSR CS Stable BeforeR D 0-0-0-n s 1 (3) TRA Address Hold Time After R D0-0-0-n s 1 (4) TRR RD Pulse Width 150 - 95 - 95 - ns 1 (5) TRD Data Delay from RD - 120 - 85 - 85 ns 1 (6) TAD Data Delay from Address - 210 - 185 - 185 ns 1 (7) TDF RD to Data Floating 5 85 5 65 5 65 ns 2, Note 1 (8) TRV Command Recovery Time 200 - 165 - 165 - ns WRITE CYCLE (9) TAW Address Stable Before W R 0-0-0-n s (10) TSW CS Stable BeforeW R 0-0-0-n s (11) TWA Address Hold Time After W R 0-0-0-n s (12) TWW WR Pulse Width 95 - 95 - 95 - ns (13) TDW Data Setup Time Before WR 140 - 95 - 95 - ns (14) TWD Data Hold Time After WR 25 - 0 - 0 - ns (15) TRV Command Recovery Time 200 - 165 - 165 - ns CLOCK AND GATE (16) TCLK Clock Period 125 DC 100 DC 80 DC ns 1 (17) TPWH High Pulse Width 60 - 30 - 30 - ns 1 (18) TPWL Low Pulse Width 60 - 40 - 30 - ns 1 (19) TR Clock Rise Time - 25 - 25 - 25 ns (20) TF Clock Fall Time - 25 - 25 - 25 ns (21) TGW Gate Width High 50 - 50 - 50 - ns 1 (22) TGL Gate Width Low 50 - 50 - 50 - ns 1 (23) TGS Gate Setup Time to CLK 50 - 40 - 40 - ns 1 (24) TGH Gate Hold Time After CLK 50 - 50 - 50 - ns 1 (25) TOD Output Delay from CLK - 150 - 100 - 100 ns 1 (26) TODG Output Delay from Gate - 120 - 100 - 100 ns 1 (27) TWO OUT Delay from Mode Write - 260 - 240 - 240 ns 1 (28) TWC CLK Delay for Loading 0 55 0 55 0 55 ns 1 (29) TWG Gate Delay for Sampling -5 40 -5 40 -5 40 ns 1 (30) TCL CLK Setup for Count Latch -40 40 -40 40 -40 40 ns 1 NOTE: 1. Not tested, but characterized at initial design and at major process/design changes. 82C54
NOTES: 1. VCC = 5.5V± 0.5V 2. GND = 0V 3. VIH = 4.5V±10% 4. VIL = -0.2V to 0.4V 5. R1 = 47kΩ± 5% 6. R2 = 1.0kΩ± 5% 7. R3 = 2.7kΩ± 5% 8. R4 = 1.8kΩ± 5% 9. R5 = 1.2kΩ± 5% 10. C1 = 0.01µF Min 11. F0 = 100kHz ±10% VCC GND A A VCC GND F11 A GND F10 F12 VCC A VCC 1911 3 2 14 14 15 16 17 1812 13 28 27 26 VCC/2 Q6 GND OPEN VCC/2 F1Q7 GND OPEN VCC/2 F10 F11 OPEN GND F12 R5 R1 R5 R1 R2 R1R1R1R1R1 VCC Q2 Q1 OPEN Q3 VCC VCC 82C54
All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Die Characteristics DIE DIMENSIONS: 129mils x 155mils x 19mils (3270µm x 3940µm x 483µm) METALLIZATION: Type: Si-Al-Cu Thickness: Metal 1: 8k Å ± 0.75kÅ Metal 2: 12kÅ ± 1.0kÅ GLASSIVATION: Type: Nitrox Thickness: 10k Å ± 3.0kÅ Metallization Mask Layout 82C54 CS CLK2 OUT2 GATE2 CLK0 D5 D6 D7 VCC WR RD OUT0 GATE0 GND OUT1 GATE1 CLK1 82C54